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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [bench/] [ATMEL_FLASH/] [flash_verilog/] [flash_verilog_w_wo_hold/] [testbench_AT26DFx.v] - Blame information for rev 12

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//--------------------------------------------------------------------------
// This is the property of PERFTRENDS TECHNOLOGIES PRIVATE LIMITED and
// possession or use of file has to be with the written LICENCE AGGREMENT
// from PERFTRENDS TECHNOLOGIES PRIVATE LIMITED.
//
//--------------------------------------------------------------------------
//
// Project : ATMEL Data Flash Device
//--------------------------------------------------------------------------
// File         : $RCSfile: testbench_AT26DFx.v,v $
// Path         : $Source: /home/cvs/atmel_flash_dev/design_26x/testbench_AT26DFx.v,v $
// Author       : $ Devi Vasumathy N $
// Created on   : $ 26-03-07 $
// Revision     : $Revision: 1.5 $
// Last modified by : $Author: devivasumathy $
// Last modified on : $Date: 2007/04/16 06:24:44 $
//--------------------------------------------------------------------------
// Module               : AT26DFxxx.v
// Description          : testbench for devices AT26F004, AT26DF081A, 
//                        AT26DF161A, AT26DF321
//
//--------------------------------------------------------------------------
//
// Design hierarchy : _top.v/top_1.v/top_2.v/...
// Instantiated Modules : top_1.v, top_2.v
//--------------------------------------------------------------------------
// Revision history :
// $Log: testbench_AT26DFx.v,v $
// Revision 1.5  2007/04/16 06:24:44  devivasumathy
// *** empty log message ***
//
// Revision 1.4  2007/04/10 09:37:36  devivasumathy
// *** empty log message ***
//
// Revision 1.3  2007/04/09 12:06:09  devivasumathy
// *** empty log message ***
//
// Revision 1.2  2007/04/05 14:45:12  devivasumathy
// *** empty log message ***
//
// Revision 1.1  2007/04/05 11:32:55  devivasumathy
// AT26DFx data flash model testbench
//
//--------------------------------------------------------------------------
 
// module declarations
module AT26DFx_testbench(
                        clk,
                        HOLDB,
                        SO_data,
                        tr_read_stat,
                        tr_write_stat,
                        tr_wr_en,
                        tr_wr_dis,
                        tr_man,
                        tr_pwr_dwn,
                        tr_res_pwr_dwn,
                        tr_byt_prog,
                        tr_rd_array,
                        tr_rd_array_l,
                        tr_seq_byt,
                        tr_protect,
                        tr_unprotect,
                        tr_rd_protect,
                        tr_be4,
                        tr_be32,
                        tr_be64,
                        tr_ce,
                        data_num,
                        no_addr,
                        m_address,
                        w_data,
                        serial_in,
                        out_data);
 
// input declarations
input clk;              // Clock input
input HOLDB;            // Hold
input SO_data;          // SO from BFM
input tr_read_stat;     // trigger for read status reg
input tr_write_stat;    // trigger for write status reg
input tr_wr_en;         // trigger for Write Enable
input tr_wr_dis;        // trigger for Write Disable
input tr_man;           // trigger for read Manufacturer ID
input tr_pwr_dwn;       // trigger for Deep Power-Down
input tr_res_pwr_dwn;   // trigger for resume from Deep Power-Down
input tr_byt_prog;      // trigger for Byte programming
input tr_rd_array;      // trigger for Read array
input tr_rd_array_l;    // trigger for Read array in low frequeny
input tr_seq_byt;       // trigger for Sequential programming
input tr_protect;       // trigger for Protect sector
input tr_unprotect;     // trigger for Unprotect sector
input tr_rd_protect;    // trigger for read protection register
input tr_be4;           // trigger for 4KB Block erase
input tr_be32;          // trigger for 32KB Block erase
input tr_be64;          // trigger for 64KB Block erase
input tr_ce;            // trigger for Chip erase
input [8:0] data_num;    // no. of data to be transmitted/read
input no_addr;          // No address for consecutive sequential programming
input [23:0] m_address; // address for protect/unprotect/read arrays/programming/erase
input [7:0] w_data;      // write data for Byte programming / Sequential programming
 
// output declarations
output serial_in;       // SI for BFM
output [7:0] out_data;   // data from read array to top
 
// Output-reg declarations
reg [7:0] out_data;
reg serial_in;
 
// parameters for SI related delay
parameter tDS     = 2 ;         // Data in Setup time
parameter tDH     = 3 ;         // Data in Hold time
 
// opcode registers
reg [7:0] read_status;           // opcode for read status reg
reg [7:0] wite_status;           // opcode for write status reg
reg [7:0] write_enable;          // opcode for Write Enable
reg [7:0] write_disable; // opcode for Write Disable
reg [7:0] manufacturer;          // opcode for Manufacturer ID
reg [7:0] deep_power_down;       // opcode for Deep Power-Down
reg [7:0] res_deep_power;        // opcode for resume from Deep Power-Down
reg [7:0] byte_program;          // opcode for Byte programming
reg [7:0] read_array;            // opcode for Read array
reg [7:0] read_array_l;          // opcode for Read array in low frequeny
reg [7:0] seq_program;           // opcode for Sequential programming
reg [7:0] protect;               // opcode for Protect sector
reg [7:0] unprotect;             // opcode for Unprotect sector
reg [7:0] read_protect;          // opcode for read protection register
reg [7:0] erase_4;               // opcode for 4KB Block erase
reg [7:0] erase_32;              // opcode for 32KB Block erase
reg [7:0] erase_64;              // opcode for 64KB Block erase
reg [7:0] chip_erase;            // opcode for Chip erase
integer i,j;
reg [7:0] x_val;         // dont care values for Read array in low frequeny
 
// events for all the opcodes
event read_stat;
event wr_en;
event wr_dis;
event manufact;
event pwr_dwn;
event res_pwr_dwn;
event byt_prog;
event rd_array;
event rd_array_l;
event seq_byte;
event protect_sector;
event unprotect_sector;
event read_sector;
event write_stat;
event erase4;
event erase32;
event erase64;
event erase_chip;
 
initial
begin
        serial_in       = 1'b1;
        x_val           = 8'bx;
        read_status     = 8'h05;
        write_enable    = 8'h06;
        write_disable   = 8'h04;
        manufacturer    = 8'h9F;
        deep_power_down = 8'hB9;
        res_deep_power  = 8'hAB;
        byte_program    = 8'h02;
        read_array      = 8'h0B;
        read_array_l    = 8'h03;
        seq_program     = 8'hAF;
        protect         = 8'h36;
        unprotect       = 8'h39;
        read_protect    = 8'h3C;
        wite_status     = 8'h01;
        erase_4         = 8'h20;
        erase_32        = 8'h52;
        erase_64        = 8'hD8;
        chip_erase      = 8'hC7;
 
        out_data        = 8'b0;
 
end
 
// trigger particular opcode,address and data sending event
always @(tr_read_stat or tr_write_stat or tr_wr_en or tr_wr_dis or
        tr_man or tr_pwr_dwn or tr_res_pwr_dwn or
        tr_byt_prog or tr_seq_byt or
        tr_rd_array or tr_rd_array_l or
        tr_protect or tr_unprotect or tr_rd_protect or
        tr_be4 or tr_be32 or tr_be64 or tr_ce)
begin
        if(tr_byt_prog==1'b1)
                -> byt_prog;
        else if(tr_seq_byt==1'b1)
                -> seq_byte;
        else if(tr_protect==1'b1)
                -> protect_sector;
        else if(tr_unprotect==1'b1)
                -> unprotect_sector;
        else if(tr_rd_protect==1'b1)
                -> read_sector;
        else if(tr_rd_array==1'b1)
                -> rd_array;
        else if(tr_rd_array_l==1'b1)
                -> rd_array_l;
        else if(tr_read_stat==1'b1)
                -> read_stat;
        else if(tr_write_stat==1'b1)
                -> write_stat;
        else if(tr_wr_en==1'b1)
                -> wr_en;
        else if(tr_wr_dis==1'b1)
                -> wr_dis;
        else if(tr_man==1'b1)
                -> manufact;
        else if(tr_pwr_dwn==1'b1)
                -> pwr_dwn;
        else if(tr_res_pwr_dwn==1'b1)
                -> res_pwr_dwn;
        else if(tr_be4==1'b1)
                -> erase4;
        else if(tr_be32==1'b1)
                -> erase32;
        else if(tr_be64==1'b1)
                -> erase64;
        else if(tr_ce==1'b1)
                -> erase_chip;
end
 
always @(read_stat)
begin
        for (i=8; i > 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = read_status[i-1];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        serial_in = 1'bz;
end
 
always @(wr_en)
begin
        for (i=8; i > 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = write_enable[i-1];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        serial_in = 1'bz;
end
 
always @(wr_dis)
begin
        for (i=8; i > 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = write_disable[i-1];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        serial_in = 1'bz;
end
 
always @(manufact)
begin
        for (i=8; i > 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = manufacturer[i-1];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        serial_in = 1'bz;
end
 
always @(pwr_dwn)
begin
        for (i=8; i > 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = deep_power_down[i-1];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        serial_in = 1'bz;
end
 
always @(res_pwr_dwn)
begin
        for (i=8; i > 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = res_deep_power[i-1];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        serial_in = 1'bz;
end
 
always @(byt_prog)
begin
        for (i=8; i > 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = byte_program[i-1];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        for (i=23; i >= 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = m_address[i];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        for(j=0; j<data_num; j=j+1)
        begin
                for (i=7; i >= 0; i=i-1)
                begin
                        @ (negedge clk);
                        #tDS;
                        serial_in = w_data[i];
                        @ (posedge clk);
                        #tDH;
                        serial_in = 1'bx;
                        if(HOLDB==1'b0)
                                wait (HOLDB);
                end
        end
        j=0;
        serial_in = 1'bz;
end
 
always @(rd_array)
begin
        for (i=8; i > 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = read_array[i-1];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        for (i=23; i >= 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = m_address[i];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait(HOLDB);
        end
        for (i=7; i >= 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = x_val[i];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        serial_in = 1'bz;
        for(j=0; j<data_num; j=j+1)// to receive data from model
        begin
                for (i=8; i > 0; i=i-1)
                begin
                        @ (posedge clk);
                        out_data[i-1] = SO_data;
                end
        end
        j=0;
end
 
always @(rd_array_l)
begin
        for (i=8; i > 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = read_array_l[i-1];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        for (i=23; i >= 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = m_address[i];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        serial_in = 1'bz;
        for(j=0; j<data_num; j=j+1)// to receive data from model
        begin
                for (i=8; i > 0; i=i-1)
                begin
                        @ (posedge clk);
                        out_data[i-1] = SO_data;
                end
        end
        j=0;
end
 
always @(seq_byte)
begin
        for (i=8; i > 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = seq_program[i-1];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        if(no_addr==1'b0)
            for (i=23; i >= 0; i=i-1)
            begin
                @ (negedge clk);
                #tDS;
                serial_in = m_address[i];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
            end
        for (i=7; i >= 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = w_data[i];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        serial_in = 1'bz;
end
 
always @(protect_sector)
begin
        for (i=8; i > 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = protect[i-1];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        for (i=23; i >= 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = m_address[i];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        serial_in = 1'bz;
end
 
always @(unprotect_sector)
begin
        for (i=8; i > 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = unprotect[i-1];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        for (i=23; i >= 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = m_address[i];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        serial_in = 1'bz;
end
 
always @(read_sector)
begin
        for (i=8; i > 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = read_protect[i-1];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        for (i=23; i >= 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = m_address[i];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        serial_in = 1'bz;
end
 
always @(write_stat)
begin
        for (i=8; i > 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = wite_status[i-1];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        for (i=7; i >= 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = w_data[i];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        serial_in = 1'bz;
end
 
always @(erase4)
begin
        for (i=8; i > 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = erase_4[i-1];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        for (i=23; i >= 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = m_address[i];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        serial_in = 1'bz;
end
 
always @(erase32)
begin
        for (i=8; i > 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = erase_32[i-1];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        for (i=23; i >= 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = m_address[i];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        serial_in = 1'bz;
end
 
always @(erase64)
begin
        for (i=8; i > 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = erase_64[i-1];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        for (i=23; i >= 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = m_address[i];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        serial_in = 1'bz;
end
 
always @(erase_chip)
begin
        for (i=8; i > 0; i=i-1)
        begin
                @ (negedge clk);
                #tDS;
                serial_in = chip_erase[i-1];
                @ (posedge clk);
                #tDH;
                serial_in = 1'bx;
                if(HOLDB==1'b0)
                        wait (HOLDB);
        end
        serial_in = 1'bz;
end
 
endmodule

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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [bench/] [ATMEL_FLASH/] [flash_verilog/] [flash_verilog_w_wo_hold/] [testbench_AT26DFx.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	xianfeng	`//--------------------------------------------------------------------------`
2			`// This is the property of PERFTRENDS TECHNOLOGIES PRIVATE LIMITED and`
3			`// possession or use of file has to be with the written LICENCE AGGREMENT`
4			`// from PERFTRENDS TECHNOLOGIES PRIVATE LIMITED.`
5			`//`
6			`//--------------------------------------------------------------------------`
7			`//`
8			`// Project : ATMEL Data Flash Device`
9			`//--------------------------------------------------------------------------`
10			`// File : $RCSfile: testbench_AT26DFx.v,v $`
11			`// Path : $Source: /home/cvs/atmel_flash_dev/design_26x/testbench_AT26DFx.v,v $`
12			`// Author : $ Devi Vasumathy N $`
13			`// Created on : $ 26-03-07 $`
14			`// Revision : $Revision: 1.5 $`
15			`// Last modified by : $Author: devivasumathy $`
16			`// Last modified on : $Date: 2007/04/16 06:24:44 $`
17			`//--------------------------------------------------------------------------`
18			`// Module : AT26DFxxx.v`
19			`// Description : testbench for devices AT26F004, AT26DF081A,`
20			`// AT26DF161A, AT26DF321`
21			`//`
22			`//--------------------------------------------------------------------------`
23			`//`
24			`// Design hierarchy : _top.v/top_1.v/top_2.v/...`
25			`// Instantiated Modules : top_1.v, top_2.v`
26			`//--------------------------------------------------------------------------`
27			`// Revision history :`
28			`// $Log: testbench_AT26DFx.v,v $`
29			`// Revision 1.5 2007/04/16 06:24:44 devivasumathy`
30			`// * empty log message *`
31			`//`
32			`// Revision 1.4 2007/04/10 09:37:36 devivasumathy`
33			`// * empty log message *`
34			`//`
35			`// Revision 1.3 2007/04/09 12:06:09 devivasumathy`
36			`// * empty log message *`
37			`//`
38			`// Revision 1.2 2007/04/05 14:45:12 devivasumathy`
39			`// * empty log message *`
40			`//`
41			`// Revision 1.1 2007/04/05 11:32:55 devivasumathy`
42			`// AT26DFx data flash model testbench`
43			`//`
44			`//--------------------------------------------------------------------------`
45
46			`// module declarations`
47			`module AT26DFx_testbench(`
48			`clk,`
49			`HOLDB,`
50			`SO_data,`
51			`tr_read_stat,`
52			`tr_write_stat,`
53			`tr_wr_en,`
54			`tr_wr_dis,`
55			`tr_man,`
56			`tr_pwr_dwn,`
57			`tr_res_pwr_dwn,`
58			`tr_byt_prog,`
59			`tr_rd_array,`
60			`tr_rd_array_l,`
61			`tr_seq_byt,`
62			`tr_protect,`
63			`tr_unprotect,`
64			`tr_rd_protect,`
65			`tr_be4,`
66			`tr_be32,`
67			`tr_be64,`
68			`tr_ce,`
69			`data_num,`
70			`no_addr,`
71			`m_address,`
72			`w_data,`
73			`serial_in,`
74			`out_data);`
75
76			`// input declarations`
77			`input clk; // Clock input`
78			`input HOLDB; // Hold`
79			`input SO_data; // SO from BFM`
80			`input tr_read_stat; // trigger for read status reg`
81			`input tr_write_stat; // trigger for write status reg`
82			`input tr_wr_en; // trigger for Write Enable`
83			`input tr_wr_dis; // trigger for Write Disable`
84			`input tr_man; // trigger for read Manufacturer ID`
85			`input tr_pwr_dwn; // trigger for Deep Power-Down`
86			`input tr_res_pwr_dwn; // trigger for resume from Deep Power-Down`
87			`input tr_byt_prog; // trigger for Byte programming`
88			`input tr_rd_array; // trigger for Read array`
89			`input tr_rd_array_l; // trigger for Read array in low frequeny`
90			`input tr_seq_byt; // trigger for Sequential programming`
91			`input tr_protect; // trigger for Protect sector`
92			`input tr_unprotect; // trigger for Unprotect sector`
93			`input tr_rd_protect; // trigger for read protection register`
94			`input tr_be4; // trigger for 4KB Block erase`
95			`input tr_be32; // trigger for 32KB Block erase`
96			`input tr_be64; // trigger for 64KB Block erase`
97			`input tr_ce; // trigger for Chip erase`
98			`input [8:0] data_num; // no. of data to be transmitted/read`
99			`input no_addr; // No address for consecutive sequential programming`
100			`input [23:0] m_address; // address for protect/unprotect/read arrays/programming/erase`
101			`input [7:0] w_data; // write data for Byte programming / Sequential programming`
102
103			`// output declarations`
104			`output serial_in; // SI for BFM`
105			`output [7:0] out_data; // data from read array to top`
106
107			`// Output-reg declarations`
108			`reg [7:0] out_data;`
109			`reg serial_in;`
110
111			`// parameters for SI related delay`
112			`parameter tDS = 2 ; // Data in Setup time`
113			`parameter tDH = 3 ; // Data in Hold time`
114
115			`// opcode registers`
116			`reg [7:0] read_status; // opcode for read status reg`
117			`reg [7:0] wite_status; // opcode for write status reg`
118			`reg [7:0] write_enable; // opcode for Write Enable`
119			`reg [7:0] write_disable; // opcode for Write Disable`
120			`reg [7:0] manufacturer; // opcode for Manufacturer ID`
121			`reg [7:0] deep_power_down; // opcode for Deep Power-Down`
122			`reg [7:0] res_deep_power; // opcode for resume from Deep Power-Down`
123			`reg [7:0] byte_program; // opcode for Byte programming`
124			`reg [7:0] read_array; // opcode for Read array`
125			`reg [7:0] read_array_l; // opcode for Read array in low frequeny`
126			`reg [7:0] seq_program; // opcode for Sequential programming`
127			`reg [7:0] protect; // opcode for Protect sector`
128			`reg [7:0] unprotect; // opcode for Unprotect sector`
129			`reg [7:0] read_protect; // opcode for read protection register`
130			`reg [7:0] erase_4; // opcode for 4KB Block erase`
131			`reg [7:0] erase_32; // opcode for 32KB Block erase`
132			`reg [7:0] erase_64; // opcode for 64KB Block erase`
133			`reg [7:0] chip_erase; // opcode for Chip erase`
134			`integer i,j;`
135			`reg [7:0] x_val; // dont care values for Read array in low frequeny`
136
137			`// events for all the opcodes`
138			`event read_stat;`
139			`event wr_en;`
140			`event wr_dis;`
141			`event manufact;`
142			`event pwr_dwn;`
143			`event res_pwr_dwn;`
144			`event byt_prog;`
145			`event rd_array;`
146			`event rd_array_l;`
147			`event seq_byte;`
148			`event protect_sector;`
149			`event unprotect_sector;`
150			`event read_sector;`
151			`event write_stat;`
152			`event erase4;`
153			`event erase32;`
154			`event erase64;`
155			`event erase_chip;`
156
157			`initial`
158			`begin`
159			`serial_in = 1'b1;`
160			`x_val = 8'bx;`
161			`read_status = 8'h05;`
162			`write_enable = 8'h06;`
163			`write_disable = 8'h04;`
164			`manufacturer = 8'h9F;`
165			`deep_power_down = 8'hB9;`
166			`res_deep_power = 8'hAB;`
167			`byte_program = 8'h02;`
168			`read_array = 8'h0B;`
169			`read_array_l = 8'h03;`
170			`seq_program = 8'hAF;`
171			`protect = 8'h36;`
172			`unprotect = 8'h39;`
173			`read_protect = 8'h3C;`
174			`wite_status = 8'h01;`
175			`erase_4 = 8'h20;`
176			`erase_32 = 8'h52;`
177			`erase_64 = 8'hD8;`
178			`chip_erase = 8'hC7;`
179
180			`out_data = 8'b0;`
181
182			`end`
183
184			`// trigger particular opcode,address and data sending event`
185			`always @(tr_read_stat or tr_write_stat or tr_wr_en or tr_wr_dis or`
186			`tr_man or tr_pwr_dwn or tr_res_pwr_dwn or`
187			`tr_byt_prog or tr_seq_byt or`
188			`tr_rd_array or tr_rd_array_l or`
189			`tr_protect or tr_unprotect or tr_rd_protect or`
190			`tr_be4 or tr_be32 or tr_be64 or tr_ce)`
191			`begin`
192			`if(tr_byt_prog==1'b1)`
193			`-> byt_prog;`
194			`else if(tr_seq_byt==1'b1)`
195			`-> seq_byte;`
196			`else if(tr_protect==1'b1)`
197			`-> protect_sector;`
198			`else if(tr_unprotect==1'b1)`
199			`-> unprotect_sector;`
200			`else if(tr_rd_protect==1'b1)`
201			`-> read_sector;`
202			`else if(tr_rd_array==1'b1)`
203			`-> rd_array;`
204			`else if(tr_rd_array_l==1'b1)`
205			`-> rd_array_l;`
206			`else if(tr_read_stat==1'b1)`
207			`-> read_stat;`
208			`else if(tr_write_stat==1'b1)`
209			`-> write_stat;`
210			`else if(tr_wr_en==1'b1)`
211			`-> wr_en;`
212			`else if(tr_wr_dis==1'b1)`
213			`-> wr_dis;`
214			`else if(tr_man==1'b1)`
215			`-> manufact;`
216			`else if(tr_pwr_dwn==1'b1)`
217			`-> pwr_dwn;`
218			`else if(tr_res_pwr_dwn==1'b1)`
219			`-> res_pwr_dwn;`
220			`else if(tr_be4==1'b1)`
221			`-> erase4;`
222			`else if(tr_be32==1'b1)`
223			`-> erase32;`
224			`else if(tr_be64==1'b1)`
225			`-> erase64;`
226			`else if(tr_ce==1'b1)`
227			`-> erase_chip;`
228			`end`
229
230			`always @(read_stat)`
231			`begin`
232			`for (i=8; i > 0; i=i-1)`
233			`begin`
234			`@ (negedge clk);`
235			`#tDS;`
236			`serial_in = read_status[i-1];`
237			`@ (posedge clk);`
238			`#tDH;`
239			`serial_in = 1'bx;`
240			`if(HOLDB==1'b0)`
241			`wait (HOLDB);`
242			`end`
243			`serial_in = 1'bz;`
244			`end`
245
246			`always @(wr_en)`
247			`begin`
248			`for (i=8; i > 0; i=i-1)`
249			`begin`
250			`@ (negedge clk);`
251			`#tDS;`
252			`serial_in = write_enable[i-1];`
253			`@ (posedge clk);`
254			`#tDH;`
255			`serial_in = 1'bx;`
256			`if(HOLDB==1'b0)`
257			`wait (HOLDB);`
258			`end`
259			`serial_in = 1'bz;`
260			`end`
261
262			`always @(wr_dis)`
263			`begin`
264			`for (i=8; i > 0; i=i-1)`
265			`begin`
266			`@ (negedge clk);`
267			`#tDS;`
268			`serial_in = write_disable[i-1];`
269			`@ (posedge clk);`
270			`#tDH;`
271			`serial_in = 1'bx;`
272			`if(HOLDB==1'b0)`
273			`wait (HOLDB);`
274			`end`
275			`serial_in = 1'bz;`
276			`end`
277
278			`always @(manufact)`
279			`begin`
280			`for (i=8; i > 0; i=i-1)`
281			`begin`
282			`@ (negedge clk);`
283			`#tDS;`
284			`serial_in = manufacturer[i-1];`
285			`@ (posedge clk);`
286			`#tDH;`
287			`serial_in = 1'bx;`
288			`if(HOLDB==1'b0)`
289			`wait (HOLDB);`
290			`end`
291			`serial_in = 1'bz;`
292			`end`
293
294			`always @(pwr_dwn)`
295			`begin`
296			`for (i=8; i > 0; i=i-1)`
297			`begin`
298			`@ (negedge clk);`
299			`#tDS;`
300			`serial_in = deep_power_down[i-1];`
301			`@ (posedge clk);`
302			`#tDH;`
303			`serial_in = 1'bx;`
304			`if(HOLDB==1'b0)`
305			`wait (HOLDB);`
306			`end`
307			`serial_in = 1'bz;`
308			`end`
309
310			`always @(res_pwr_dwn)`
311			`begin`
312			`for (i=8; i > 0; i=i-1)`
313			`begin`
314			`@ (negedge clk);`
315			`#tDS;`
316			`serial_in = res_deep_power[i-1];`
317			`@ (posedge clk);`
318			`#tDH;`
319			`serial_in = 1'bx;`
320			`if(HOLDB==1'b0)`
321			`wait (HOLDB);`
322			`end`
323			`serial_in = 1'bz;`
324			`end`
325
326			`always @(byt_prog)`
327			`begin`
328			`for (i=8; i > 0; i=i-1)`
329			`begin`
330			`@ (negedge clk);`
331			`#tDS;`
332			`serial_in = byte_program[i-1];`
333			`@ (posedge clk);`
334			`#tDH;`
335			`serial_in = 1'bx;`
336			`if(HOLDB==1'b0)`
337			`wait (HOLDB);`
338			`end`
339			`for (i=23; i >= 0; i=i-1)`
340			`begin`
341			`@ (negedge clk);`
342			`#tDS;`
343			`serial_in = m_address[i];`
344			`@ (posedge clk);`
345			`#tDH;`
346			`serial_in = 1'bx;`
347			`if(HOLDB==1'b0)`
348			`wait (HOLDB);`
349			`end`
350			`for(j=0; j<data_num; j=j+1)`
351			`begin`
352			`for (i=7; i >= 0; i=i-1)`
353			`begin`
354			`@ (negedge clk);`
355			`#tDS;`
356			`serial_in = w_data[i];`
357			`@ (posedge clk);`
358			`#tDH;`
359			`serial_in = 1'bx;`
360			`if(HOLDB==1'b0)`
361			`wait (HOLDB);`
362			`end`
363			`end`
364			`j=0;`
365			`serial_in = 1'bz;`
366			`end`
367
368			`always @(rd_array)`
369			`begin`
370			`for (i=8; i > 0; i=i-1)`
371			`begin`
372			`@ (negedge clk);`
373			`#tDS;`
374			`serial_in = read_array[i-1];`
375			`@ (posedge clk);`
376			`#tDH;`
377			`serial_in = 1'bx;`
378			`if(HOLDB==1'b0)`
379			`wait (HOLDB);`
380			`end`
381			`for (i=23; i >= 0; i=i-1)`
382			`begin`
383			`@ (negedge clk);`
384			`#tDS;`
385			`serial_in = m_address[i];`
386			`@ (posedge clk);`
387			`#tDH;`
388			`serial_in = 1'bx;`
389			`if(HOLDB==1'b0)`
390			`wait(HOLDB);`
391			`end`
392			`for (i=7; i >= 0; i=i-1)`
393			`begin`
394			`@ (negedge clk);`
395			`#tDS;`
396			`serial_in = x_val[i];`
397			`@ (posedge clk);`
398			`#tDH;`
399			`serial_in = 1'bx;`
400			`if(HOLDB==1'b0)`
401			`wait (HOLDB);`
402			`end`
403			`serial_in = 1'bz;`
404			`for(j=0; j<data_num; j=j+1)// to receive data from model`
405			`begin`
406			`for (i=8; i > 0; i=i-1)`
407			`begin`
408			`@ (posedge clk);`
409			`out_data[i-1] = SO_data;`
410			`end`
411			`end`
412			`j=0;`
413			`end`
414
415			`always @(rd_array_l)`
416			`begin`
417			`for (i=8; i > 0; i=i-1)`
418			`begin`
419			`@ (negedge clk);`
420			`#tDS;`
421			`serial_in = read_array_l[i-1];`
422			`@ (posedge clk);`
423			`#tDH;`
424			`serial_in = 1'bx;`
425			`if(HOLDB==1'b0)`
426			`wait (HOLDB);`
427			`end`
428			`for (i=23; i >= 0; i=i-1)`
429			`begin`
430			`@ (negedge clk);`
431			`#tDS;`
432			`serial_in = m_address[i];`
433			`@ (posedge clk);`
434			`#tDH;`
435			`serial_in = 1'bx;`
436			`if(HOLDB==1'b0)`
437			`wait (HOLDB);`
438			`end`
439			`serial_in = 1'bz;`
440			`for(j=0; j<data_num; j=j+1)// to receive data from model`
441			`begin`
442			`for (i=8; i > 0; i=i-1)`
443			`begin`
444			`@ (posedge clk);`
445			`out_data[i-1] = SO_data;`
446			`end`
447			`end`
448			`j=0;`
449			`end`
450
451			`always @(seq_byte)`
452			`begin`
453			`for (i=8; i > 0; i=i-1)`
454			`begin`
455			`@ (negedge clk);`
456			`#tDS;`
457			`serial_in = seq_program[i-1];`
458			`@ (posedge clk);`
459			`#tDH;`
460			`serial_in = 1'bx;`
461			`if(HOLDB==1'b0)`
462			`wait (HOLDB);`
463			`end`
464			`if(no_addr==1'b0)`
465			`for (i=23; i >= 0; i=i-1)`
466			`begin`
467			`@ (negedge clk);`
468			`#tDS;`
469			`serial_in = m_address[i];`
470			`@ (posedge clk);`
471			`#tDH;`
472			`serial_in = 1'bx;`
473			`if(HOLDB==1'b0)`
474			`wait (HOLDB);`
475			`end`
476			`for (i=7; i >= 0; i=i-1)`
477			`begin`
478			`@ (negedge clk);`
479			`#tDS;`
480			`serial_in = w_data[i];`
481			`@ (posedge clk);`
482			`#tDH;`
483			`serial_in = 1'bx;`
484			`if(HOLDB==1'b0)`
485			`wait (HOLDB);`
486			`end`
487			`serial_in = 1'bz;`
488			`end`
489
490			`always @(protect_sector)`
491			`begin`
492			`for (i=8; i > 0; i=i-1)`
493			`begin`
494			`@ (negedge clk);`
495			`#tDS;`
496			`serial_in = protect[i-1];`
497			`@ (posedge clk);`
498			`#tDH;`
499			`serial_in = 1'bx;`
500			`if(HOLDB==1'b0)`
501			`wait (HOLDB);`
502			`end`
503			`for (i=23; i >= 0; i=i-1)`
504			`begin`
505			`@ (negedge clk);`
506			`#tDS;`
507			`serial_in = m_address[i];`
508			`@ (posedge clk);`
509			`#tDH;`
510			`serial_in = 1'bx;`
511			`if(HOLDB==1'b0)`
512			`wait (HOLDB);`
513			`end`
514			`serial_in = 1'bz;`
515			`end`
516
517			`always @(unprotect_sector)`
518			`begin`
519			`for (i=8; i > 0; i=i-1)`
520			`begin`
521			`@ (negedge clk);`
522			`#tDS;`
523			`serial_in = unprotect[i-1];`
524			`@ (posedge clk);`
525			`#tDH;`
526			`serial_in = 1'bx;`
527			`if(HOLDB==1'b0)`
528			`wait (HOLDB);`
529			`end`
530			`for (i=23; i >= 0; i=i-1)`
531			`begin`
532			`@ (negedge clk);`
533			`#tDS;`
534			`serial_in = m_address[i];`
535			`@ (posedge clk);`
536			`#tDH;`
537			`serial_in = 1'bx;`
538			`if(HOLDB==1'b0)`
539			`wait (HOLDB);`
540			`end`
541			`serial_in = 1'bz;`
542			`end`
543
544			`always @(read_sector)`
545			`begin`
546			`for (i=8; i > 0; i=i-1)`
547			`begin`
548			`@ (negedge clk);`
549			`#tDS;`
550			`serial_in = read_protect[i-1];`
551			`@ (posedge clk);`
552			`#tDH;`
553			`serial_in = 1'bx;`
554			`if(HOLDB==1'b0)`
555			`wait (HOLDB);`
556			`end`
557			`for (i=23; i >= 0; i=i-1)`
558			`begin`
559			`@ (negedge clk);`
560			`#tDS;`
561			`serial_in = m_address[i];`
562			`@ (posedge clk);`
563			`#tDH;`
564			`serial_in = 1'bx;`
565			`if(HOLDB==1'b0)`
566			`wait (HOLDB);`
567			`end`
568			`serial_in = 1'bz;`
569			`end`
570
571			`always @(write_stat)`
572			`begin`
573			`for (i=8; i > 0; i=i-1)`
574			`begin`
575			`@ (negedge clk);`
576			`#tDS;`
577			`serial_in = wite_status[i-1];`
578			`@ (posedge clk);`
579			`#tDH;`
580			`serial_in = 1'bx;`
581			`if(HOLDB==1'b0)`
582			`wait (HOLDB);`
583			`end`
584			`for (i=7; i >= 0; i=i-1)`
585			`begin`
586			`@ (negedge clk);`
587			`#tDS;`
588			`serial_in = w_data[i];`
589			`@ (posedge clk);`
590			`#tDH;`
591			`serial_in = 1'bx;`
592			`if(HOLDB==1'b0)`
593			`wait (HOLDB);`
594			`end`
595			`serial_in = 1'bz;`
596			`end`
597
598			`always @(erase4)`
599			`begin`
600			`for (i=8; i > 0; i=i-1)`
601			`begin`
602			`@ (negedge clk);`
603			`#tDS;`
604			`serial_in = erase_4[i-1];`
605			`@ (posedge clk);`
606			`#tDH;`
607			`serial_in = 1'bx;`
608			`if(HOLDB==1'b0)`
609			`wait (HOLDB);`
610			`end`
611			`for (i=23; i >= 0; i=i-1)`
612			`begin`
613			`@ (negedge clk);`
614			`#tDS;`
615			`serial_in = m_address[i];`
616			`@ (posedge clk);`
617			`#tDH;`
618			`serial_in = 1'bx;`
619			`if(HOLDB==1'b0)`
620			`wait (HOLDB);`
621			`end`
622			`serial_in = 1'bz;`
623			`end`
624
625			`always @(erase32)`
626			`begin`
627			`for (i=8; i > 0; i=i-1)`
628			`begin`
629			`@ (negedge clk);`
630			`#tDS;`
631			`serial_in = erase_32[i-1];`
632			`@ (posedge clk);`
633			`#tDH;`
634			`serial_in = 1'bx;`
635			`if(HOLDB==1'b0)`
636			`wait (HOLDB);`
637			`end`
638			`for (i=23; i >= 0; i=i-1)`
639			`begin`
640			`@ (negedge clk);`
641			`#tDS;`
642			`serial_in = m_address[i];`
643			`@ (posedge clk);`
644			`#tDH;`
645			`serial_in = 1'bx;`
646			`if(HOLDB==1'b0)`
647			`wait (HOLDB);`
648			`end`
649			`serial_in = 1'bz;`
650			`end`
651
652			`always @(erase64)`
653			`begin`
654			`for (i=8; i > 0; i=i-1)`
655			`begin`
656			`@ (negedge clk);`
657			`#tDS;`
658			`serial_in = erase_64[i-1];`
659			`@ (posedge clk);`
660			`#tDH;`
661			`serial_in = 1'bx;`
662			`if(HOLDB==1'b0)`
663			`wait (HOLDB);`
664			`end`
665			`for (i=23; i >= 0; i=i-1)`
666			`begin`
667			`@ (negedge clk);`
668			`#tDS;`
669			`serial_in = m_address[i];`
670			`@ (posedge clk);`
671			`#tDH;`
672			`serial_in = 1'bx;`
673			`if(HOLDB==1'b0)`
674			`wait (HOLDB);`
675			`end`
676			`serial_in = 1'bz;`
677			`end`
678
679			`always @(erase_chip)`
680			`begin`
681			`for (i=8; i > 0; i=i-1)`
682			`begin`
683			`@ (negedge clk);`
684			`#tDS;`
685			`serial_in = chip_erase[i-1];`
686			`@ (posedge clk);`
687			`#tDH;`
688			`serial_in = 1'bx;`
689			`if(HOLDB==1'b0)`
690			`wait (HOLDB);`
691			`end`
692			`serial_in = 1'bz;`
693			`end`
694
695			`endmodule`