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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [bench/] [ATMEL_FLASH/] [flash_verilog/] [flash_verilog_w_wo_hold/] [top26x_testbench.v] - Blame information for rev 12

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1 12 xianfeng 
//--------------------------------------------------------------------------
2 
// This is the property of PERFTRENDS TECHNOLOGIES PRIVATE LIMITED and
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// possession or use of file has to be with the written LICENCE AGGREMENT
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// from PERFTRENDS TECHNOLOGIES PRIVATE LIMITED.
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//
6 
//--------------------------------------------------------------------------
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//
8 
// Project : ATMEL Data Flash Device
9 
//--------------------------------------------------------------------------
10 
// File         : $RCSfile: top26x_testbench.v,v $
11 
// Path         : $Source: /home/cvs/atmel_flash_dev/design_26x/top26x_testbench.v,v $
12 
// Author       : $ Devi Vasumathy N $
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// Created on   : $ 27-03-07 $
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// Revision     : $Revision: 1.11 $
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// Last modified by : $Author: devivasumathy $
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// Last modified on : $Date: 2007/05/10 05:15:51 $
17 
//--------------------------------------------------------------------------
18 
// Module               : AT26DFxxx.v
19 
// Description          : testbench top for devices AT26F004, AT26DF081A,
20 
//                        AT26DF161A, AT26DF321
21 
//
22 
//--------------------------------------------------------------------------
23 
//
24 
// Design hierarchy : _top.v/top_1.v/top_2.v/...
25 
// Instantiated Modules : top_1.v, top_2.v
26 
//--------------------------------------------------------------------------
27 
// Revision history :
28 
// $Log: top26x_testbench.v,v $
29 
// Revision 1.11  2007/05/10 05:15:51  devivasumathy
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// Card Memory preload
31 
//
32 
// Revision 1.10  2007/04/27 09:09:40  devivasumathy
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// *** empty log message ***
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//
35 
// Revision 1.9  2007/04/17 10:50:59  devivasumathy
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// Timing verified
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//
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// Revision 1.8  2007/04/16 06:28:55  devivasumathy
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// *** empty log message ***
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//
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// Revision 1.7  2007/04/16 06:24:44  devivasumathy
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// *** empty log message ***
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//
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// Revision 1.6  2007/04/12 09:43:55  magesh
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// *** empty log message ***
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//
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// Revision 1.5  2007/04/12 05:02:10  devivasumathy
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// AT26x
49 
//
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// Revision 1.4  2007/04/10 09:37:36  devivasumathy
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// *** empty log message ***
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//
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// Revision 1.3  2007/04/09 12:06:09  devivasumathy
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// *** empty log message ***
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//
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// Revision 1.2  2007/04/05 14:45:12  devivasumathy
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// *** empty log message ***
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//
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// Revision 1.1  2007/04/05 11:32:55  devivasumathy
60 
// AT26DFx data flash model testbench
61 
//
62 
//--------------------------------------------------------------------------
63 
`timescale 1 ns / 1 ps
64 
 
65 
module top26x_testbench();
66 
 
67 
reg SCK_gen;            // local clock
68 
 
69 
reg CSB_out;            // CSB signal for BFM
70 
reg WPB_out;            // WPB signal for BFM
71 
reg HOLDB_out;          // HOLDB signal for BFM
72 
wire SCK_out;           // SCK for BFM
73 
wire SO_in;             // SO from BFM
74 
wire SI_out;            // SI for BFM
75 
wire [7:0] out_data;
76 
 
77 
reg trg_read_stat;      // trigger for read status reg
78 
reg trg_write_stat;     // trigger for write status reg;
79 
reg trg_wr_en;          // trigger for Write Enable
80 
reg trg_wr_dis;         // trigger for Write Disable
81 
reg trg_man;            // trigger for read Manufacturer ID
82 
reg trg_pwr_dwn;        // trigger for Deep Power-Down
83 
reg trg_res_pwr_dwn;    // trigger for resume from Deep Power-Down
84 
reg trg_byt_prog;       // trigger for Byte programming
85 
reg trg_rd_array;       // trigger for Read array
86 
reg trg_rd_array_l;     // trigger for Read array in low frequency
87 
reg trg_seq_byt;        // trigger for Sequential programming
88 
reg trg_protect;        // trigger for Protect sector
89 
reg trg_unprotect;      // trigger for Unprotect sector;
90 
reg trg_rd_protect;     // trigger for read protection register
91 
reg trg_be4;            // trigger for 4KB Block erase
92 
reg trg_be32;           // trigger for 32KB Block erase
93 
reg trg_be64;           // trigger for 64KB Block erase
94 
reg trg_ce;             // trigger for Chip erase
95 
reg [8:0] t_data_num;    // no. of data to be transmitted/read
96 
reg t_no_addr;          // No address for consecutive sequential programming
97 
reg [23:0] address;      // address for protect/unprotect/read arrays/programming/erase
98 
reg [7:0] data;          // write data for Byte programming / Sequential programming
99 
 
100 
integer i;
101 
integer j;
102 
integer k;
103 
integer delay;                  // delay for chip erase
104 
reg [7:0] store_data [63:0];      // write data stored here for data validation check
105 
reg [7:0] read_data [63:0];       // read data stored here for data validation check
106 
reg CSB_start;                  // for SPI mode 0; to avoid glitch in SCK
107 
reg CSB_stop;                   // for SPI mode 3; to avoid glitch in SCK
108 
 
109 
`ifdef 041
110 
parameter DEVICE = "AT25DF041A";        // Device selected
111 
`endif
112 
`ifdef 081
113 
parameter DEVICE = "AT26DF081A";
114 
`endif
115 
`ifdef 161
116 
parameter DEVICE = "AT26DF161A";
117 
`endif
118 
`ifdef 321
119 
parameter DEVICE = "AT26DF321";
120 
`endif
121 
 
122 
`ifdef LOAD
123 
        parameter PRELOAD = 1;                  // preload memory with content in MEMORY_FILE
124 
`else
125 
        parameter PRELOAD = 0;                   // preload memory with content in MEMORY_FILE
126 
`endif
127 
 
128 
`ifdef LOAD
129 
        parameter MEMORY_FILE = "memory.txt";   // Memory pre-load
130 
`else
131 
        parameter MEMORY_FILE = 0;               // Memory pre-load
132 
`endif
133 
 
134 
// ********************************************************************* //
135 
//Timing Parameters :
136 
// ******************************************************************** //
137 
parameter fRDLF   = 33;         // SCK Frequency for read Array (Low freq - 03h opcode)
138 
//representation in ns
139 
 
140 
parameter tCSH    = 50;         // Chip Select high time
141 
parameter tCSLS   = 5 ;         // Chip Select Low Setup time
142 
parameter tCSLH   = 5 ;         // Chip Select Low hold time
143 
//parameter tCSLH   = 12;       // (for SPI3)           // Chip Select Low hold time
144 
parameter tCSHS   = 5 ;         // Chip Select high Setup time
145 
parameter tCSHH   = 5 ;         // Chip Select high hold time
146 
 
147 
parameter tDS     = 2 ;         // Data in Setup time
148 
parameter tDH     = 3 ;         // Data in Hold time
149 
 
150 
parameter tHLS    = 5 ;         // HOLD! Low Setup Time
151 
parameter tHHS    = 5 ;         // HOLD! High Setup Time
152 
parameter tHLH    = 5 ;         // HOLD! Low Hold Time
153 
parameter tHHH    = 5 ;         // HOLD! High Hold Time
154 
 
155 
parameter tWPS    = 20;         // Write Protect Setup Time (only when SPRL=1)
156 
parameter tWPH    = 100;        // Write Protect Hold Time (only when SPRL=1)
157 
 
158 
parameter tWRSR   = 200;        // Write Status Register Time
159 
 
160 
parameter tSECP   = 20;         // Sector Protect Time
161 
parameter tSECUP  = 20;         // Sector Unprotect Time
162 
 
163 
parameter tEDPD   = 3000;       // Chip Select high to Deep Power-down (3 us)
164 
parameter tRDPD   = 3000;       // Chip Select high to Stand-by Mode
165 
parameter tPP     = 5000000;    // Page Program Time
166 
parameter tBLKE4  = 200000000;  // Block Erase Time 4-kB (0.350 sec)
167 
parameter tBLKE32 = 600000000;  // Block Erase Time 32-kB
168 
parameter tCHPEn = 1000000000;  // local chip erase time
169 
 
170 
// variable parameters
171 
// ******************************************************************** //
172 
//parameter tBLKE64 = 950000000;        // Block Erase Time 64-kB
173 
//parameter tCHPE   = 3000000000;       // Chip Erase Time. this is actual;
174 
                                        // due to simulation warning splitted into 2 parameters as tCHPE = tmult * tCHPEn
175 
//parameter tmult   = 3;                // Multiplication factor for chip erase timing
176 
 
177 
parameter tBP =         (DEVICE == "AT25DF041A") ? 7000 :
178 
                        (DEVICE == "AT26DF081A") ? 7000 :
179 
                        (DEVICE == "AT26DF161A") ? 7000 :
180 
                        (DEVICE == "AT26DF321")  ? 6000 : 7000;
181 
 
182 
parameter tBLKE64 =     (DEVICE == "AT25DF041A") ? 950000000 :
183 
                        (DEVICE == "AT26DF081A") ? 950000000 :
184 
                        (DEVICE == "AT26DF161A") ? 950000000 :
185 
                        (DEVICE == "AT26DF321")  ? 1000000000 :950000000 ;
186 
 
187 
parameter tmult =       (DEVICE == "AT25DF041A") ? 3 :
188 
                        (DEVICE == "AT26DF081A") ? 6 :
189 
                        (DEVICE == "AT26DF161A") ? 12 :
190 
                        (DEVICE == "AT26DF321")  ? 36 : 3;
191 
 
192 
//parameter fSCK    = 70;               // Serial clock (SCK) Frequency in MHz
193 
//parameter tSCKH   = 6.4;              // SCK High time
194 
//parameter tSCKL   = 6.4;              // SCK Low time
195 
parameter tSCKH   = 8.4;                // SCK High time
196 
parameter tSCKL   = 8.4;                // SCK Low time
197 
 
198 
parameter fSCK =        (DEVICE == "AT25DF041A") ? 70 :
199 
                        (DEVICE == "AT26DF081A") ? 70 :
200 
                        (DEVICE == "AT26DF161A") ? 70 :
201 
                        (DEVICE == "AT26DF321")  ? 66 : 70;
202 
/*
203 
parameter tSCKH =       (DEVICE == "AT25DF041A") ? 6.4 :
204 
                        (DEVICE == "AT26DF081A") ? 6.4 :
205 
                        (DEVICE == "AT26DF161A") ? 6.4 :
206 
                        (DEVICE == "AT26DF321")  ? 6.8 : 6.4;
207 
 
208 
parameter tSCKL =       (DEVICE == "AT25DF041A") ? 6.4 :
209 
                        (DEVICE == "AT26DF081A") ? 6.4 :
210 
                        (DEVICE == "AT26DF161A") ? 6.4 :
211 
                        (DEVICE == "AT26DF321")  ? 6.8 : 6.4;*/
212 
// ******************************************************************** //
213 
 
214 
 
215 
// ******************************************************************** //
216 
// used in Model
217 
//parameter tDIS    = 6;                // Output Disable time
218 
//parameter tV      = 6;                // Output Valid time
219 
//parameter tOH     = 0 ;               // Output Hold time
220 
 
221 
//parameter tHLQZ   = 6 ;               // HOLD! Low to Output High-z
222 
//parameter tHHQX   = 6 ;               // HOLD! High to Output Low-z
223 
// ******************************************************************** //
224 
 
225 
// local clock generation
226 
always
227 
        #(tSCKH) SCK_gen = !SCK_gen;
228 
 
229 
// for SCK
230 
`ifdef MODE3
231 
assign SCK_out = (CSB_out==1'b0) ? SCK_gen : (CSB_stop==1'b1) ? SCK_gen : 1'b1; // SPI mode 3
232 
`else
233 
assign SCK_out = (CSB_out==1'b0) ? SCK_gen : (CSB_start==1'b1) ? SCK_gen : 1'b0; // SPI mode 0
234 
`endif
235 
 
236 
initial
237 
begin
238 
        $dumpvars;
239 
end
240 
 
241 
initial
242 
begin
243 
i = 0;
244 
CSB_start        = 1'b0;
245 
CSB_stop         = 1'b0;
246 
SCK_gen          = 1'b1;
247 
WPB_out          = 1'b1;
248 
HOLDB_out        = 1'b1;
249 
trg_read_stat    = 1'b0;
250 
trg_write_stat   = 1'b0;
251 
trg_wr_en        = 1'b0;
252 
trg_wr_dis       = 1'b0;
253 
trg_man          = 1'b0;
254 
trg_pwr_dwn      = 1'b0;
255 
trg_res_pwr_dwn  = 1'b0;
256 
trg_byt_prog     = 1'b0;
257 
trg_rd_array     = 1'b0;
258 
trg_rd_array_l   = 1'b0;
259 
trg_seq_byt      = 1'b0;
260 
t_no_addr        = 1'b0;
261 
trg_protect      = 1'b0;
262 
trg_unprotect    = 1'b0;
263 
trg_rd_protect   = 1'b0;
264 
trg_be4          = 1'b0;
265 
trg_be32         = 1'b0;
266 
trg_be64         = 1'b0;
267 
trg_ce           = 1'b0;
268 
t_data_num       = 9'b0;
269 
 
270 
CSB_out = 1'b1;
271 
#(11*tSCKH)
272 
 
273 
@(posedge SCK_gen); CSB_start = 1'b1;
274 
#tCSHH
275 
CSB_out = 1'b0;CSB_start = 1'b0;trg_read_stat=1'b1;     // read status register
276 
#(16*tSCKH)
277 
#(38*tSCKH)
278 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1; trg_read_stat=1'b0;
279 
@(posedge SCK_gen);CSB_stop=1'b0;
280 
 
281 
#(4*tSCKH)
282 
@(posedge SCK_gen); CSB_start = 1'b1;
283 
#tCSHH
284 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
285 
#(16*tSCKH);
286 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
287 
@(posedge SCK_gen);CSB_stop=1'b0;
288 
 
289 
#(4*tSCKH)
290 
@(posedge SCK_gen); CSB_start = 1'b1;
291 
#tCSHH
292 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_dis = 1'b1;              // write disable
293 
#(2*tSCKH);
294 
#(16*tSCKH);
295 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_dis = 1'b0;
296 
@(posedge SCK_gen);CSB_stop=1'b0;
297 
 
298 
#(4*tSCKH)
299 
@(posedge SCK_gen); CSB_start = 1'b1;
300 
#tCSHH
301 
CSB_out = 1'b0;CSB_start = 1'b0;trg_man = 1'b1;         // Manufacturer
302 
#(84*tSCKH);
303 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_man = 1'b0;
304 
@(posedge SCK_gen);CSB_stop=1'b0;
305 
 
306 
#(4*tSCKH);
307 
@(posedge SCK_gen); CSB_start = 1'b1;
308 
#tCSHH
309 
CSB_out = 1'b0;CSB_start = 1'b0;trg_pwr_dwn = 1'b1;             // deep power down
310 
#(2*tSCKH);
311 
#(16*tSCKH);
312 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_pwr_dwn = 1'b0;
313 
@(posedge SCK_gen);CSB_stop=1'b0;
314 
#tEDPD;
315 
 
316 
#(4*tSCKH);
317 
@(posedge SCK_gen); CSB_start = 1'b1;
318 
#tCSHH
319 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable - this will not be executed
320 
#(18*tSCKH);
321 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
322 
@(posedge SCK_gen);CSB_stop=1'b0;
323 
 
324 
#(4*tSCKH);
325 
@(posedge SCK_gen); CSB_start = 1'b1;
326 
#tCSHH
327 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h000101; // unprotect sector
328 
#(16*tSCKH);  // for opcode txn
329 
#(48*tSCKH);  // for address txn
330 
#(2*tSCKH);
331 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
332 
@(posedge SCK_gen);CSB_stop=1'b0;
333 
#tSECUP
334 
 
335 
#(4*tSCKH);
336 
@(posedge SCK_gen); CSB_start = 1'b1;
337 
#tCSHH
338 
CSB_out = 1'b0;CSB_start = 1'b0;trg_res_pwr_dwn = 1'b1; // resume deep power down
339 
#(18*tSCKH);
340 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_res_pwr_dwn = 1'b0;
341 
@(posedge SCK_gen);CSB_stop=1'b0;
342 
#tRDPD;
343 
 
344 
#(4*tSCKH);
345 
@(posedge SCK_gen); CSB_start = 1'b1;
346 
#tCSHH
347 
CSB_out = 1'b0;CSB_start = 1'b0;trg_read_stat=1'b1;             // read status register
348 
#(54*tSCKH);
349 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_read_stat=1'b0;
350 
@(posedge SCK_gen);CSB_stop=1'b0;
351 
 
352 
#(4*tSCKH);
353 
@(posedge SCK_gen); CSB_start = 1'b1;
354 
#tCSHH
355 
CSB_out = 1'b0;CSB_start = 1'b0;trg_rd_protect = 1'b1; address = 24'h00010A; // read sector protection
356 
#(16*tSCKH);  // for opcode txn
357 
#(48*tSCKH);  // for address txn
358 
#(20*tSCKH);  // for data txn
359 
#(2*tSCKH);
360 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_rd_protect = 1'b0;
361 
@(posedge SCK_gen);CSB_stop=1'b0;
362 
#tSECP;
363 
///*
364 
$display("****** ****** Byte/Page programming Start ****** ******");
365 
#(4*tSCKH);
366 
 
367 
@(posedge SCK_gen); CSB_start = 1'b1;
368 
#tCSHH
369 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
370 
#(18*tSCKH);
371 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
372 
@(posedge SCK_gen);CSB_stop=1'b0;
373 
 
374 
#(4*tSCKH);
375 
@(posedge SCK_gen); CSB_start = 1'b1;
376 
#tCSHH
377 
CSB_out = 1'b0;CSB_start = 1'b0;trg_byt_prog = 1'b1;address = 24'h00010A;data = 8'h05;t_data_num = 9'b0_0000_0001; //byte program
378 
#(16*tSCKH);  // for opcode txn
379 
#(48*tSCKH);  // for address txn
380 
#(16*tSCKH);  // for data txn
381 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_byt_prog = 1'b0;t_data_num = 9'b0;
382 
@(posedge SCK_gen);CSB_stop=1'b0;
383 
#tPP;
384 
 
385 
#(4*tSCKH);
386 
@(posedge SCK_gen); CSB_start = 1'b1;
387 
#tCSHH
388 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
389 
#(18*tSCKH);
390 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
391 
@(posedge SCK_gen);CSB_stop=1'b0;
392 
 
393 
#(4*tSCKH);
394 
@(posedge SCK_gen); CSB_start = 1'b1;
395 
#tCSHH
396 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h000101; // unprotect sector
397 
#(16*tSCKH);  // for opcode txn
398 
#(48*tSCKH);  // for address txn
399 
#(2*tSCKH);
400 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
401 
@(posedge SCK_gen);CSB_stop=1'b0;
402 
#tSECUP;
403 
 
404 
#(4*tSCKH);
405 
@(posedge SCK_gen); CSB_start = 1'b1;
406 
#tCSHH
407 
CSB_out = 1'b0;CSB_start = 1'b0;trg_byt_prog = 1'b1;address = 24'h00010B;data = 8'h06;t_data_num = 9'b0_0000_0001; //byte program
408 
#(16*tSCKH);  // for opcode txn
409 
#(48*tSCKH);  // for address txn
410 
#(16*tSCKH);  // for data txn
411 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_byt_prog = 1'b0;t_data_num = 9'b0;
412 
@(posedge SCK_gen);CSB_stop=1'b0;
413 
#tPP;
414 
 
415 
#(4*tSCKH);
416 
@(posedge SCK_gen); CSB_start = 1'b1;
417 
#tCSHH
418 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
419 
#(18*tSCKH);
420 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
421 
@(posedge SCK_gen);CSB_stop=1'b0;
422 
 
423 
#(4*tSCKH);
424 
@(posedge SCK_gen); CSB_start = 1'b1;
425 
#tCSHH
426 
CSB_out = 1'b0;CSB_start = 1'b0;trg_byt_prog = 1'b1;address = 24'h000100;data = 8'h04;t_data_num = 9'b0_0000_0010;//byte program
427 
#(16*tSCKH);  // for opcode txn
428 
#(48*tSCKH);  // for address txn
429 
#(16*tSCKH); data = 8'h05;  // for data txn
430 
#(16*tSCKH);  // for data txn
431 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_byt_prog = 1'b0;t_data_num = 9'b0;
432 
@(posedge SCK_gen);CSB_stop=1'b0;
433 
#tPP;
434 
 
435 
#(4*tSCKH);
436 
@(posedge SCK_gen); CSB_start = 1'b1;
437 
#tCSHH
438 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
439 
#(18*tSCKH);
440 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
441 
@(posedge SCK_gen);CSB_stop=1'b0;
442 
 
443 
#(4*tSCKH);
444 
@(posedge SCK_gen); CSB_start = 1'b1;
445 
#tCSHH
446 
CSB_out = 1'b0;CSB_start = 1'b0;trg_byt_prog = 1'b1;address = 24'h000102;data = 8'h2F;t_data_num = 9'b0_0000_1001;//byte program
447 
#(16*tSCKH);  // for opcode txn
448 
#(48*tSCKH);  // for address txn
449 
#(16*tSCKH); data = 8'h2E; // for data txn
450 
#(16*tSCKH); data = 8'h2A; // for data txn
451 
#(16*tSCKH); data = 8'h21; // for data txn
452 
#(16*tSCKH); data = 8'h3F; // for data txn
453 
#(16*tSCKH); data = 8'h4F; // for data txn
454 
#(16*tSCKH); data = 8'h5F; // for data txn
455 
#(16*tSCKH); data = 8'h6F; // for data txn
456 
#(16*tSCKH); data = 8'h7F; // for data txn
457 
#(16*tSCKH); // for data txn
458 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_byt_prog = 1'b0;t_data_num = 9'b0;
459 
@(posedge SCK_gen);CSB_stop=1'b0;
460 
#tPP;
461 
 
462 
#(4*tSCKH);
463 
@(posedge SCK_gen); CSB_start = 1'b1;
464 
#tCSHH
465 
CSB_out = 1'b0;CSB_start = 1'b0;trg_rd_array_l = 1'b1;address = 24'h000100;t_data_num = 9'b0_0000_0001; // read array (low freq)
466 
#(16*tSCKH);  // for opcode txn
467 
#(48*tSCKH);  // for address txn
468 
#(20*tSCKH);  // for data txn
469 
#(20*tSCKH);  // for data txn
470 
#(20*tSCKH);  // for data txn
471 
#(20*tSCKH);  // for data txn
472 
#(20*tSCKH);  // for data txn
473 
#(20*tSCKH);  // for data txn
474 
#(20*tSCKH);  // for data txn
475 
#(20*tSCKH);  // for data txn
476 
#(20*tSCKH);  // for data txn
477 
#(2*tSCKH);
478 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_rd_array_l = 1'b0;t_data_num = 9'b0;
479 
@(posedge SCK_gen);CSB_stop=1'b0;
480 
 
481 
#(4*tSCKH);
482 
@(posedge SCK_gen); CSB_start = 1'b1;
483 
#tCSHH
484 
CSB_out = 1'b0;CSB_start = 1'b0;trg_rd_protect = 1'b1; address = 24'h000101; // read sector protection
485 
#(16*tSCKH);  // for opcode txn
486 
#(48*tSCKH);  // for address txn
487 
#(20*tSCKH);  // for data txn
488 
#(2*tSCKH);
489 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_rd_protect = 1'b0;
490 
@(posedge SCK_gen);CSB_stop=1'b0;
491 
#tSECP;
492 
 
493 
#(4*tSCKH);
494 
@(posedge SCK_gen); CSB_start = 1'b1;
495 
#tCSHH
496 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
497 
#(18*tSCKH);
498 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
499 
@(posedge SCK_gen);CSB_stop=1'b0;
500 
 
501 
#(4*tSCKH);
502 
@(posedge SCK_gen); CSB_start = 1'b1;
503 
#tCSHH
504 
CSB_out = 1'b0;CSB_start = 1'b0;trg_protect = 1'b1; address = 24'h000101; // protect sector
505 
#(16*tSCKH);  // for opcode txn
506 
#(48*tSCKH);  // for address txn
507 
#(2*tSCKH);
508 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_protect = 1'b0;
509 
@(posedge SCK_gen);CSB_stop=1'b0;
510 
 
511 
#(4*tSCKH);
512 
@(posedge SCK_gen); CSB_start = 1'b1;
513 
#tCSHH
514 
CSB_out = 1'b0;CSB_start = 1'b0;trg_rd_protect = 1'b1; address = 24'h000108; // read sector protection
515 
#(16*tSCKH);  // for opcode txn
516 
#(48*tSCKH);  // for address txn
517 
#(20*tSCKH);  // for data txn
518 
#(2*tSCKH);
519 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_rd_protect = 1'b0;
520 
@(posedge SCK_gen);CSB_stop=1'b0;
521 
#tSECP;
522 
 
523 
#(4*tSCKH);
524 
@(posedge SCK_gen); CSB_start = 1'b1;
525 
#tCSHH
526 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
527 
#(18*tSCKH);
528 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
529 
@(posedge SCK_gen);CSB_stop=1'b0;
530 
 
531 
#(4*tSCKH);
532 
@(posedge SCK_gen); CSB_start = 1'b1;
533 
#tCSHH
534 
CSB_out = 1'b0;CSB_start = 1'b0;trg_byt_prog = 1'b1;address = 24'h00010B;data = 8'hCA;t_data_num = 9'b0_0000_0001;//byte program
535 
#(16*tSCKH);  // for opcode txn
536 
#(48*tSCKH);  // for address txn
537 
#(16*tSCKH);  // for data txn
538 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_byt_prog = 1'b0;
539 
@(posedge SCK_gen);CSB_stop=1'b0;
540 
#tPP;
541 
 
542 
#(4*tSCKH);
543 
@(posedge SCK_gen); CSB_start = 1'b1;
544 
#tCSHH
545 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
546 
#(18*tSCKH);
547 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
548 
@(posedge SCK_gen);CSB_stop=1'b0;
549 
 
550 
#(4*tSCKH);
551 
@(posedge SCK_gen); CSB_start = 1'b1;
552 
#tCSHH
553 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h000A01; // unprotect sector
554 
#(16*tSCKH);  // for opcode txn
555 
#(48*tSCKH);  // for address txn
556 
#(2*tSCKH);
557 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
558 
@(posedge SCK_gen);CSB_stop=1'b0;
559 
#tSECUP;
560 
 
561 
#(4*tSCKH);
562 
@(posedge SCK_gen); CSB_start = 1'b1;
563 
#tCSHH
564 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
565 
#(18*tSCKH);
566 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
567 
@(posedge SCK_gen);CSB_stop=1'b0;
568 
 
569 
#(4*tSCKH);
570 
@(posedge SCK_gen); CSB_start = 1'b1;
571 
#tCSHH
572 
CSB_out = 1'b0;CSB_start = 1'b0;trg_byt_prog = 1'b1;address = 24'h000A04;data = 8'h2F;t_data_num = 9'b1_0000_0000;//byte program
573 
#(16*tSCKH);  // for opcode txn
574 
#(48*tSCKH);  // for address txn
575 
for(i=0; i < 256; i=i+1) // for one page programming
576 
begin
577 
        #(16*tSCKH); data = 8'h10 + (3 * i);
578 
end
579 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_byt_prog = 1'b0;t_data_num = 9'b0;
580 
@(posedge SCK_gen);CSB_stop=1'b0;
581 
#tPP;
582 
 
583 
#(4*tSCKH);
584 
@(posedge SCK_gen); CSB_start = 1'b1;
585 
#tCSHH
586 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
587 
#(18*tSCKH);
588 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
589 
@(posedge SCK_gen);CSB_stop=1'b0;
590 
 
591 
#(4*tSCKH);
592 
@(posedge SCK_gen); CSB_start = 1'b1;
593 
#tCSHH
594 
CSB_out = 1'b0;CSB_start = 1'b0;trg_protect = 1'b1; address = 24'h000A00; // protect sector
595 
#(16*tSCKH);  // for opcode txn
596 
#(48*tSCKH);  // for address txn
597 
#(2*tSCKH);
598 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_protect = 1'b0;
599 
@(posedge SCK_gen);CSB_stop=1'b0;
600 
#(2*tSCKH);
601 
$display("****** ****** Byte/Page programming End ****** ******");
602 
//*/
603 
///*
604 
$display("****** ****** Sequential programming Start ****** ******");
605 
#(4*tSCKH);
606 
 
607 
@(posedge SCK_gen); CSB_start = 1'b1;
608 
#tCSHH
609 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
610 
#(18*tSCKH);
611 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
612 
@(posedge SCK_gen);CSB_stop=1'b0;
613 
 
614 
#(4*tSCKH);
615 
@(posedge SCK_gen); CSB_start = 1'b1;
616 
#tCSHH
617 
CSB_out = 1'b0;CSB_start = 1'b0;trg_seq_byt = 1'b1;address = 24'h07A000;data = 8'h1F;// sequential byte program
618 
#(16*tSCKH);  // for opcode txn
619 
#(48*tSCKH);  // for address txn
620 
#(16*tSCKH);  // for data txn
621 
#(2*tSCKH);
622 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_seq_byt = 1'b0;
623 
@(posedge SCK_gen);CSB_stop=1'b0;
624 
#tBP;
625 
 
626 
`ifdef 321
627 
`else
628 
#(4*tSCKH);
629 
@(posedge SCK_gen); CSB_start = 1'b1;
630 
#tCSHH
631 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
632 
#(18*tSCKH);
633 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
634 
@(posedge SCK_gen);CSB_stop=1'b0;
635 
 
636 
#(4*tSCKH);
637 
@(posedge SCK_gen); CSB_start = 1'b1;
638 
#tCSHH
639 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h07A000; // unprotect sector
640 
#(16*tSCKH);  // for opcode txn
641 
#(48*tSCKH);  // for address txn
642 
#(2*tSCKH);
643 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
644 
@(posedge SCK_gen);CSB_stop=1'b0;
645 
#tSECUP;
646 
 
647 
#(4*tSCKH);
648 
@(posedge SCK_gen); CSB_start = 1'b1;
649 
#tCSHH
650 
CSB_out = 1'b0;CSB_start = 1'b0;trg_seq_byt = 1'b1;address = 24'h07A000;data = 8'h1F;// sequential byte program
651 
#(16*tSCKH);  // for opcode txn
652 
#(48*tSCKH);  // for address txn
653 
#(16*tSCKH);  // for data txn
654 
#(2*tSCKH);
655 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_seq_byt = 1'b0;
656 
@(posedge SCK_gen);CSB_stop=1'b0;
657 
#tBP;
658 
 
659 
#(4*tSCKH);
660 
@(posedge SCK_gen); CSB_start = 1'b1;
661 
#tCSHH
662 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
663 
#(18*tSCKH);
664 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
665 
@(posedge SCK_gen);CSB_stop=1'b0;
666 
 
667 
#(4*tSCKH);
668 
@(posedge SCK_gen); CSB_start = 1'b1;
669 
#tCSHH
670 
CSB_out = 1'b0;CSB_start = 1'b0;trg_seq_byt = 1'b1;address = 24'h07A000;data = 8'h1F;// sequential byte program
671 
#(16*tSCKH);  // for opcode txn
672 
#(48*tSCKH);  // for address txn
673 
#(16*tSCKH);  // for data txn
674 
#(2*tSCKH);
675 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_seq_byt = 1'b0;
676 
@(posedge SCK_gen);CSB_stop=1'b0;
677 
#tBP;
678 
 
679 
#(4*tSCKH);
680 
@(posedge SCK_gen); CSB_start = 1'b1;
681 
#tCSHH
682 
CSB_out = 1'b0;CSB_start = 1'b0;trg_seq_byt = 1'b1;data = 8'h6E;t_no_addr=1'b1;// sequential byte program
683 
#(16*tSCKH);  // for opcode txn
684 
#(16*tSCKH);  // for data txn
685 
#(2*tSCKH);
686 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_seq_byt = 1'b0;t_no_addr=1'b0;
687 
@(posedge SCK_gen);CSB_stop=1'b0;
688 
#tBP;
689 
 
690 
#(4*tSCKH);
691 
@(posedge SCK_gen); CSB_start = 1'b1;
692 
#tCSHH
693 
CSB_out = 1'b0;CSB_start = 1'b0;trg_seq_byt = 1'b1;data = 8'h6B;t_no_addr=1'b1;// sequential byte program
694 
#(16*tSCKH);  // for opcode txn
695 
#(16*tSCKH);  // for data txn
696 
#(2*tSCKH);
697 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_seq_byt = 1'b0;t_no_addr=1'b0;
698 
@(posedge SCK_gen);CSB_stop=1'b0;
699 
#tBP;
700 
 
701 
#(4*tSCKH);
702 
@(posedge SCK_gen); CSB_start = 1'b1;
703 
#tCSHH
704 
CSB_out = 1'b0;CSB_start = 1'b0;trg_seq_byt = 1'b1;data = 8'h81;t_no_addr=1'b1;// sequential byte program
705 
#(16*tSCKH);  // for opcode txn
706 
#(16*tSCKH);  // for data txn
707 
#(2*tSCKH);
708 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_seq_byt = 1'b0;t_no_addr=1'b0;
709 
@(posedge SCK_gen);CSB_stop=1'b0;
710 
#tBP;
711 
 
712 
#(4*tSCKH);
713 
@(posedge SCK_gen); CSB_start = 1'b1;
714 
#tCSHH
715 
CSB_out = 1'b0;CSB_start = 1'b0;trg_seq_byt = 1'b1;data = 8'h14;t_no_addr=1'b1;// sequential byte program
716 
#(16*tSCKH);  // for opcode txn
717 
#(16*tSCKH);  // for data txn
718 
#(2*tSCKH);
719 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_seq_byt = 1'b0;t_no_addr=1'b0;
720 
@(posedge SCK_gen);CSB_stop=1'b0;
721 
#tBP;
722 
 
723 
#(4*tSCKH);
724 
@(posedge SCK_gen); CSB_start = 1'b1;
725 
#tCSHH
726 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_dis = 1'b1;              // write disable
727 
#(18*tSCKH);
728 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_dis = 1'b0;
729 
@(posedge SCK_gen);CSB_stop=1'b0;
730 
 
731 
#(4*tSCKH);
732 
@(posedge SCK_gen); CSB_start = 1'b1;
733 
#tCSHH
734 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
735 
#(18*tSCKH);
736 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
737 
@(posedge SCK_gen);CSB_stop=1'b0;
738 
 
739 
#(4*tSCKH);
740 
@(posedge SCK_gen); CSB_start = 1'b1;
741 
#tCSHH
742 
CSB_out = 1'b0;CSB_start = 1'b0;trg_protect = 1'b1; address = 24'h07A000; // protect sector
743 
#(16*tSCKH);  // for opcode txn
744 
#(48*tSCKH);  // for address txn
745 
#(2*tSCKH);
746 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_protect = 1'b0;
747 
@(posedge SCK_gen);CSB_stop=1'b0;
748 
 
749 
#(4*tSCKH);
750 
@(posedge SCK_gen); CSB_start = 1'b1;
751 
#tCSHH
752 
CSB_out = 1'b0;CSB_start = 1'b0;trg_rd_array = 1'b1;address = 24'h07A000;t_data_num = 9'b0_0000_0101; // read array
753 
#(16*tSCKH);  // for opcode txn
754 
#(48*tSCKH);  // for address txn
755 
#(16*tSCKH);  // for x val
756 
#(16*tSCKH);  // for data txn
757 
#(16*tSCKH);  // for data txn
758 
#(16*tSCKH);  // for data txn
759 
#(16*tSCKH);  // for data txn
760 
#(16*tSCKH);  // for data txn
761 
#(2*tSCKH);
762 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_rd_array = 1'b0;t_data_num = 9'b0;
763 
@(posedge SCK_gen);CSB_stop=1'b0;
764 
 
765 
#(4*tSCKH);
766 
@(posedge SCK_gen); CSB_start = 1'b1;
767 
#tCSHH
768 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
769 
#(18*tSCKH);
770 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
771 
@(posedge SCK_gen);CSB_stop=1'b0;
772 
 
773 
#(4*tSCKH);
774 
@(posedge SCK_gen); CSB_start = 1'b1;
775 
#tCSHH
776 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h060000; // unprotect sector
777 
#(16*tSCKH);  // for opcode txn
778 
#(48*tSCKH);  // for address txn
779 
#(2*tSCKH);
780 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
781 
@(posedge SCK_gen);CSB_stop=1'b0;
782 
#tSECUP;
783 
 
784 
#(4*tSCKH);
785 
@(posedge SCK_gen); CSB_start = 1'b1;
786 
#tCSHH
787 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
788 
#(18*tSCKH);
789 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
790 
@(posedge SCK_gen);CSB_stop=1'b0;
791 
 
792 
#(4*tSCKH);
793 
@(posedge SCK_gen); CSB_start = 1'b1;
794 
#tCSHH
795 
CSB_out = 1'b0;CSB_start = 1'b0;trg_seq_byt = 1'b1;address = 24'h060000;data = 8'h1F;// sequential byte program
796 
#(16*tSCKH);  // for opcode txn
797 
#(48*tSCKH);  // for address txn
798 
#(16*tSCKH);  // for data txn
799 
#(2*tSCKH);
800 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_seq_byt = 1'b0;
801 
@(posedge SCK_gen);CSB_stop=1'b0;
802 
#tBP;
803 
 
804 
for(i=1; i < 51; i=i+1)
805 
begin
806 
#(4*tSCKH);
807 
@(posedge SCK_gen); CSB_start = 1'b1;
808 
#tCSHH
809 
CSB_out = 1'b0;CSB_start = 1'b0;trg_seq_byt = 1'b1;t_no_addr=1'b1;// sequential byte program
810 
data = (8'hAE + i + (i*4));
811 
#(16*tSCKH);  // for opcode txn
812 
#(16*tSCKH);  // for data txn
813 
#(2*tSCKH);
814 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_seq_byt = 1'b0;t_no_addr=1'b0;
815 
@(posedge SCK_gen);CSB_stop=1'b0;
816 
#tBP;
817 
end
818 
 
819 
#(4*tSCKH);
820 
@(posedge SCK_gen); CSB_start = 1'b1;
821 
#tCSHH
822 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_dis = 1'b1;              // write disable
823 
#(18*tSCKH);
824 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_dis = 1'b0;
825 
@(posedge SCK_gen);CSB_stop=1'b0;
826 
 
827 
#(4*tSCKH);
828 
@(posedge SCK_gen); CSB_start = 1'b1;
829 
#tCSHH
830 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
831 
#(18*tSCKH);
832 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
833 
@(posedge SCK_gen);CSB_stop=1'b0;
834 
 
835 
#(4*tSCKH);
836 
@(posedge SCK_gen); CSB_start = 1'b1;
837 
#tCSHH
838 
CSB_out = 1'b0;CSB_start = 1'b0;trg_protect = 1'b1; address = 24'h060000; // protect sector
839 
#(16*tSCKH);  // for opcode txn
840 
#(48*tSCKH);  // for address txn
841 
#(2*tSCKH);
842 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_protect = 1'b0;
843 
@(posedge SCK_gen);CSB_stop=1'b0;
844 
 
845 
#(4*tSCKH);
846 
@(posedge SCK_gen); CSB_start = 1'b1;
847 
#tCSHH
848 
CSB_out = 1'b0;CSB_start = 1'b0;trg_rd_array = 1'b1;address = 24'h060000;t_data_num = 9'b0_0011_0011; // read array
849 
#(16*tSCKH);  // for opcode txn
850 
#(48*tSCKH);  // for address txn
851 
#(16*tSCKH);  // for x val
852 
#(16*tSCKH);  // for data txn
853 
for(i=1; i < 51; i=i+1)
854 
#(16*tSCKH);  // for data txn
855 
#(2*tSCKH);
856 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_rd_array = 1'b0;t_data_num = 9'b0;
857 
@(posedge SCK_gen);CSB_stop=1'b0;
858 
 
859 
#(4*tSCKH);
860 
@(posedge SCK_gen); CSB_start = 1'b1;
861 
#tCSHH
862 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
863 
#(18*tSCKH);
864 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
865 
@(posedge SCK_gen);CSB_stop=1'b0;
866 
 
867 
#(4*tSCKH);
868 
@(posedge SCK_gen); CSB_start = 1'b1;
869 
#tCSHH
870 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h07C000; // unprotect sector
871 
#(16*tSCKH);  // for opcode txn
872 
#(48*tSCKH);  // for address txn
873 
#(2*tSCKH);
874 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
875 
@(posedge SCK_gen);CSB_stop=1'b0;
876 
#tSECUP;
877 
 
878 
#(4*tSCKH);
879 
@(posedge SCK_gen); CSB_start = 1'b1;
880 
#tCSHH
881 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
882 
#(18*tSCKH);
883 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
884 
@(posedge SCK_gen);CSB_stop=1'b0;
885 
 
886 
#(4*tSCKH);
887 
@(posedge SCK_gen); CSB_start = 1'b1;
888 
#tCSHH
889 
CSB_out = 1'b0;CSB_start = 1'b0;trg_seq_byt = 1'b1;address = 24'h07FFFD;data = 8'h1F;// sequential byte program
890 
#(16*tSCKH);  // for opcode txn
891 
#(48*tSCKH);  // for address txn
892 
#(16*tSCKH);  // for data txn
893 
#(2*tSCKH);
894 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_seq_byt = 1'b0;
895 
@(posedge SCK_gen);CSB_stop=1'b0;
896 
#tBP;
897 
 
898 
#(4*tSCKH);
899 
@(posedge SCK_gen); CSB_start = 1'b1;
900 
#tCSHH
901 
CSB_out = 1'b0;CSB_start = 1'b0;trg_seq_byt = 1'b1;data = 8'h6B;t_no_addr=1'b1;// sequential byte program
902 
#(16*tSCKH);  // for opcode txn
903 
#(16*tSCKH);  // for data txn
904 
#(2*tSCKH);
905 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_seq_byt = 1'b0;t_no_addr=1'b0;
906 
@(posedge SCK_gen);CSB_stop=1'b0;
907 
#tBP;
908 
 
909 
#(4*tSCKH);
910 
@(posedge SCK_gen); CSB_start = 1'b1;
911 
#tCSHH
912 
CSB_out = 1'b0;CSB_start = 1'b0;trg_seq_byt = 1'b1;data = 8'h6B;t_no_addr=1'b1;// sequential byte program
913 
#(16*tSCKH);  // for opcode txn
914 
#(16*tSCKH);  // for data txn
915 
#(2*tSCKH);
916 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_seq_byt = 1'b0;t_no_addr=1'b0;
917 
@(posedge SCK_gen);CSB_stop=1'b0;
918 
#tBP;
919 
 
920 
#(4*tSCKH);
921 
@(posedge SCK_gen); CSB_start = 1'b1;
922 
#tCSHH
923 
CSB_out = 1'b0;CSB_start = 1'b0;trg_seq_byt = 1'b1;data = 8'h6B;t_no_addr=1'b1;// sequential byte program
924 
#(16*tSCKH);  // for opcode txn
925 
#(16*tSCKH);  // for data txn
926 
#(2*tSCKH);
927 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_seq_byt = 1'b0;t_no_addr=1'b0;
928 
@(posedge SCK_gen);CSB_stop=1'b0;
929 
#tBP;
930 
 
931 
#(4*tSCKH);
932 
@(posedge SCK_gen); CSB_start = 1'b1;
933 
#tCSHH
934 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
935 
#(18*tSCKH);
936 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
937 
@(posedge SCK_gen);CSB_stop=1'b0;
938 
 
939 
#(4*tSCKH);
940 
@(posedge SCK_gen); CSB_start = 1'b1;
941 
#tCSHH
942 
CSB_out = 1'b0;CSB_start = 1'b0;trg_protect = 1'b1; address = 24'h07C000; // protect sector
943 
#(16*tSCKH);  // for opcode txn
944 
#(48*tSCKH);  // for address txn
945 
#(2*tSCKH);
946 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_protect = 1'b0;
947 
@(posedge SCK_gen);CSB_stop=1'b0;
948 
#(2*tSCKH);
949 
 
950 
`endif
951 
$display("****** ****** Sequential programming end ****** ******");
952 
//*/
953 
///*
954 
// ----- check SPRL and WP -----
955 
$display("****** ****** Global protect, unprotect, SPRL and WPB start ****** ******");
956 
#(4*tSCKH);
957 
@(posedge SCK_gen); CSB_start = 1'b1;
958 
#tCSHH
959 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
960 
#(18*tSCKH);
961 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
962 
@(posedge SCK_gen);CSB_stop=1'b0;
963 
 
964 
#(4*tSCKH);
965 
@(posedge SCK_gen); CSB_start = 1'b1;
966 
#tCSHH
967 
CSB_out = 1'b0;CSB_start = 1'b0;trg_write_stat = 1'b1;data = 8'hF0; //Write Status reg - set SPRL
968 
#(16*tSCKH);  // for opcode txn
969 
#(16*tSCKH);  // for data txn
970 
#(2*tSCKH);
971 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_write_stat = 1'b0;
972 
@(posedge SCK_gen);CSB_stop=1'b0;
973 
#tWRSR;
974 
 
975 
#(4*tSCKH);
976 
@(posedge SCK_gen); CSB_start = 1'b1;
977 
#tCSHH
978 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
979 
#(18*tSCKH);
980 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
981 
@(posedge SCK_gen);CSB_stop=1'b0;
982 
 
983 
#(4*tSCKH);
984 
@(posedge SCK_gen); CSB_start = 1'b1;
985 
#tCSHH
986 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h011101; // unprotect sector
987 
#(16*tSCKH);  // for opcode txn
988 
#(48*tSCKH);  // for address txn
989 
#(2*tSCKH);
990 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
991 
@(posedge SCK_gen);CSB_stop=1'b0;
992 
#tSECUP;
993 
 
994 
#(4*tSCKH);
995 
@(posedge SCK_gen); CSB_start = 1'b1;
996 
#tCSHH
997 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
998 
#(18*tSCKH);
999 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1000 
@(posedge SCK_gen);CSB_stop=1'b0;
1001 
 
1002 
#(4*tSCKH);
1003 
@(posedge SCK_gen); CSB_start = 1'b1;
1004 
#tCSHH
1005 
CSB_out = 1'b0;CSB_start = 1'b0;trg_write_stat = 1'b1;data = 8'h0F; //Write Status reg - reset SPRL
1006 
#(16*tSCKH);  // for opcode txn
1007 
#(16*tSCKH);  // for data txn
1008 
#(2*tSCKH);
1009 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_write_stat = 1'b0;
1010 
@(posedge SCK_gen);CSB_stop=1'b0;
1011 
#tWRSR;
1012 
 
1013 
#(4*tSCKH);
1014 
@(posedge SCK_gen); CSB_start = 1'b1;
1015 
#tCSHH
1016 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1017 
#(18*tSCKH);
1018 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1019 
@(posedge SCK_gen);CSB_stop=1'b0;
1020 
 
1021 
#(4*tSCKH);
1022 
@(posedge SCK_gen); CSB_start = 1'b1;
1023 
#tCSHH
1024 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h011101; // unprotect sector
1025 
#(16*tSCKH);  // for opcode txn
1026 
#(48*tSCKH);  // for address txn
1027 
#(2*tSCKH);
1028 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
1029 
@(posedge SCK_gen);CSB_stop=1'b0;
1030 
#tSECUP;
1031 
 
1032 
#(4*tSCKH);
1033 
#tWPH;
1034 
WPB_out = 1'b0;
1035 
@(posedge SCK_gen); CSB_start = 1'b1;
1036 
#tCSHH
1037 
CSB_out = 1'b0;CSB_start = 1'b0;trg_read_stat=1'b1;             // read status register
1038 
#(54*tSCKH);
1039 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_read_stat=1'b0;
1040 
@(posedge SCK_gen);CSB_stop=1'b0;
1041 
 
1042 
#(4*tSCKH);
1043 
@(posedge SCK_gen); CSB_start = 1'b1;
1044 
#tCSHH
1045 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1046 
#(18*tSCKH);
1047 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1048 
@(posedge SCK_gen);CSB_stop=1'b0;
1049 
 
1050 
#(4*tSCKH);
1051 
@(posedge SCK_gen); CSB_start = 1'b1;
1052 
#tCSHH
1053 
CSB_out = 1'b0;CSB_start = 1'b0;trg_write_stat = 1'b1;data = 8'hF0; //Write Status reg - set SPRL
1054 
#(16*tSCKH);  // for opcode txn
1055 
#(16*tSCKH);  // for data txn
1056 
#(2*tSCKH);
1057 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_write_stat = 1'b0;
1058 
@(posedge SCK_gen);CSB_stop=1'b0;
1059 
#tWRSR;
1060 
 
1061 
#(4*tSCKH);
1062 
@(posedge SCK_gen); CSB_start = 1'b1;
1063 
#tCSHH
1064 
CSB_out = 1'b0;CSB_start = 1'b0;trg_read_stat=1'b1;             // read status register
1065 
#(54*tSCKH);
1066 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_read_stat=1'b0;
1067 
@(posedge SCK_gen);CSB_stop=1'b0;
1068 
 
1069 
#(4*tSCKH);
1070 
@(posedge SCK_gen); CSB_start = 1'b1;
1071 
#tCSHH
1072 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1073 
#(18*tSCKH);
1074 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1075 
@(posedge SCK_gen);CSB_stop=1'b0;
1076 
 
1077 
#(4*tSCKH);
1078 
@(posedge SCK_gen); CSB_start = 1'b1;
1079 
#tCSHH
1080 
CSB_out = 1'b0;CSB_start = 1'b0;trg_protect = 1'b1; address = 24'h011101; // protect sector
1081 
#(16*tSCKH);  // for opcode txn
1082 
#(48*tSCKH);  // for address txn
1083 
#(2*tSCKH);
1084 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_protect = 1'b0;
1085 
@(posedge SCK_gen);CSB_stop=1'b0;
1086 
 
1087 
#(4*tSCKH);
1088 
@(posedge SCK_gen); CSB_start = 1'b1;
1089 
#tCSHH
1090 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1091 
#(18*tSCKH);
1092 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1093 
@(posedge SCK_gen);CSB_stop=1'b0;
1094 
 
1095 
#(4*tSCKH);
1096 
@(posedge SCK_gen); CSB_start = 1'b1;
1097 
#tCSHH
1098 
CSB_out = 1'b0;CSB_start = 1'b0;trg_write_stat = 1'b1;data = 8'hF0; //Write Status reg - set SPRL
1099 
#(16*tSCKH);  // for opcode txn
1100 
#(16*tSCKH);  // for data txn
1101 
#(2*tSCKH);
1102 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_write_stat = 1'b0;
1103 
@(posedge SCK_gen);CSB_stop=1'b0;
1104 
#tWRSR;
1105 
 
1106 
#(4*tSCKH);
1107 
@(posedge SCK_gen); CSB_start = 1'b1;
1108 
#tCSHH
1109 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1110 
#(18*tSCKH);
1111 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1112 
@(posedge SCK_gen);CSB_stop=1'b0;
1113 
 
1114 
#(4*tSCKH);
1115 
@(posedge SCK_gen); CSB_start = 1'b1;
1116 
#tCSHH
1117 
CSB_out = 1'b0;CSB_start = 1'b0;trg_write_stat = 1'b1;data = 8'h0F; //Write Status reg - reset SPRL
1118 
#(16*tSCKH);  // for opcode txn
1119 
#(16*tSCKH);  // for data txn
1120 
#(2*tSCKH);
1121 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_write_stat = 1'b0;
1122 
@(posedge SCK_gen);CSB_stop=1'b0;
1123 
#tWRSR;
1124 
 
1125 
WPB_out = 1'b1;
1126 
#tWPS;
1127 
@(posedge SCK_gen); CSB_start = 1'b1;
1128 
#tCSHH
1129 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1130 
#(18*tSCKH);
1131 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1132 
@(posedge SCK_gen);CSB_stop=1'b0;
1133 
 
1134 
#(4*tSCKH);
1135 
@(posedge SCK_gen); CSB_start = 1'b1;
1136 
#tCSHH
1137 
CSB_out = 1'b0;CSB_start = 1'b0;trg_write_stat = 1'b1;data = 8'hF0; //Write Status reg - set SPRL
1138 
#(16*tSCKH);  // for opcode txn
1139 
#(16*tSCKH);  // for data txn
1140 
#(2*tSCKH);
1141 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_write_stat = 1'b0;
1142 
@(posedge SCK_gen);CSB_stop=1'b0;
1143 
#tWRSR;
1144 
 
1145 
#(4*tSCKH);
1146 
@(posedge SCK_gen); CSB_start = 1'b1;
1147 
#tCSHH
1148 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1149 
#(18*tSCKH);
1150 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1151 
@(posedge SCK_gen);CSB_stop=1'b0;
1152 
 
1153 
#(4*tSCKH);
1154 
@(posedge SCK_gen); CSB_start = 1'b1;
1155 
#tCSHH
1156 
CSB_out = 1'b0;CSB_start = 1'b0;trg_write_stat = 1'b1;data = 8'h00; //Write Status reg - reset SPRL; global unprotect
1157 
#(16*tSCKH);  // for opcode txn
1158 
#(16*tSCKH);  // for data txn
1159 
#(2*tSCKH);
1160 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_write_stat = 1'b0;
1161 
@(posedge SCK_gen);CSB_stop=1'b0;
1162 
#tWRSR;
1163 
// since SPRL is locked, global unprotect will not be executed
1164 
 
1165 
#(4*tSCKH);
1166 
@(posedge SCK_gen); CSB_start = 1'b1;
1167 
#tCSHH
1168 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1169 
#(18*tSCKH);
1170 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1171 
@(posedge SCK_gen);CSB_stop=1'b0;
1172 
 
1173 
#(4*tSCKH);
1174 
@(posedge SCK_gen); CSB_start = 1'b1;
1175 
#tCSHH
1176 
CSB_out = 1'b0;CSB_start = 1'b0;trg_protect = 1'b1; address = 24'h011101; // protect sector
1177 
#(16*tSCKH);  // for opcode txn
1178 
#(48*tSCKH);  // for address txn
1179 
#(2*tSCKH);
1180 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_protect = 1'b0;
1181 
@(posedge SCK_gen);CSB_stop=1'b0;
1182 
#(2*tSCKH);
1183 
 
1184 
#(4*tSCKH);
1185 
@(posedge SCK_gen); CSB_start = 1'b1;
1186 
#tCSHH
1187 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1188 
#(18*tSCKH);
1189 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1190 
@(posedge SCK_gen);CSB_stop=1'b0;
1191 
 
1192 
#(4*tSCKH);
1193 
@(posedge SCK_gen); CSB_start = 1'b1;
1194 
#tCSHH
1195 
CSB_out = 1'b0;CSB_start = 1'b0;trg_write_stat = 1'b1;data = 8'h00; //Write Status reg - global unprotect
1196 
#(16*tSCKH);  // for opcode txn
1197 
#(16*tSCKH);  // for data txn
1198 
#(4*tSCKH);
1199 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_write_stat = 1'b0;
1200 
@(posedge SCK_gen);CSB_stop=1'b0;
1201 
#tWRSR;
1202 
 
1203 
#(4*tSCKH);
1204 
@(posedge SCK_gen); CSB_start = 1'b1;
1205 
#tCSHH
1206 
CSB_out = 1'b0;CSB_start = 1'b0;trg_rd_protect = 1'b1; address = 24'h00010A; // read sector protection
1207 
#(16*tSCKH);  // for opcode txn
1208 
#(48*tSCKH);  // for address txn
1209 
#(20*tSCKH);  // for data txn
1210 
#(2*tSCKH);
1211 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_rd_protect = 1'b0;
1212 
@(posedge SCK_gen);CSB_stop=1'b0;
1213 
#tSECP;
1214 
 
1215 
#(4*tSCKH);
1216 
@(posedge SCK_gen); CSB_start = 1'b1;
1217 
#tCSHH
1218 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1219 
#(18*tSCKH);
1220 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1221 
@(posedge SCK_gen);CSB_stop=1'b0;
1222 
 
1223 
#(4*tSCKH);
1224 
@(posedge SCK_gen); CSB_start = 1'b1;
1225 
#tCSHH
1226 
CSB_out = 1'b0;CSB_start = 1'b0;trg_protect = 1'b1; address = 24'h000000; // protect sector
1227 
#(16*tSCKH);  // for opcode txn
1228 
#(48*tSCKH);  // for address txn
1229 
#(2*tSCKH);
1230 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_protect = 1'b0;
1231 
@(posedge SCK_gen);CSB_stop=1'b0;
1232 
 
1233 
#(4*tSCKH);
1234 
@(posedge SCK_gen); CSB_start = 1'b1;
1235 
#tCSHH
1236 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1237 
#(18*tSCKH);
1238 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1239 
@(posedge SCK_gen);CSB_stop=1'b0;
1240 
 
1241 
#(4*tSCKH);
1242 
@(posedge SCK_gen); CSB_start = 1'b1;
1243 
#tCSHH
1244 
CSB_out = 1'b0;CSB_start = 1'b0;trg_protect = 1'b1; address = 24'h010000; // protect sector
1245 
#(16*tSCKH);  // for opcode txn
1246 
#(48*tSCKH);  // for address txn
1247 
#(2*tSCKH);
1248 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_protect = 1'b0;
1249 
@(posedge SCK_gen);CSB_stop=1'b0;
1250 
 
1251 
#(4*tSCKH);
1252 
@(posedge SCK_gen); CSB_start = 1'b1;
1253 
#tCSHH
1254 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1255 
#(18*tSCKH);
1256 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1257 
@(posedge SCK_gen);CSB_stop=1'b0;
1258 
 
1259 
#(4*tSCKH);
1260 
@(posedge SCK_gen); CSB_start = 1'b1;
1261 
#tCSHH
1262 
CSB_out = 1'b0;CSB_start = 1'b0;trg_protect = 1'b1; address = 24'h020000; // protect sector
1263 
#(16*tSCKH);  // for opcode txn
1264 
#(48*tSCKH);  // for address txn
1265 
#(2*tSCKH);
1266 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_protect = 1'b0;
1267 
@(posedge SCK_gen);CSB_stop=1'b0;
1268 
 
1269 
#(4*tSCKH);
1270 
@(posedge SCK_gen); CSB_start = 1'b1;
1271 
#tCSHH
1272 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1273 
#(18*tSCKH);
1274 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1275 
@(posedge SCK_gen);CSB_stop=1'b0;
1276 
 
1277 
#(4*tSCKH);
1278 
@(posedge SCK_gen); CSB_start = 1'b1;
1279 
#tCSHH
1280 
CSB_out = 1'b0;CSB_start = 1'b0;trg_write_stat = 1'b1;data = 8'h7F; //Write Status reg - global protect; reset SPRL
1281 
#(16*tSCKH);  // for opcode txn
1282 
#(16*tSCKH);  // for data txn
1283 
#(2*tSCKH);
1284 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_write_stat = 1'b0;
1285 
@(posedge SCK_gen);CSB_stop=1'b0;
1286 
#tWRSR;
1287 
 
1288 
#(4*tSCKH);
1289 
@(posedge SCK_gen); CSB_start = 1'b1;
1290 
#tCSHH
1291 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1292 
#(18*tSCKH);
1293 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1294 
@(posedge SCK_gen);CSB_stop=1'b0;
1295 
 
1296 
#(4*tSCKH);
1297 
@(posedge SCK_gen); CSB_start = 1'b1;
1298 
#tCSHH
1299 
CSB_out = 1'b0;CSB_start = 1'b0;trg_write_stat = 1'b1;data = 8'h00; //Write Status reg - global unprotect
1300 
#(16*tSCKH);  // for opcode txn
1301 
#(16*tSCKH);  // for data txn
1302 
#(2*tSCKH);
1303 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_write_stat = 1'b0;
1304 
@(posedge SCK_gen);CSB_stop=1'b0;
1305 
#tWRSR;
1306 
 
1307 
#(4*tSCKH);
1308 
@(posedge SCK_gen); CSB_start = 1'b1;
1309 
#tCSHH
1310 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1311 
#(18*tSCKH);
1312 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1313 
@(posedge SCK_gen);CSB_stop=1'b0;
1314 
 
1315 
#(4*tSCKH);
1316 
@(posedge SCK_gen); CSB_start = 1'b1;
1317 
#tCSHH
1318 
CSB_out = 1'b0;CSB_start = 1'b0;trg_protect = 1'b1; address = 24'h000101; // protect sector
1319 
#(16*tSCKH);  // for opcode txn
1320 
#(48*tSCKH);  // for address txn
1321 
#(2*tSCKH);
1322 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_protect = 1'b0;
1323 
@(posedge SCK_gen);CSB_stop=1'b0;
1324 
#(10*tSCKH);
1325 
 
1326 
#(4*tSCKH);
1327 
@(posedge SCK_gen); CSB_start = 1'b1;
1328 
#tCSHH
1329 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1330 
#(18*tSCKH);
1331 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1332 
@(posedge SCK_gen);CSB_stop=1'b0;
1333 
 
1334 
#(4*tSCKH);
1335 
@(posedge SCK_gen); CSB_start = 1'b1;
1336 
#tCSHH
1337 
CSB_out = 1'b0;CSB_start = 1'b0;trg_write_stat = 1'b1;data = 8'hF0; //Write Status reg - set SPRL
1338 
#(16*tSCKH);  // for opcode txn
1339 
#(16*tSCKH);  // for data txn
1340 
#(4*tSCKH);
1341 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_write_stat = 1'b0;
1342 
@(posedge SCK_gen);CSB_stop=1'b0;
1343 
#tWRSR;
1344 
 
1345 
#(4*tSCKH);
1346 
@(posedge SCK_gen); CSB_start = 1'b1;
1347 
#tCSHH
1348 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1349 
#(18*tSCKH);
1350 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1351 
@(posedge SCK_gen);CSB_stop=1'b0;
1352 
 
1353 
#(4*tSCKH);
1354 
@(posedge SCK_gen); CSB_start = 1'b1;
1355 
#tCSHH
1356 
CSB_out = 1'b0;CSB_start = 1'b0;trg_write_stat = 1'b1;data = 8'h00; //Write Status reg - global unprotect
1357 
#(16*tSCKH);  // for opcode txn
1358 
#(16*tSCKH);  // for data txn
1359 
#(2*tSCKH);
1360 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_write_stat = 1'b0;
1361 
@(posedge SCK_gen);CSB_stop=1'b0;
1362 
#tWRSR;
1363 
// above global unprotect resets SPRL only. since SPRL is set, global unprotect cannot be done
1364 
 
1365 
#(4*tSCKH);
1366 
@(posedge SCK_gen); CSB_start = 1'b1;
1367 
#tCSHH
1368 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1369 
#(18*tSCKH);
1370 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1371 
@(posedge SCK_gen);CSB_stop=1'b0;
1372 
 
1373 
#(4*tSCKH);
1374 
@(posedge SCK_gen); CSB_start = 1'b1;
1375 
#tCSHH
1376 
CSB_out = 1'b0;CSB_start = 1'b0;trg_write_stat = 1'b1;data = 8'hFF; //Write Status reg - global protect; SPRL set
1377 
#(16*tSCKH);  // for opcode txn
1378 
#(16*tSCKH);  // for data txn
1379 
#(2*tSCKH);
1380 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_write_stat = 1'b0;
1381 
@(posedge SCK_gen);CSB_stop=1'b0;
1382 
#tWRSR;
1383 
 
1384 
#(4*tSCKH);
1385 
@(posedge SCK_gen); CSB_start = 1'b1;
1386 
#tCSHH
1387 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1388 
#(18*tSCKH);
1389 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1390 
@(posedge SCK_gen);CSB_stop=1'b0;
1391 
 
1392 
#(4*tSCKH);
1393 
@(posedge SCK_gen); CSB_start = 1'b1;
1394 
#tCSHH
1395 
CSB_out = 1'b0;CSB_start = 1'b0;trg_write_stat = 1'b1;data = 8'h0F; //Write Status reg - reset SPRL
1396 
#(16*tSCKH);  // for opcode txn
1397 
#(16*tSCKH);  // for data txn
1398 
#(4*tSCKH);
1399 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_write_stat = 1'b0;
1400 
@(posedge SCK_gen);CSB_stop=1'b0;
1401 
#tWRSR;
1402 
 
1403 
#(2*tSCKH);
1404 
$display("****** ****** Global protect, unprotect, SPRL and WPB end ****** ******");
1405 
//*/
1406 
// this part will take huge amount of time to simulate. Hence commented. can be run after uncommenting.
1407 
/*
1408 
$display("****** ****** Block Erase Start ****** ******");
1409 
 
1410 
#(4*tSCKH);
1411 
@(posedge SCK_gen); CSB_start = 1'b1;
1412 
#tCSHH
1413 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1414 
#(18*tSCKH);
1415 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1416 
@(posedge SCK_gen);CSB_stop=1'b0;
1417 
 
1418 
#(4*tSCKH);
1419 
@(posedge SCK_gen); CSB_start = 1'b1;
1420 
#tCSHH
1421 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h060000; // unprotect sector
1422 
#(16*tSCKH);  // for opcode txn
1423 
#(48*tSCKH);  // for address txn
1424 
#(2*tSCKH);
1425 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
1426 
@(posedge SCK_gen);CSB_stop=1'b0;
1427 
#tSECUP;
1428 
 
1429 
#(4*tSCKH);
1430 
@(posedge SCK_gen); CSB_start = 1'b1;
1431 
#tCSHH
1432 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1433 
#(18*tSCKH);
1434 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1435 
@(posedge SCK_gen);CSB_stop=1'b0;
1436 
 
1437 
#(4*tSCKH);
1438 
@(posedge SCK_gen); CSB_start = 1'b1;
1439 
#tCSHH
1440 
CSB_out = 1'b0;CSB_start = 1'b0;trg_be4 = 1'b1;address = 24'h060032; // 4K block erase
1441 
#(16*tSCKH);  // for opcode txn
1442 
#(48*tSCKH);  // for address txn
1443 
#(2*tSCKH);
1444 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_be4 = 1'b0;
1445 
@(posedge SCK_gen);CSB_stop=1'b0;
1446 
#tBLKE4;
1447 
 
1448 
#(4*tSCKH);
1449 
@(posedge SCK_gen); CSB_start = 1'b1;
1450 
#tCSHH
1451 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1452 
#(18*tSCKH);
1453 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1454 
@(posedge SCK_gen);CSB_stop=1'b0;
1455 
 
1456 
#(4*tSCKH);
1457 
@(posedge SCK_gen); CSB_start = 1'b1;
1458 
#tCSHH
1459 
CSB_out = 1'b0;CSB_start = 1'b0;trg_be32 = 1'b1;address = 24'h065032; // 32K block erase
1460 
#(16*tSCKH);  // for opcode txn
1461 
#(48*tSCKH);  // for address txn
1462 
#(2*tSCKH);
1463 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_be32 = 1'b0;
1464 
@(posedge SCK_gen);CSB_stop=1'b0;
1465 
#tBLKE32;
1466 
 
1467 
#(4*tSCKH);
1468 
@(posedge SCK_gen); CSB_start = 1'b1;
1469 
#tCSHH
1470 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1471 
#(18*tSCKH);
1472 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1473 
@(posedge SCK_gen);CSB_stop=1'b0;
1474 
 
1475 
#(4*tSCKH);
1476 
@(posedge SCK_gen); CSB_start = 1'b1;
1477 
#tCSHH
1478 
CSB_out = 1'b0;CSB_start = 1'b0;trg_be64 = 1'b1;address = 24'h06A032; // 64K block erase
1479 
#(16*tSCKH);  // for opcode txn
1480 
#(48*tSCKH);  // for address txn
1481 
#(2*tSCKH);
1482 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_be64 = 1'b0;
1483 
@(posedge SCK_gen);CSB_stop=1'b0;
1484 
#tBLKE64;
1485 
 
1486 
#(4*tSCKH);
1487 
@(posedge SCK_gen); CSB_start = 1'b1;
1488 
#tCSHH
1489 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1490 
#(18*tSCKH);
1491 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1492 
@(posedge SCK_gen);CSB_stop=1'b0;
1493 
 
1494 
#(4*tSCKH);
1495 
@(posedge SCK_gen); CSB_start = 1'b1;
1496 
#tCSHH
1497 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h000000; // unprotect sector
1498 
#(16*tSCKH);  // for opcode txn
1499 
#(48*tSCKH);  // for address txn
1500 
#(2*tSCKH);
1501 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
1502 
@(posedge SCK_gen);CSB_stop=1'b0;
1503 
#tSECUP;
1504 
 
1505 
#(4*tSCKH);
1506 
@(posedge SCK_gen); CSB_start = 1'b1;
1507 
#tCSHH
1508 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1509 
#(18*tSCKH);
1510 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1511 
@(posedge SCK_gen);CSB_stop=1'b0;
1512 
 
1513 
#(4*tSCKH);
1514 
@(posedge SCK_gen); CSB_start = 1'b1;
1515 
#tCSHH
1516 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h010000; // unprotect sector
1517 
#(16*tSCKH);  // for opcode txn
1518 
#(48*tSCKH);  // for address txn
1519 
#(2*tSCKH);
1520 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
1521 
@(posedge SCK_gen);CSB_stop=1'b0;
1522 
#tSECUP;
1523 
 
1524 
#(4*tSCKH);
1525 
@(posedge SCK_gen); CSB_start = 1'b1;
1526 
#tCSHH
1527 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1528 
#(18*tSCKH);
1529 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1530 
@(posedge SCK_gen);CSB_stop=1'b0;
1531 
 
1532 
#(4*tSCKH);
1533 
@(posedge SCK_gen); CSB_start = 1'b1;
1534 
#tCSHH
1535 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h020000; // unprotect sector
1536 
#(16*tSCKH);  // for opcode txn
1537 
#(48*tSCKH);  // for address txn
1538 
#(2*tSCKH);
1539 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
1540 
@(posedge SCK_gen);CSB_stop=1'b0;
1541 
#tSECUP;
1542 
 
1543 
#(4*tSCKH);
1544 
@(posedge SCK_gen); CSB_start = 1'b1;
1545 
#tCSHH
1546 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1547 
#(18*tSCKH);
1548 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1549 
@(posedge SCK_gen);CSB_stop=1'b0;
1550 
 
1551 
#(4*tSCKH);
1552 
@(posedge SCK_gen); CSB_start = 1'b1;
1553 
#tCSHH
1554 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h030000; // unprotect sector
1555 
#(16*tSCKH);  // for opcode txn
1556 
#(48*tSCKH);  // for address txn
1557 
#(2*tSCKH);
1558 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
1559 
@(posedge SCK_gen);CSB_stop=1'b0;
1560 
#tSECUP;
1561 
 
1562 
#(4*tSCKH);
1563 
@(posedge SCK_gen); CSB_start = 1'b1;
1564 
#tCSHH
1565 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1566 
#(18*tSCKH); CSB_out = 1'b1;trg_wr_en = 1'b0;
1567 
@(posedge SCK_gen);CSB_stop=1'b0;
1568 
 
1569 
#(4*tSCKH);
1570 
@(posedge SCK_gen); CSB_start = 1'b1;
1571 
#tCSHH
1572 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h040000; // unprotect sector
1573 
#(16*tSCKH);  // for opcode txn
1574 
#(48*tSCKH);  // for address txn
1575 
#(2*tSCKH);
1576 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
1577 
@(posedge SCK_gen);CSB_stop=1'b0;
1578 
#tSECUP;
1579 
 
1580 
#(4*tSCKH);
1581 
@(posedge SCK_gen); CSB_start = 1'b1;
1582 
#tCSHH
1583 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1584 
#(18*tSCKH);
1585 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1586 
@(posedge SCK_gen);CSB_stop=1'b0;
1587 
 
1588 
#(4*tSCKH);
1589 
@(posedge SCK_gen); CSB_start = 1'b1;
1590 
#tCSHH
1591 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h050000; // unprotect sector
1592 
#(16*tSCKH);  // for opcode txn
1593 
#(48*tSCKH);  // for address txn
1594 
#(2*tSCKH);
1595 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
1596 
@(posedge SCK_gen);CSB_stop=1'b0;
1597 
#tSECUP;
1598 
 
1599 
#(4*tSCKH);
1600 
@(posedge SCK_gen); CSB_start = 1'b1;
1601 
#tCSHH
1602 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1603 
#(18*tSCKH);
1604 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1605 
@(posedge SCK_gen);CSB_stop=1'b0;
1606 
 
1607 
#(4*tSCKH);
1608 
@(posedge SCK_gen); CSB_start = 1'b1;
1609 
#tCSHH
1610 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h060000; // unprotect sector
1611 
#(16*tSCKH);  // for opcode txn
1612 
#(48*tSCKH);  // for address txn
1613 
#(2*tSCKH);
1614 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
1615 
@(posedge SCK_gen);CSB_stop=1'b0;
1616 
#tSECUP;
1617 
 
1618 
#(4*tSCKH);
1619 
@(posedge SCK_gen); CSB_start = 1'b1;
1620 
#tCSHH
1621 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1622 
#(18*tSCKH);
1623 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1624 
@(posedge SCK_gen);CSB_stop=1'b0;
1625 
 
1626 
#(4*tSCKH);
1627 
@(posedge SCK_gen); CSB_start = 1'b1;
1628 
#tCSHH
1629 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h070000; // unprotect sector
1630 
#(16*tSCKH);  // for opcode txn
1631 
#(48*tSCKH);  // for address txn
1632 
#(2*tSCKH);
1633 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
1634 
@(posedge SCK_gen);CSB_stop=1'b0;
1635 
#tSECUP;
1636 
 
1637 
#(4*tSCKH);
1638 
@(posedge SCK_gen); CSB_start = 1'b1;
1639 
#tCSHH
1640 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1641 
#(18*tSCKH);
1642 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1643 
@(posedge SCK_gen);CSB_stop=1'b0;
1644 
 
1645 
#(4*tSCKH);
1646 
@(posedge SCK_gen); CSB_start = 1'b1;
1647 
#tCSHH
1648 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h078000; // unprotect sector
1649 
#(16*tSCKH);  // for opcode txn
1650 
#(48*tSCKH);  // for address txn
1651 
#(2*tSCKH);
1652 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
1653 
@(posedge SCK_gen);CSB_stop=1'b0;
1654 
#tSECUP;
1655 
 
1656 
#(4*tSCKH);
1657 
@(posedge SCK_gen); CSB_start = 1'b1;
1658 
#tCSHH
1659 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1660 
#(18*tSCKH);
1661 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1662 
@(posedge SCK_gen);CSB_stop=1'b0;
1663 
 
1664 
#(4*tSCKH);
1665 
@(posedge SCK_gen); CSB_start = 1'b1;
1666 
#tCSHH
1667 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h07A000; // unprotect sector
1668 
#(16*tSCKH);  // for opcode txn
1669 
#(48*tSCKH);  // for address txn
1670 
#(2*tSCKH);
1671 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
1672 
@(posedge SCK_gen);CSB_stop=1'b0;
1673 
#tSECUP;
1674 
 
1675 
#(4*tSCKH);
1676 
@(posedge SCK_gen); CSB_start = 1'b1;
1677 
#tCSHH
1678 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1679 
#(18*tSCKH);
1680 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1681 
@(posedge SCK_gen);CSB_stop=1'b0;
1682 
 
1683 
#(4*tSCKH);
1684 
@(posedge SCK_gen); CSB_start = 1'b1;
1685 
#tCSHH
1686 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h07C000; // unprotect sector
1687 
#(16*tSCKH);  // for opcode txn
1688 
#(48*tSCKH);  // for address txn
1689 
#(2*tSCKH);
1690 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
1691 
@(posedge SCK_gen);CSB_stop=1'b0;
1692 
#tSECUP;
1693 
 
1694 
// for slot 7-10
1695 
#(4*tSCKH);
1696 
@(posedge SCK_gen); CSB_start = 1'b1;
1697 
#tCSHH
1698 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1699 
#(18*tSCKH);
1700 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1701 
@(posedge SCK_gen);CSB_stop=1'b0;
1702 
 
1703 
#(4*tSCKH);
1704 
@(posedge SCK_gen); CSB_start = 1'b1;
1705 
#tCSHH
1706 
CSB_out = 1'b0;CSB_start = 1'b0;trg_be64 = 1'b1;address = 24'h070000; // 64K block erase
1707 
#(16*tSCKH);  // for opcode txn
1708 
#(48*tSCKH);  // for address txn
1709 
#(2*tSCKH);
1710 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_be64 = 1'b0;
1711 
@(posedge SCK_gen);CSB_stop=1'b0;
1712 
#tBLKE64;
1713 
 
1714 
#(4*tSCKH);
1715 
@(posedge SCK_gen); CSB_start = 1'b1;
1716 
#tCSHH
1717 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1718 
#(18*tSCKH);
1719 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1720 
@(posedge SCK_gen);CSB_stop=1'b0;
1721 
 
1722 
#(4*tSCKH);
1723 
@(posedge SCK_gen); CSB_start = 1'b1;
1724 
#tCSHH
1725 
CSB_out = 1'b0;CSB_start = 1'b0;trg_be32 = 1'b1;address = 24'h07A000; // 32K block erase
1726 
#(16*tSCKH);  // for opcode txn
1727 
#(48*tSCKH);  // for address txn
1728 
#(2*tSCKH);
1729 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_be32 = 1'b0;
1730 
@(posedge SCK_gen);CSB_stop=1'b0;
1731 
#tBLKE32;
1732 
 
1733 
#(4*tSCKH);
1734 
@(posedge SCK_gen); CSB_start = 1'b1;
1735 
#tCSHH
1736 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1737 
#(18*tSCKH);
1738 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1739 
@(posedge SCK_gen);CSB_stop=1'b0;
1740 
 
1741 
#(4*tSCKH);
1742 
@(posedge SCK_gen); CSB_start = 1'b1;
1743 
#tCSHH
1744 
CSB_out = 1'b0;CSB_start = 1'b0;trg_write_stat = 1'b1;data = 8'h00; //Write Status reg - global unprotect
1745 
#(16*tSCKH);  // for opcode txn
1746 
#(16*tSCKH);  // for data txn
1747 
#(2*tSCKH);
1748 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_write_stat = 1'b0;
1749 
@(posedge SCK_gen);CSB_stop=1'b0;
1750 
#tWRSR;
1751 
 
1752 
#(4*tSCKH);
1753 
@(posedge SCK_gen); CSB_start = 1'b1;
1754 
#tCSHH
1755 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1756 
#(18*tSCKH);
1757 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1758 
@(posedge SCK_gen);CSB_stop=1'b0;
1759 
 
1760 
#(4*tSCKH);
1761 
@(posedge SCK_gen); CSB_start = 1'b1;
1762 
#tCSHH
1763 
CSB_out = 1'b0;CSB_start = 1'b0;trg_ce = 1'b1;address = 24'h060032; // Chip erase
1764 
#(16*tSCKH);  // for opcode txn
1765 
#(48*tSCKH);  // for address txn
1766 
#(2*tSCKH);
1767 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_ce = 1'b0;
1768 
@(posedge SCK_gen);CSB_stop=1'b0;
1769 
                for(delay =0; delay < tmult; delay = delay+1)
1770 
                        #tCHPEn;
1771 
#(15*tSCKH);
1772 
 
1773 
#(4*tSCKH);
1774 
@(posedge SCK_gen); CSB_start = 1'b1;
1775 
#tCSHH
1776 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1777 
#(18*tSCKH);
1778 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1779 
@(posedge SCK_gen);CSB_stop=1'b0;
1780 
 
1781 
#(4*tSCKH);
1782 
@(posedge SCK_gen); CSB_start = 1'b1;
1783 
#tCSHH
1784 
CSB_out = 1'b0;CSB_start = 1'b0;trg_write_stat = 1'b1;data = 8'hFF; //Write Status reg - global protect; SPRL set
1785 
#(16*tSCKH);  // for opcode txn
1786 
#(16*tSCKH);  // for data txn
1787 
#(2*tSCKH);
1788 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_write_stat = 1'b0;
1789 
@(posedge SCK_gen);CSB_stop=1'b0;
1790 
#tWRSR;
1791 
 
1792 
#(4*tSCKH);
1793 
@(posedge SCK_gen); CSB_start = 1'b1;
1794 
#tCSHH
1795 
CSB_out = 1'b0;CSB_start = 1'b0;trg_rd_array = 1'b1;address = 24'h060000;t_data_num = 9'b0_0011_0011; // read array
1796 
#(16*tSCKH);  // for opcode txn
1797 
#(48*tSCKH);  // for address txn
1798 
#(16*tSCKH);  // for x val
1799 
#(20*tSCKH);  // for data txn
1800 
for(i=1; i < 51; i=i+1)
1801 
#(16*tSCKH);  // for data txn
1802 
#(2*tSCKH);
1803 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_rd_array = 1'b0;t_data_num = 9'b0;
1804 
@(posedge SCK_gen);CSB_stop=1'b0;
1805 
#(2*tSCKH);
1806 
 
1807 
`ifdef 041
1808 
// Erase operation in uneven sectors for device AT25DF041A
1809 
#(4*tSCKH);
1810 
@(posedge SCK_gen); CSB_start = 1'b1;
1811 
#tCSHH
1812 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1813 
#(18*tSCKH);
1814 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1815 
@(posedge SCK_gen);CSB_stop=1'b0;
1816 
 
1817 
#(4*tSCKH);
1818 
@(posedge SCK_gen); CSB_start = 1'b1;
1819 
#tCSHH
1820 
CSB_out = 1'b0;CSB_start = 1'b0;trg_write_stat = 1'b1;data = 8'h0F; //Write Status reg - reset SPRL
1821 
#(16*tSCKH);  // for opcode txn
1822 
#(16*tSCKH);  // for data txn
1823 
#(2*tSCKH);
1824 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_write_stat = 1'b0;
1825 
@(posedge SCK_gen);CSB_stop=1'b0;
1826 
#tWRSR;
1827 
 
1828 
#(4*tSCKH);
1829 
@(posedge SCK_gen); CSB_start = 1'b1;
1830 
#tCSHH
1831 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1832 
#(18*tSCKH);
1833 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1834 
@(posedge SCK_gen);CSB_stop=1'b0;
1835 
 
1836 
#(4*tSCKH);
1837 
@(posedge SCK_gen); CSB_start = 1'b1;
1838 
#tCSHH
1839 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h070000; // unprotect sector
1840 
#(16*tSCKH);  // for opcode txn
1841 
#(48*tSCKH);  // for address txn
1842 
#(2*tSCKH);
1843 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
1844 
@(posedge SCK_gen);CSB_stop=1'b0;
1845 
#tSECUP;
1846 
 
1847 
#(4*tSCKH);
1848 
@(posedge SCK_gen); CSB_start = 1'b1;
1849 
#tCSHH
1850 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1851 
#(18*tSCKH);
1852 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1853 
@(posedge SCK_gen);CSB_stop=1'b0;
1854 
 
1855 
#(4*tSCKH);
1856 
@(posedge SCK_gen); CSB_start = 1'b1;
1857 
#tCSHH
1858 
CSB_out = 1'b0;CSB_start = 1'b0;trg_be64 = 1'b1;address = 24'h070000; // 64K block erase
1859 
#(16*tSCKH);  // for opcode txn
1860 
#(48*tSCKH);  // for address txn
1861 
#(2*tSCKH);
1862 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_be64 = 1'b0;
1863 
@(posedge SCK_gen);CSB_stop=1'b0;
1864 
#tBLKE64;
1865 
 
1866 
#(4*tSCKH);
1867 
@(posedge SCK_gen); CSB_start = 1'b1;
1868 
#tCSHH
1869 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1870 
#(18*tSCKH);
1871 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1872 
@(posedge SCK_gen);CSB_stop=1'b0;
1873 
 
1874 
#(4*tSCKH);
1875 
@(posedge SCK_gen); CSB_start = 1'b1;
1876 
#tCSHH
1877 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h07A000; // unprotect sector
1878 
#(16*tSCKH);  // for opcode txn
1879 
#(48*tSCKH);  // for address txn
1880 
#(2*tSCKH);
1881 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
1882 
@(posedge SCK_gen);CSB_stop=1'b0;
1883 
#tSECUP;
1884 
 
1885 
#(4*tSCKH);
1886 
@(posedge SCK_gen); CSB_start = 1'b1;
1887 
#tCSHH
1888 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1889 
#(18*tSCKH);
1890 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1891 
@(posedge SCK_gen);CSB_stop=1'b0;
1892 
 
1893 
#(4*tSCKH);
1894 
@(posedge SCK_gen); CSB_start = 1'b1;
1895 
#tCSHH
1896 
CSB_out = 1'b0;CSB_start = 1'b0;trg_be32 = 1'b1;address = 24'h07A000; // 32K block erase
1897 
#(16*tSCKH);  // for opcode txn
1898 
#(48*tSCKH);  // for address txn
1899 
#(2*tSCKH);
1900 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_be32 = 1'b0;
1901 
@(posedge SCK_gen);CSB_stop=1'b0;
1902 
#tBLKE32;
1903 
 
1904 
#(4*tSCKH);
1905 
@(posedge SCK_gen); CSB_start = 1'b1;
1906 
#tCSHH
1907 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1908 
#(18*tSCKH);
1909 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1910 
@(posedge SCK_gen);CSB_stop=1'b0;
1911 
 
1912 
#(4*tSCKH);
1913 
@(posedge SCK_gen); CSB_start = 1'b1;
1914 
#tCSHH
1915 
CSB_out = 1'b0;CSB_start = 1'b0;trg_write_stat = 1'b1;data = 8'hFF; //Write Status reg - global protect; SPRL set
1916 
#(16*tSCKH);  // for opcode txn
1917 
#(16*tSCKH);  // for data txn
1918 
#(2*tSCKH);
1919 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_write_stat = 1'b0;
1920 
@(posedge SCK_gen);CSB_stop=1'b0;
1921 
#tWRSR;
1922 
`endif
1923 
 
1924 
`ifdef 081
1925 
// Erase operation in uneven sectors for device AT26DF081A
1926 
#(4*tSCKH);
1927 
@(posedge SCK_gen); CSB_start = 1'b1;
1928 
#tCSHH
1929 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1930 
#(18*tSCKH);
1931 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1932 
@(posedge SCK_gen);CSB_stop=1'b0;
1933 
 
1934 
#(4*tSCKH);
1935 
@(posedge SCK_gen); CSB_start = 1'b1;
1936 
#tCSHH
1937 
CSB_out = 1'b0;CSB_start = 1'b0;trg_write_stat = 1'b1;data = 8'h0F; //Write Status reg - reset SPRL
1938 
#(16*tSCKH);  // for opcode txn
1939 
#(16*tSCKH);  // for data txn
1940 
#(2*tSCKH);
1941 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_write_stat = 1'b0;
1942 
@(posedge SCK_gen);CSB_stop=1'b0;
1943 
#tWRSR;
1944 
 
1945 
#(4*tSCKH);
1946 
@(posedge SCK_gen); CSB_start = 1'b1;
1947 
#tCSHH
1948 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1949 
#(18*tSCKH);
1950 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1951 
@(posedge SCK_gen);CSB_stop=1'b0;
1952 
 
1953 
#(4*tSCKH);
1954 
@(posedge SCK_gen); CSB_start = 1'b1;
1955 
#tCSHH
1956 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h088000; // unprotect sector
1957 
#(16*tSCKH);  // for opcode txn
1958 
#(48*tSCKH);  // for address txn
1959 
#(2*tSCKH);
1960 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
1961 
@(posedge SCK_gen);CSB_stop=1'b0;
1962 
#tSECUP;
1963 
 
1964 
#(4*tSCKH);
1965 
@(posedge SCK_gen); CSB_start = 1'b1;
1966 
#tCSHH
1967 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1968 
#(18*tSCKH);
1969 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1970 
@(posedge SCK_gen);CSB_stop=1'b0;
1971 
 
1972 
#(4*tSCKH);
1973 
@(posedge SCK_gen); CSB_start = 1'b1;
1974 
#tCSHH
1975 
CSB_out = 1'b0;CSB_start = 1'b0;trg_be64 = 1'b1;address = 24'h080000; // 64K block erase
1976 
#(16*tSCKH);  // for opcode txn
1977 
#(48*tSCKH);  // for address txn
1978 
#(2*tSCKH);
1979 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_be64 = 1'b0;
1980 
@(posedge SCK_gen);CSB_stop=1'b0;
1981 
#tBLKE64;
1982 
 
1983 
#(4*tSCKH);
1984 
@(posedge SCK_gen); CSB_start = 1'b1;
1985 
#tCSHH
1986 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
1987 
#(18*tSCKH);
1988 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
1989 
@(posedge SCK_gen);CSB_stop=1'b0;
1990 
 
1991 
#(4*tSCKH);
1992 
@(posedge SCK_gen); CSB_start = 1'b1;
1993 
#tCSHH
1994 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h086000; // unprotect sector
1995 
#(16*tSCKH);  // for opcode txn
1996 
#(48*tSCKH);  // for address txn
1997 
#(2*tSCKH);
1998 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
1999 
@(posedge SCK_gen);CSB_stop=1'b0;
2000 
#tSECUP;
2001 
 
2002 
#(4*tSCKH);
2003 
@(posedge SCK_gen); CSB_start = 1'b1;
2004 
#tCSHH
2005 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2006 
#(18*tSCKH);
2007 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2008 
@(posedge SCK_gen);CSB_stop=1'b0;
2009 
 
2010 
#(4*tSCKH);
2011 
@(posedge SCK_gen); CSB_start = 1'b1;
2012 
#tCSHH
2013 
CSB_out = 1'b0;CSB_start = 1'b0;trg_be32 = 1'b1;address = 24'h080000; // 32K block erase
2014 
#(16*tSCKH);  // for opcode txn
2015 
#(48*tSCKH);  // for address txn
2016 
#(2*tSCKH);
2017 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_be32 = 1'b0;
2018 
@(posedge SCK_gen);CSB_stop=1'b0;
2019 
#tBLKE32;
2020 
 
2021 
#(4*tSCKH);
2022 
@(posedge SCK_gen); CSB_start = 1'b1;
2023 
#tCSHH
2024 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2025 
#(18*tSCKH);
2026 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2027 
@(posedge SCK_gen);CSB_stop=1'b0;
2028 
 
2029 
#(4*tSCKH);
2030 
@(posedge SCK_gen); CSB_start = 1'b1;
2031 
#tCSHH
2032 
CSB_out = 1'b0;CSB_start = 1'b0;trg_be4 = 1'b1;address = 24'h088000; // 4K block erase
2033 
#(16*tSCKH);  // for opcode txn
2034 
#(48*tSCKH);  // for address txn
2035 
#(2*tSCKH);
2036 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_be4 = 1'b0;
2037 
@(posedge SCK_gen);CSB_stop=1'b0;
2038 
#tBLKE32;
2039 
 
2040 
#(4*tSCKH);
2041 
@(posedge SCK_gen); CSB_start = 1'b1;
2042 
#tCSHH
2043 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2044 
#(18*tSCKH);
2045 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2046 
@(posedge SCK_gen);CSB_stop=1'b0;
2047 
 
2048 
#(4*tSCKH);
2049 
@(posedge SCK_gen); CSB_start = 1'b1;
2050 
#tCSHH
2051 
CSB_out = 1'b0;CSB_start = 1'b0;trg_write_stat = 1'b1;data = 8'hFF; //Write Status reg - global protect; SPRL set
2052 
#(16*tSCKH);  // for opcode txn
2053 
#(16*tSCKH);  // for data txn
2054 
#(2*tSCKH);
2055 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_write_stat = 1'b0;
2056 
@(posedge SCK_gen);CSB_stop=1'b0;
2057 
#tWRSR;
2058 
`endif
2059 
 
2060 
`ifdef 161
2061 
// Erase operation in uneven sectors for device AT26DF161A
2062 
#(4*tSCKH);
2063 
@(posedge SCK_gen); CSB_start = 1'b1;
2064 
#tCSHH
2065 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2066 
#(18*tSCKH);
2067 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2068 
@(posedge SCK_gen);CSB_stop=1'b0;
2069 
 
2070 
#(4*tSCKH);
2071 
@(posedge SCK_gen); CSB_start = 1'b1;
2072 
#tCSHH
2073 
CSB_out = 1'b0;CSB_start = 1'b0;trg_write_stat = 1'b1;data = 8'h0F; //Write Status reg - reset SPRL
2074 
#(16*tSCKH);  // for opcode txn
2075 
#(16*tSCKH);  // for data txn
2076 
#(2*tSCKH);
2077 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_write_stat = 1'b0;
2078 
@(posedge SCK_gen);CSB_stop=1'b0;
2079 
#tWRSR;
2080 
 
2081 
#(4*tSCKH);
2082 
@(posedge SCK_gen); CSB_start = 1'b1;
2083 
#tCSHH
2084 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2085 
#(18*tSCKH);
2086 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2087 
@(posedge SCK_gen);CSB_stop=1'b0;
2088 
 
2089 
#(4*tSCKH);
2090 
@(posedge SCK_gen); CSB_start = 1'b1;
2091 
#tCSHH
2092 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h1F8000; // unprotect sector
2093 
#(16*tSCKH);  // for opcode txn
2094 
#(48*tSCKH);  // for address txn
2095 
#(2*tSCKH);
2096 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
2097 
@(posedge SCK_gen);CSB_stop=1'b0;
2098 
#tSECUP;
2099 
 
2100 
#(4*tSCKH);
2101 
@(posedge SCK_gen); CSB_start = 1'b1;
2102 
#tCSHH
2103 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2104 
#(18*tSCKH);
2105 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2106 
@(posedge SCK_gen);CSB_stop=1'b0;
2107 
 
2108 
#(4*tSCKH);
2109 
@(posedge SCK_gen); CSB_start = 1'b1;
2110 
#tCSHH
2111 
CSB_out = 1'b0;CSB_start = 1'b0;trg_be64 = 1'b1;address = 24'h1F8000; // 64K block erase
2112 
#(16*tSCKH);  // for opcode txn
2113 
#(48*tSCKH);  // for address txn
2114 
#(2*tSCKH);
2115 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_be64 = 1'b0;
2116 
@(posedge SCK_gen);CSB_stop=1'b0;
2117 
#tBLKE64;
2118 
 
2119 
#(4*tSCKH);
2120 
@(posedge SCK_gen); CSB_start = 1'b1;
2121 
#tCSHH
2122 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2123 
#(18*tSCKH);
2124 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2125 
@(posedge SCK_gen);CSB_stop=1'b0;
2126 
 
2127 
#(4*tSCKH);
2128 
@(posedge SCK_gen); CSB_start = 1'b1;
2129 
#tCSHH
2130 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h1E8600; // unprotect sector
2131 
#(16*tSCKH);  // for opcode txn
2132 
#(48*tSCKH);  // for address txn
2133 
#(2*tSCKH);
2134 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
2135 
@(posedge SCK_gen);CSB_stop=1'b0;
2136 
#tSECUP;
2137 
 
2138 
#(4*tSCKH);
2139 
@(posedge SCK_gen); CSB_start = 1'b1;
2140 
#tCSHH
2141 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2142 
#(18*tSCKH);
2143 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2144 
@(posedge SCK_gen);CSB_stop=1'b0;
2145 
 
2146 
#(4*tSCKH);
2147 
@(posedge SCK_gen); CSB_start = 1'b1;
2148 
#tCSHH
2149 
CSB_out = 1'b0;CSB_start = 1'b0;trg_be32 = 1'b1;address = 24'h1E8600; // 32K block erase
2150 
#(16*tSCKH);  // for opcode txn
2151 
#(48*tSCKH);  // for address txn
2152 
#(2*tSCKH);
2153 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_be32 = 1'b0;
2154 
@(posedge SCK_gen);CSB_stop=1'b0;
2155 
#tBLKE32;
2156 
 
2157 
#(4*tSCKH);
2158 
@(posedge SCK_gen); CSB_start = 1'b1;
2159 
#tCSHH
2160 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2161 
#(18*tSCKH);
2162 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2163 
@(posedge SCK_gen);CSB_stop=1'b0;
2164 
 
2165 
#(4*tSCKH);
2166 
@(posedge SCK_gen); CSB_start = 1'b1;
2167 
#tCSHH
2168 
CSB_out = 1'b0;CSB_start = 1'b0;trg_be4 = 1'b1;address = 24'h1E0010; // 4K block erase
2169 
#(16*tSCKH);  // for opcode txn
2170 
#(48*tSCKH);  // for address txn
2171 
#(2*tSCKH);
2172 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_be4 = 1'b0;
2173 
@(posedge SCK_gen);CSB_stop=1'b0;
2174 
#tBLKE32;
2175 
 
2176 
#(4*tSCKH);
2177 
@(posedge SCK_gen); CSB_start = 1'b1;
2178 
#tCSHH
2179 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2180 
#(18*tSCKH);
2181 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2182 
@(posedge SCK_gen);CSB_stop=1'b0;
2183 
 
2184 
#(4*tSCKH);
2185 
@(posedge SCK_gen); CSB_start = 1'b1;
2186 
#tCSHH
2187 
CSB_out = 1'b0;CSB_start = 1'b0;trg_write_stat = 1'b1;data = 8'hFF; //Write Status reg - global protect; SPRL set
2188 
#(16*tSCKH);  // for opcode txn
2189 
#(16*tSCKH);  // for data txn
2190 
#(2*tSCKH);
2191 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_write_stat = 1'b0;
2192 
@(posedge SCK_gen);CSB_stop=1'b0;
2193 
#tWRSR;
2194 
`endif
2195 
 
2196 
`ifdef 321
2197 
// Erase operation in uneven sectors for device AT26DF321
2198 
#(4*tSCKH);
2199 
@(posedge SCK_gen); CSB_start = 1'b1;
2200 
#tCSHH
2201 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2202 
#(18*tSCKH);
2203 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2204 
@(posedge SCK_gen);CSB_stop=1'b0;
2205 
 
2206 
#(4*tSCKH);
2207 
@(posedge SCK_gen); CSB_start = 1'b1;
2208 
#tCSHH
2209 
CSB_out = 1'b0;CSB_start = 1'b0;trg_write_stat = 1'b1;data = 8'h0F; //Write Status reg - reset SPRL
2210 
#(16*tSCKH);  // for opcode txn
2211 
#(16*tSCKH);  // for data txn
2212 
#(2*tSCKH);
2213 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_write_stat = 1'b0;
2214 
@(posedge SCK_gen);CSB_stop=1'b0;
2215 
#tWRSR;
2216 
 
2217 
#(4*tSCKH);
2218 
@(posedge SCK_gen); CSB_start = 1'b1;
2219 
#tCSHH
2220 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2221 
#(18*tSCKH);
2222 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2223 
@(posedge SCK_gen);CSB_stop=1'b0;
2224 
 
2225 
#(4*tSCKH);
2226 
@(posedge SCK_gen); CSB_start = 1'b1;
2227 
#tCSHH
2228 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h3F8000; // unprotect sector
2229 
#(16*tSCKH);  // for opcode txn
2230 
#(48*tSCKH);  // for address txn
2231 
#(2*tSCKH);
2232 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
2233 
@(posedge SCK_gen);CSB_stop=1'b0;
2234 
#tSECUP;
2235 
 
2236 
#(4*tSCKH);
2237 
@(posedge SCK_gen); CSB_start = 1'b1;
2238 
#tCSHH
2239 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2240 
#(18*tSCKH);
2241 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2242 
@(posedge SCK_gen);CSB_stop=1'b0;
2243 
 
2244 
#(4*tSCKH);
2245 
@(posedge SCK_gen); CSB_start = 1'b1;
2246 
#tCSHH
2247 
CSB_out = 1'b0;CSB_start = 1'b0;trg_be64 = 1'b1;address = 24'h3F8000; // 64K block erase
2248 
#(16*tSCKH);  // for opcode txn
2249 
#(48*tSCKH);  // for address txn
2250 
#(2*tSCKH);
2251 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_be64 = 1'b0;
2252 
@(posedge SCK_gen);CSB_stop=1'b0;
2253 
#tBLKE64;
2254 
 
2255 
#(4*tSCKH);
2256 
@(posedge SCK_gen); CSB_start = 1'b1;
2257 
#tCSHH
2258 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2259 
#(18*tSCKH);
2260 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2261 
@(posedge SCK_gen);CSB_stop=1'b0;
2262 
 
2263 
#(4*tSCKH);
2264 
@(posedge SCK_gen); CSB_start = 1'b1;
2265 
#tCSHH
2266 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h3E8600; // unprotect sector
2267 
#(16*tSCKH);  // for opcode txn
2268 
#(48*tSCKH);  // for address txn
2269 
#(2*tSCKH);
2270 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
2271 
@(posedge SCK_gen);CSB_stop=1'b0;
2272 
#tSECUP;
2273 
 
2274 
#(4*tSCKH);
2275 
@(posedge SCK_gen); CSB_start = 1'b1;
2276 
#tCSHH
2277 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2278 
#(18*tSCKH);
2279 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2280 
@(posedge SCK_gen);CSB_stop=1'b0;
2281 
 
2282 
#(4*tSCKH);
2283 
@(posedge SCK_gen); CSB_start = 1'b1;
2284 
#tCSHH
2285 
CSB_out = 1'b0;CSB_start = 1'b0;trg_be32 = 1'b1;address = 24'h3E8600; // 32K block erase
2286 
#(16*tSCKH);  // for opcode txn
2287 
#(48*tSCKH);  // for address txn
2288 
#(2*tSCKH);
2289 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_be32 = 1'b0;
2290 
@(posedge SCK_gen);CSB_stop=1'b0;
2291 
#tBLKE32;
2292 
 
2293 
#(4*tSCKH);
2294 
@(posedge SCK_gen); CSB_start = 1'b1;
2295 
#tCSHH
2296 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2297 
#(18*tSCKH);
2298 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2299 
@(posedge SCK_gen);CSB_stop=1'b0;
2300 
 
2301 
#(4*tSCKH);
2302 
@(posedge SCK_gen); CSB_start = 1'b1;
2303 
#tCSHH
2304 
CSB_out = 1'b0;CSB_start = 1'b0;trg_be4 = 1'b1;address = 24'h3E0010; // 4K block erase
2305 
#(16*tSCKH);  // for opcode txn
2306 
#(48*tSCKH);  // for address txn
2307 
#(2*tSCKH);
2308 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_be4 = 1'b0;
2309 
@(posedge SCK_gen);CSB_stop=1'b0;
2310 
#tBLKE32;
2311 
 
2312 
#(4*tSCKH);
2313 
@(posedge SCK_gen); CSB_start = 1'b1;
2314 
#tCSHH
2315 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2316 
#(18*tSCKH);
2317 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2318 
@(posedge SCK_gen);CSB_stop=1'b0;
2319 
 
2320 
#(4*tSCKH);
2321 
@(posedge SCK_gen); CSB_start = 1'b1;
2322 
#tCSHH
2323 
CSB_out = 1'b0;CSB_start = 1'b0;trg_write_stat = 1'b1;data = 8'hFF; //Write Status reg - global protect; SPRL set
2324 
#(16*tSCKH);  // for opcode txn
2325 
#(16*tSCKH);  // for data txn
2326 
#(2*tSCKH);
2327 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_write_stat = 1'b0;
2328 
@(posedge SCK_gen);CSB_stop=1'b0;
2329 
#tWRSR;
2330 
`endif
2331 
 
2332 
#(2*tSCKH);
2333 
$display("****** ****** Block Erase end ****** ******");
2334 
*/
2335 
// this part can be uncommented. but will take huge amount of time to finish
2336 
///*
2337 
`ifdef 321
2338 
`else
2339 
$display("****** ****** Hold ****** ******");
2340 
#(4*tSCKH);
2341 
@(posedge SCK_gen); CSB_start = 1'b1;
2342 
#tCSHH
2343 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2344 
#(16*tSCKH);
2345 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2346 
@(posedge SCK_gen);CSB_stop=1'b0;
2347 
 
2348 
#(4*tSCKH);
2349 
@(posedge SCK_gen); CSB_start = 1'b1;
2350 
#tCSHH
2351 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h07A000; // unprotect sector
2352 
#(16*tSCKH);  // for opcode txn
2353 
#(48*tSCKH);  // for address txn
2354 
#(2*tSCKH);
2355 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
2356 
@(posedge SCK_gen);CSB_stop=1'b0;
2357 
#tSECUP;
2358 
 
2359 
#(4*tSCKH);
2360 
@(posedge SCK_gen); CSB_start = 1'b1;
2361 
#tCSHH
2362 
CSB_out = 1'b0;CSB_start = 1'b0;
2363 
trg_wr_en = 1'b1;               // write enable
2364 
#(4*tSCKH);
2365 
@(posedge SCK_gen);
2366 
#tHHH HOLDB_out = 1'b0;
2367 
#(6*tSCKH);
2368 
@(posedge SCK_gen);
2369 
#tHLH HOLDB_out = 1'b1;
2370 
#(14*tSCKH);
2371 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2372 
@(posedge SCK_gen);CSB_stop=1'b0;
2373 
 
2374 
#(4*tSCKH);
2375 
@(posedge SCK_gen); CSB_start = 1'b1;
2376 
#tCSHH
2377 
CSB_out = 1'b0;CSB_start = 1'b0;trg_byt_prog = 1'b1;address = 24'h07A000;data = 8'h2F;t_data_num = 9'b0_0000_1001;//byte program
2378 
#(16*tSCKH);  // for opcode txn
2379 
#(48*tSCKH);  // for address txn
2380 
#(16*tSCKH); data = 8'h2E; // for data txn
2381 
#(16*tSCKH); data = 8'h2A; // for data txn
2382 
#(16*tSCKH); data = 8'h21; // for data txn
2383 
#(16*tSCKH); data = 8'h3F; // for data txn
2384 
#(16*tSCKH); data = 8'h4F; // for data txn
2385 
#(16*tSCKH); data = 8'h5F; // for data txn
2386 
#(16*tSCKH); data = 8'h6F; // for data txn
2387 
#(16*tSCKH); data = 8'h7F; // for data txn
2388 
#(16*tSCKH); // for data txn
2389 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_byt_prog = 1'b0;t_data_num = 9'b0;
2390 
@(posedge SCK_gen);CSB_stop=1'b0;
2391 
#tPP;
2392 
 
2393 
#(4*tSCKH);
2394 
@(posedge SCK_gen); CSB_start = 1'b1;
2395 
#tCSHH
2396 
CSB_out = 1'b0;CSB_start = 1'b0;trg_rd_array = 1'b1;address = 24'h07A000;t_data_num = 9'b0_0011_0011; // read array
2397 
#(4*tSCKH);
2398 
@(posedge SCK_gen);
2399 
#tHHH HOLDB_out = 1'b0;
2400 
#(8*tSCKH);
2401 
@(posedge SCK_gen);
2402 
#tHLH HOLDB_out = 1'b1;
2403 
#(14*tSCKH);  // for opcode txn
2404 
#(8*tSCKH);
2405 
@(posedge SCK_gen);
2406 
#tHHH HOLDB_out = 1'b0;
2407 
#(8*tSCKH);
2408 
@(posedge SCK_gen);
2409 
#tHLH HOLDB_out = 1'b1;
2410 
#(40*tSCKH);  // for address txn
2411 
#(16*tSCKH);  // for x val
2412 
#(20*tSCKH);  // for data txn
2413 
#(20*tSCKH);  // for data txn
2414 
#(2*tSCKH);
2415 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_rd_array = 1'b0;t_data_num = 9'b0;
2416 
@(posedge SCK_gen);CSB_stop=1'b0;
2417 
 
2418 
#(4*tSCKH);
2419 
@(posedge SCK_gen); CSB_start = 1'b1;
2420 
#tCSHH
2421 
CSB_out = 1'b0;CSB_start = 1'b0;trg_rd_array_l = 1'b1;address = 24'h07A003;t_data_num = 9'b0_0000_0001; // read array
2422 
#(4*tSCKH);
2423 
@(posedge SCK_gen);
2424 
#tHHH HOLDB_out = 1'b0;
2425 
#(8*tSCKH);
2426 
@(posedge SCK_gen);
2427 
#tHLH HOLDB_out = 1'b1;
2428 
#(14*tSCKH);  // for opcode txn
2429 
#(8*tSCKH);
2430 
#tHHH HOLDB_out = 1'b0;
2431 
#(8*tSCKH);
2432 
@(posedge SCK_gen);
2433 
#tHLH HOLDB_out = 1'b1;
2434 
#(40*tSCKH);  // for address txn
2435 
#(20*tSCKH);  // for data txn
2436 
#(4*tSCKH);
2437 
@(posedge SCK_gen);
2438 
#tHHH HOLDB_out = 1'b0;
2439 
#(8*tSCKH);
2440 
@(posedge SCK_gen);
2441 
#tHLH HOLDB_out = 1'b1;
2442 
#(20*tSCKH);  // for data txn
2443 
#(4*tSCKH);
2444 
@(posedge SCK_gen);
2445 
#tHHH HOLDB_out = 1'b0;
2446 
#(8*tSCKH);
2447 
@(posedge SCK_gen);
2448 
#tHLH HOLDB_out = 1'b1;
2449 
#(2*tSCKH);
2450 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_rd_array_l = 1'b0;t_data_num = 9'b0_0000_0000;
2451 
@(posedge SCK_gen);CSB_stop=1'b0;
2452 
 
2453 
#(4*tSCKH);
2454 
@(posedge SCK_gen); CSB_start = 1'b1;
2455 
#tCSHH
2456 
CSB_out = 1'b0;CSB_start = 1'b0;trg_rd_protect = 1'b1; address = 24'h07A000; // read sector protection
2457 
#(16*tSCKH);  // for opcode txn
2458 
#(48*tSCKH);  // for address txn
2459 
#(20*tSCKH);  // for data txn
2460 
#(4*tSCKH);
2461 
@(posedge SCK_gen);
2462 
#tHHH HOLDB_out = 1'b0;
2463 
#(8*tSCKH);
2464 
@(posedge SCK_gen);
2465 
#tHLH HOLDB_out = 1'b1;
2466 
#(20*tSCKH);  // for data txn
2467 
#(2*tSCKH);
2468 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_rd_protect = 1'b0;
2469 
@(posedge SCK_gen);CSB_stop=1'b0;
2470 
#tSECP;
2471 
 
2472 
#(4*tSCKH);
2473 
@(posedge SCK_gen); CSB_start = 1'b1;
2474 
#tCSHH
2475 
CSB_out = 1'b0;CSB_start = 1'b0;trg_man = 1'b1;         // Manufacturer
2476 
#(16*tSCKH); // for opcode txn
2477 
#(4*tSCKH);
2478 
@(posedge SCK_gen);
2479 
#tHHH HOLDB_out = 1'b0;
2480 
#(8*tSCKH);
2481 
@(posedge SCK_gen);
2482 
#tHLH HOLDB_out = 1'b1;
2483 
#(84*tSCKH);
2484 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_man = 1'b0;
2485 
@(posedge SCK_gen);CSB_stop=1'b0;
2486 
 
2487 
#(4*tSCKH);
2488 
@(posedge SCK_gen); CSB_start = 1'b1;
2489 
#tCSHH
2490 
CSB_out = 1'b0;CSB_start = 1'b0;trg_read_stat=1'b1;             // read status register
2491 
#(16*tSCKH); // for opcode txn
2492 
#(8*tSCKH);
2493 
@(posedge SCK_gen);
2494 
#tHHH HOLDB_out = 1'b0;
2495 
#(8*tSCKH);
2496 
@(posedge SCK_gen);
2497 
#tHLH HOLDB_out = 1'b1;
2498 
#(54*tSCKH);
2499 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_read_stat=1'b0;
2500 
@(posedge SCK_gen);CSB_stop=1'b0;
2501 
 
2502 
$display("****** ****** Hold End ****** ******");
2503 
`endif
2504 
//*/
2505 
///*
2506 
$display("****** ****** Data validation Start****** ******");
2507 
#(4*tSCKH);
2508 
@(posedge SCK_gen); CSB_start = 1'b1;
2509 
#tCSHH
2510 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2511 
#(18*tSCKH);
2512 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2513 
@(posedge SCK_gen);CSB_stop=1'b0;
2514 
 
2515 
#(4*tSCKH);
2516 
@(posedge SCK_gen); CSB_start = 1'b1;
2517 
#tCSHH
2518 
CSB_out = 1'b0;CSB_start = 1'b0;trg_write_stat = 1'b1;data = 8'h0F; //Write Status reg - set SPRL
2519 
#(16*tSCKH);  // for opcode txn
2520 
#(16*tSCKH);  // for data txn
2521 
#(2*tSCKH);
2522 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_write_stat = 1'b0;
2523 
@(posedge SCK_gen);CSB_stop=1'b0;
2524 
#tWRSR;
2525 
 
2526 
#(4*tSCKH);
2527 
@(posedge SCK_gen); CSB_start = 1'b1;
2528 
#tCSHH
2529 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2530 
#(16*tSCKH);
2531 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2532 
@(posedge SCK_gen);CSB_stop=1'b0;
2533 
 
2534 
#(4*tSCKH);
2535 
@(posedge SCK_gen); CSB_start = 1'b1;
2536 
#tCSHH
2537 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h000101; // unprotect sector
2538 
#(16*tSCKH);  // for opcode txn
2539 
#(48*tSCKH);  // for address txn
2540 
#(2*tSCKH);
2541 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
2542 
@(posedge SCK_gen);CSB_stop=1'b0;
2543 
#tSECUP;
2544 
 
2545 
#(4*tSCKH);
2546 
@(posedge SCK_gen); CSB_start = 1'b1;
2547 
#tCSHH
2548 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2549 
#(18*tSCKH);
2550 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2551 
@(posedge SCK_gen);CSB_stop=1'b0;
2552 
 
2553 
j=0;
2554 
#(4*tSCKH);
2555 
@(posedge SCK_gen); CSB_start = 1'b1;
2556 
#tCSHH
2557 
CSB_out = 1'b0;CSB_start = 1'b0;trg_byt_prog = 1'b1;address = 24'h000101;data = 8'h2F;t_data_num = 9'b0_0000_1001;//byte program
2558 
#(16*tSCKH);  // for opcode txn
2559 
#(48*tSCKH);  // for address txn
2560 
store_data [j] = data; j=j+1;
2561 
#(16*tSCKH); data = 8'h2E; store_data [j] = data; j=j+1; // for data txn
2562 
#(16*tSCKH); data = 8'h2A; store_data [j] = data; j=j+1; // for data txn
2563 
#(16*tSCKH); data = 8'h21; store_data [j] = data; j=j+1; // for data txn
2564 
#(16*tSCKH); data = 8'h3F; store_data [j] = data; j=j+1; // for data txn
2565 
#(16*tSCKH); data = 8'h4F; store_data [j] = data; j=j+1; // for data txn
2566 
#(16*tSCKH); data = 8'h5F; store_data [j] = data; j=j+1; // for data txn
2567 
#(16*tSCKH); data = 8'h6F; store_data [j] = data; j=j+1; // for data txn
2568 
#(16*tSCKH); data = 8'h7F; store_data [j] = data; j=j+1; // for data txn
2569 
#(16*tSCKH); store_data [j] = data; j=j+1; // for data txn
2570 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_byt_prog = 1'b0;t_data_num = 9'b0;
2571 
@(posedge SCK_gen);CSB_stop=1'b0;
2572 
#tPP;
2573 
 
2574 
#(4*tSCKH);
2575 
@(posedge SCK_gen); CSB_start = 1'b1;
2576 
#tCSHH
2577 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2578 
#(18*tSCKH);
2579 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2580 
@(posedge SCK_gen);CSB_stop=1'b0;
2581 
 
2582 
#(4*tSCKH);
2583 
@(posedge SCK_gen); CSB_start = 1'b1;
2584 
#tCSHH
2585 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h000A01; // unprotect sector
2586 
#(16*tSCKH);  // for opcode txn
2587 
#(48*tSCKH);  // for address txn
2588 
#(2*tSCKH);
2589 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
2590 
@(posedge SCK_gen);CSB_stop=1'b0;
2591 
#tSECUP;
2592 
 
2593 
#(4*tSCKH);
2594 
@(posedge SCK_gen); CSB_start = 1'b1;
2595 
#tCSHH
2596 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2597 
#(18*tSCKH);
2598 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2599 
@(posedge SCK_gen);CSB_stop=1'b0;
2600 
 
2601 
#(4*tSCKH);
2602 
@(posedge SCK_gen); CSB_start = 1'b1;
2603 
#tCSHH
2604 
CSB_out = 1'b0;CSB_start = 1'b0;trg_byt_prog = 1'b1;address = 24'h000A04;data = 8'h2F;t_data_num = 9'b0_0001_1001;//byte program
2605 
#(16*tSCKH);  // for opcode txn
2606 
#(48*tSCKH);  // for address txn
2607 
for(i=0; i < 25; i=i+1) // for one page programming
2608 
begin
2609 
        #(16*tSCKH); store_data [j] = data; j=j+1; data = 8'h10 + (3 * i);
2610 
end
2611 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_byt_prog = 1'b0;t_data_num = 9'b0;
2612 
@(posedge SCK_gen);CSB_stop=1'b0;
2613 
#tPP;
2614 
 
2615 
#(4*tSCKH);
2616 
@(posedge SCK_gen); CSB_start = 1'b1;
2617 
#tCSHH
2618 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2619 
#(16*tSCKH);
2620 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2621 
@(posedge SCK_gen);CSB_stop=1'b0;
2622 
 
2623 
#(4*tSCKH);
2624 
@(posedge SCK_gen); CSB_start = 1'b1;
2625 
#tCSHH
2626 
CSB_out = 1'b0;CSB_start = 1'b0;trg_protect = 1'b1; address = 24'h000101; // protect sector
2627 
#(16*tSCKH);  // for opcode txn
2628 
#(48*tSCKH);  // for address txn
2629 
#(2*tSCKH);
2630 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_protect = 1'b0;
2631 
@(posedge SCK_gen);CSB_stop=1'b0;
2632 
 
2633 
#(4*tSCKH);
2634 
@(posedge SCK_gen); CSB_start = 1'b1;
2635 
#tCSHH
2636 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2637 
#(18*tSCKH);
2638 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2639 
@(posedge SCK_gen);CSB_stop=1'b0;
2640 
 
2641 
#(4*tSCKH);
2642 
@(posedge SCK_gen); CSB_start = 1'b1;
2643 
#tCSHH
2644 
CSB_out = 1'b0;CSB_start = 1'b0;trg_protect = 1'b1; address = 24'h000A01; // protect sector
2645 
#(16*tSCKH);  // for opcode txn
2646 
#(48*tSCKH);  // for address txn
2647 
#(2*tSCKH);
2648 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_protect = 1'b0;
2649 
@(posedge SCK_gen);CSB_stop=1'b0;
2650 
#tSECP
2651 
 
2652 
k=0;
2653 
#(4*tSCKH);
2654 
@(posedge SCK_gen); CSB_start = 1'b1;
2655 
#tCSHH
2656 
CSB_out = 1'b0;CSB_start = 1'b0;trg_rd_array_l = 1'b1;address = 24'h000101;t_data_num = 9'b0_0000_1001;// read array (low freq)
2657 
#(16*tSCKH);  // for opcode txn
2658 
#(48*tSCKH);  // for address txn
2659 
for(i=0; i < 9; i=i+1)
2660 
begin
2661 
        #(16*tSCKH); // for data txn
2662 
        read_data[k] = out_data;k=k+1;
2663 
end
2664 
#(2*tSCKH);
2665 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_rd_array_l = 1'b0;t_data_num = 9'b0_0000_0000;
2666 
@(posedge SCK_gen);CSB_stop=1'b0;
2667 
 
2668 
#(4*tSCKH);
2669 
@(posedge SCK_gen); CSB_start = 1'b1;
2670 
#tCSHH
2671 
CSB_out = 1'b0;CSB_start = 1'b0;trg_rd_array_l = 1'b1;address = 24'h000A04;t_data_num = 9'b0_0001_1001;// read array (low freq)
2672 
#(16*tSCKH);  // for opcode txn
2673 
#(48*tSCKH);  // for address txn
2674 
for(i=0; i <= 25; i=i+1)
2675 
begin
2676 
        read_data[k] = out_data;k=k+1;
2677 
        #(16*tSCKH); // for data txn
2678 
end
2679 
#(2*tSCKH);
2680 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_rd_array_l = 1'b0;t_data_num = 9'b0_0000_0000;
2681 
@(posedge SCK_gen);CSB_stop=1'b0;
2682 
 
2683 
for (i=0; i < k; i=i+1)
2684 
begin
2685 
        if(store_data[i] == read_data[i])
2686 
                $display("Write Data: %h, Read Data: %h Valid Data received",store_data[i],read_data[i]);
2687 
        else
2688 
                $display("Write Data: %h, Read Data: %h Invalid Data received",store_data[i],read_data[i]);
2689 
end
2690 
i=0;
2691 
j=0;
2692 
k=0;
2693 
 
2694 
#(4*tSCKH);
2695 
@(posedge SCK_gen); CSB_start = 1'b1;
2696 
#tCSHH
2697 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2698 
#(18*tSCKH);
2699 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2700 
@(posedge SCK_gen);CSB_stop=1'b0;
2701 
 
2702 
#(4*tSCKH);
2703 
@(posedge SCK_gen); CSB_start = 1'b1;
2704 
#tCSHH
2705 
CSB_out = 1'b0;CSB_start = 1'b0;trg_write_stat = 1'b1;data = 8'hF0; //Write Status reg - set SPRL
2706 
#(16*tSCKH);  // for opcode txn
2707 
#(16*tSCKH);  // for data txn
2708 
#(2*tSCKH);
2709 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_write_stat = 1'b0;
2710 
@(posedge SCK_gen);CSB_stop=1'b0;
2711 
#tWRSR;
2712 
// this will create data mismatch since byte program will not be done  -- intentionally done
2713 
 
2714 
#(4*tSCKH);
2715 
@(posedge SCK_gen); CSB_start = 1'b1;
2716 
#tCSHH
2717 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2718 
#(16*tSCKH);
2719 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2720 
@(posedge SCK_gen);CSB_stop=1'b0;
2721 
 
2722 
#(4*tSCKH);
2723 
@(posedge SCK_gen); CSB_start = 1'b1;
2724 
#tCSHH
2725 
CSB_out = 1'b0;CSB_start = 1'b0;trg_unprotect = 1'b1; address = 24'h000101; // unprotect sector
2726 
#(16*tSCKH);  // for opcode txn
2727 
#(48*tSCKH);  // for address txn
2728 
#(2*tSCKH);
2729 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_unprotect = 1'b0;
2730 
@(posedge SCK_gen);CSB_stop=1'b0;
2731 
#tSECUP;
2732 
 
2733 
#(4*tSCKH);
2734 
@(posedge SCK_gen); CSB_start = 1'b1;
2735 
#tCSHH
2736 
CSB_out = 1'b0;CSB_start = 1'b0;trg_wr_en = 1'b1;               // write enable
2737 
#(18*tSCKH);
2738 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_wr_en = 1'b0;
2739 
@(posedge SCK_gen);CSB_stop=1'b0;
2740 
 
2741 
j=0;
2742 
#(4*tSCKH);
2743 
@(posedge SCK_gen); CSB_start = 1'b1;
2744 
#tCSHH
2745 
CSB_out = 1'b0;CSB_start = 1'b0;trg_byt_prog = 1'b1;address = 24'h000301;data = 8'h2F;t_data_num = 9'b0_0000_0100;//byte program
2746 
#(16*tSCKH);  // for opcode txn
2747 
#(48*tSCKH);  // for address txn
2748 
store_data [j] = data; j=j+1;
2749 
#(16*tSCKH); data = 8'h2E; store_data [j] = data; j=j+1; // for data txn
2750 
#(16*tSCKH); data = 8'h2A; store_data [j] = data; j=j+1; // for data txn
2751 
#(16*tSCKH); data = 8'h21; store_data [j] = data; j=j+1; // for data txn
2752 
#(16*tSCKH); store_data [j] = data; j=j+1; // for data txn
2753 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_byt_prog = 1'b0;t_data_num = 9'b0;
2754 
@(posedge SCK_gen);CSB_stop=1'b0;
2755 
#tPP;
2756 
 
2757 
k=0;
2758 
#(4*tSCKH);
2759 
@(posedge SCK_gen); CSB_start = 1'b1;
2760 
#tCSHH
2761 
CSB_out = 1'b0;CSB_start = 1'b0;trg_rd_array_l = 1'b1;address = 24'h000301;t_data_num = 9'b0_0000_0100;// read array (low freq)
2762 
#(16*tSCKH);  // for opcode txn
2763 
#(48*tSCKH);  // for address txn
2764 
#(16*tSCKH); // for data txn
2765 
for(i=0; i <= 4; i=i+1)
2766 
begin
2767 
        read_data[k] = out_data;k=k+1;
2768 
        #(16*tSCKH); // for data txn
2769 
end
2770 
#(2*tSCKH);
2771 
#tCSLH CSB_out = 1'b1;CSB_stop=1'b1;trg_rd_array_l = 1'b0;t_data_num = 9'b0_0000_0000;
2772 
@(posedge SCK_gen);CSB_stop=1'b0;
2773 
 
2774 
for (i=0; i < k; i=i+1)
2775 
begin
2776 
        if(store_data[i] == read_data[i])
2777 
                $display("Write Data: %h, Read Data: %h Valid Data received",store_data[i],read_data[i]);
2778 
        else
2779 
                $display("Write Data: %h, Read Data: %h Invalid Data received",store_data[i],read_data[i]);
2780 
end
2781 
 
2782 
i=0;
2783 
k=0;
2784 
j=0;
2785 
$display("****** ****** Data validation End ****** ******");
2786 
//*/
2787 
 
2788 
#(38*tSCKH);
2789 
$finish;
2790 
 
2791 
end
2792 
 
2793 
`ifdef 041
2794 
AT26DFxxx #("AT25DF041A",PRELOAD,MEMORY_FILE) AT26DFxxx_dev1 (
2795 
`endif
2796 
`ifdef 081
2797 
AT26DFxxx #("AT26DF081A",PRELOAD,MEMORY_FILE) AT26DFxxx_dev1 (
2798 
`endif
2799 
`ifdef 161
2800 
AT26DFxxx #("AT26DF161A",PRELOAD,MEMORY_FILE) AT26DFxxx_dev1 (
2801 
`endif
2802 
`ifdef 321
2803 
AT26DFxxx #("AT26DF321",PRELOAD,MEMORY_FILE) AT26DFxxx_dev1 (
2804 
`endif
2805 
                .CSB    (CSB_out),
2806 
                .SCK    (SCK_out),
2807 
                .SI     (SI_out),
2808 
                .WPB    (WPB_out),
2809 
        `ifdef 321
2810 
        `else
2811 
                .HOLDB  (HOLDB_out),
2812 
        `endif
2813 
                .SO     (SO_in)
2814 
                );
2815 
 
2816 
AT26DFx_testbench tb1 (
2817 
                .clk            (SCK_gen),
2818 
                .HOLDB          (HOLDB_out),
2819 
                .SO_data        (SO_in),
2820 
                .tr_read_stat   (trg_read_stat),
2821 
                .tr_write_stat  (trg_write_stat),
2822 
                .tr_wr_en       (trg_wr_en),
2823 
                .tr_wr_dis      (trg_wr_dis),
2824 
                .tr_man         (trg_man),
2825 
                .tr_pwr_dwn     (trg_pwr_dwn),
2826 
                .tr_res_pwr_dwn (trg_res_pwr_dwn),
2827 
                .tr_byt_prog    (trg_byt_prog),
2828 
                .tr_rd_array    (trg_rd_array),
2829 
                .tr_rd_array_l  (trg_rd_array_l),
2830 
                .tr_seq_byt     (trg_seq_byt),
2831 
                .tr_protect     (trg_protect),
2832 
                .tr_unprotect   (trg_unprotect),
2833 
                .tr_rd_protect  (trg_rd_protect),
2834 
                .tr_be4         (trg_be4),
2835 
                .tr_be32        (trg_be32),
2836 
                .tr_be64        (trg_be64),
2837 
                .tr_ce          (trg_ce),
2838 
                .data_num       (t_data_num),
2839 
                .no_addr        (t_no_addr),
2840 
                .m_address      (address),
2841 
                .w_data         (data),
2842 
                .serial_in      (SI_out),
2843 
                .out_data       (out_data)
2844 
                );
2845 
 
2846 
endmodule

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