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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [bench/] [MT46V16M16/] [ddr_dimm.v] - Blame information for rev 12

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1 12 xianfeng 
/****************************************************************************************
2 
*
3 
*    File Name:  ddr_dimm.v
4 
*
5 
*  Description:  Micron SDRAM DDR (Double Data Rate) 184 pin dual in-line memory module (DIMM)
6 
*
7 
*   Limitation:  - SPD (Serial Presence-Detect) is not modeled
8 
*
9 
*   Disclaimer   This software code and all associated documentation, comments or other
10 
*  of Warranty:  information (collectively "Software") is provided "AS IS" without
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*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
12 
*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
13 
*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
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*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
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*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
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*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
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*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
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*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
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*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
20 
*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
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*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
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*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
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*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
24 
*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
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*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
26 
*                DAMAGES. Because some jurisdictions prohibit the exclusion or
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*                limitation of liability for consequential or incidental damages, the
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*                above limitation may not apply to you.
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*
30 
*                Copyright 2003 Micron Technology, Inc. All rights reserved.
31 
*
32 
****************************************************************************************/
33 
 
34 
`timescale 1ns / 1ps
35 
 
36 
module ddr_dimm (
37 
    reset_n,
38 
    ck     ,
39 
    ck_n   ,
40 
    cke    ,
41 
    s_n    ,
42 
    ras_n  ,
43 
    cas_n  ,
44 
    we_n   ,
45 
    ba     ,
46 
    addr   ,
47 
    dqs    ,
48 
    dq     ,
49 
    cb     ,
50 
    scl    ,
51 
    sa     ,
52 
    sda
53 
);
54 
 
55 
`include "ddr_parameters.vh"
56 
 
57 
    input                  reset_n;
58 
    input            [2:0] ck     ;
59 
    input            [2:0] ck_n   ;
60 
    input            [1:0] cke    ;
61 
    input            [1:0] s_n    ;
62 
    input                  ras_n  ;
63 
    input                  cas_n  ;
64 
    input                  we_n   ;
65 
    input            [1:0] ba     ;
66 
    input           [13:0] addr   ;
67 
    inout           [17:0] dqs    ;
68 
    inout           [63:0] dq     ;
69 
    inout            [7:0] cb     ;
70 
    input                  scl    ; // no connect
71 
    input            [2:0] sa     ; // no connect
72 
    inout                  sda    ; // no connect
73 
`ifdef DUAL_RANK
74 
    initial if (DEBUG) $display("%m: Dual Rank");
75 
`else
76 
    initial if (DEBUG) $display("%m: Single Rank");
77 
`endif
78 
`ifdef ECC
79 
    initial if (DEBUG) $display("%m: ECC");
80 
`else
81 
    initial if (DEBUG) $display("%m: non ECC");
82 
`endif
83 
`ifdef RDIMM
84 
    initial if (DEBUG) $display("%m: Registered DIMM");
85 
    wire             [2:0] rck    = {3{ck[0]}};
86 
    wire             [2:0] rck_n  = {3{ck_n[0]}};
87 
    reg              [1:0] rcke   ;
88 
    reg              [1:0] rs_n   ;
89 
    reg                    rras_n ;
90 
    reg                    rcas_n ;
91 
    reg                    rwe_n  ;
92 
    reg              [1:0] rba    ;
93 
    reg             [13:0] raddr  ;
94 
 
95 
    always @(negedge reset_n or posedge ck[0]) begin
96 
        if (!reset_n) begin
97 
            rcke   <= 0;
98 
            rs_n   <= 0;
99 
            rras_n <= 0;
100 
            rcas_n <= 0;
101 
            rwe_n  <= 0;
102 
            rba    <= 0;
103 
            raddr  <= 0;
104 
        end else begin
105 
            rcke   <=   cke;
106 
            rs_n   <=   s_n;
107 
            rras_n <= ras_n;
108 
            rcas_n <= cas_n;
109 
            rwe_n  <=  we_n;
110 
            rba    <=    ba;
111 
            raddr  <=  addr;
112 
        end
113 
    end
114 
`else
115 
    initial if (DEBUG) $display("%m: Unbuffered DIMM");
116 
    wire             [2:0] rck    = ck   ;
117 
    wire             [2:0] rck_n  = ck_n ;
118 
    wire             [1:0] rs_n   = s_n  ;
119 
    wire             [1:0] rcke   = cke  ;
120 
    wire                   rras_n = ras_n;
121 
    wire                   rcas_n = cas_n;
122 
    wire                   rwe_n  = we_n ;
123 
    wire             [1:0] rba    = ba   ;
124 
    wire            [13:0] raddr  = addr ;
125 
`endif
126 
 
127 
    wire                   zero   = 1'b0;
128 
    wire                   one    = 1'b1;
129 
 
130 
  //ddr      (ck    , ck_n    , cke    , cs_n   , ras_n , cas_n , we_n , ba , addr                , dm            , dq       , dqs           );
131 
`ifdef x4
132 
    initial if (DEBUG) $display("%m: Component Width = x4");
133 
    ddr U1   (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[ 3: 0], dqs[  0]      );
134 
    ddr U2   (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[11: 8], dqs[  1]      );
135 
    ddr U3   (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[19:16], dqs[  2]      );
136 
    ddr U4   (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[27:24], dqs[  3]      );
137 
    ddr U6   (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[35:32], dqs[  4]      );
138 
    ddr U7   (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[43:40], dqs[  5]      );
139 
    ddr U8   (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[51:48], dqs[  6]      );
140 
    ddr U9   (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[59:56], dqs[  7]      );
141 
    `ifdef ECC
142 
    ddr U5   (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , cb[ 3: 0], dqs[  8]      );
143 
    `endif
144 
    ddr U18  (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[ 7: 4], dqs[  9]      );
145 
    ddr U17  (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[15:12], dqs[ 10]      );
146 
    ddr U16  (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[23:20], dqs[ 11]      );
147 
    ddr U15  (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[31:28], dqs[ 12]      );
148 
    ddr U13  (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[39:36], dqs[ 13]      );
149 
    ddr U12  (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[47:44], dqs[ 14]      );
150 
    ddr U11  (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[55:52], dqs[ 15]      );
151 
    ddr U10  (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[63:60], dqs[ 16]      );
152 
    `ifdef ECC
153 
    ddr U14  (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , cb[ 7: 4], dqs[ 17]      );
154 
    `endif
155 
    `ifdef DUAL_RANK
156 
    ddr U1t  (rck[1], rck_n[1], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[ 3: 0], dqs[  0]      );
157 
    ddr U2t  (rck[1], rck_n[1], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[11: 8], dqs[  1]      );
158 
    ddr U3t  (rck[1], rck_n[1], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[19:16], dqs[  2]      );
159 
    ddr U4t  (rck[0], rck_n[0], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[27:24], dqs[  3]      );
160 
    ddr U6t  (rck[0], rck_n[0], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[35:32], dqs[  4]      );
161 
    ddr U7t  (rck[2], rck_n[2], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[43:40], dqs[  5]      );
162 
    ddr U8t  (rck[2], rck_n[2], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[51:48], dqs[  6]      );
163 
    ddr U9t  (rck[2], rck_n[2], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[59:56], dqs[  7]      );
164 
        `ifdef ECC
165 
    ddr U5t  (rck[0], rck_n[0], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , cb[ 3: 0], dqs[  8]      );
166 
        `endif
167 
    ddr U18t (rck[1], rck_n[1], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[ 7: 4], dqs[  9]      );
168 
    ddr U17t (rck[1], rck_n[1], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[15:12], dqs[ 10]      );
169 
    ddr U16t (rck[1], rck_n[1], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[23:20], dqs[ 11]      );
170 
    ddr U15t (rck[0], rck_n[0], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[31:28], dqs[ 12]      );
171 
    ddr U13t (rck[0], rck_n[0], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[39:36], dqs[ 13]      );
172 
    ddr U12t (rck[2], rck_n[2], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[47:44], dqs[ 14]      );
173 
    ddr U11t (rck[2], rck_n[2], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[55:52], dqs[ 15]      );
174 
    ddr U10t (rck[2], rck_n[2], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , dq[63:60], dqs[ 16]      );
175 
        `ifdef ECC
176 
    ddr U14t (rck[0], rck_n[0], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], zero          , cb[ 7: 4], dqs[ 17]      );
177 
        `endif
178 
    `endif
179 
`else `ifdef x8
180 
    initial if (DEBUG) $display("%m: Component Width = x8");
181 
    ddr U1   (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], dqs[ 9]       , dq[ 7: 0], dqs[  0]      );
182 
    ddr U2   (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], dqs[10]       , dq[15: 8], dqs[  1]      );
183 
    ddr U3   (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], dqs[11]       , dq[23:16], dqs[  2]      );
184 
    ddr U4   (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], dqs[12]       , dq[31:24], dqs[  3]      );
185 
    ddr U6   (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], dqs[13]       , dq[39:32], dqs[  4]      );
186 
    ddr U7   (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], dqs[14]       , dq[47:40], dqs[  5]      );
187 
    ddr U8   (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], dqs[15]       , dq[55:48], dqs[  6]      );
188 
    ddr U9   (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], dqs[16]       , dq[63:56], dqs[  7]      );
189 
    `ifdef ECC
190 
    ddr U5   (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], dqs[17]       , cb[ 7: 0], dqs[  8]      );
191 
    `endif
192 
    `ifdef DUAL_RANK
193 
    ddr U18  (rck[1], rck_n[1], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], dqs[ 9]       , dq[ 7: 0], dqs[  0]      );
194 
    ddr U17  (rck[1], rck_n[1], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], dqs[10]       , dq[15: 8], dqs[  1]      );
195 
    ddr U16  (rck[1], rck_n[1], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], dqs[11]       , dq[23:16], dqs[  2]      );
196 
    ddr U15  (rck[0], rck_n[0], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], dqs[12]       , dq[31:24], dqs[  3]      );
197 
    ddr U13  (rck[0], rck_n[0], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], dqs[13]       , dq[39:32], dqs[  4]      );
198 
    ddr U12  (rck[2], rck_n[2], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], dqs[14]       , dq[47:40], dqs[  5]      );
199 
    ddr U11  (rck[2], rck_n[2], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], dqs[15]       , dq[55:48], dqs[  6]      );
200 
    ddr U10  (rck[2], rck_n[2], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], dqs[16]       , dq[63:56], dqs[  7]      );
201 
        `ifdef ECC
202 
    ddr U14  (rck[0], rck_n[0], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], dqs[17]       , cb[ 7: 0], dqs[  8]      );
203 
        `endif
204 
    `endif
205 
`else `ifdef x16
206 
    initial if (DEBUG) $display("%m: Component Width = x16");
207 
    ddr U1   (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], dqs[10: 9]    , dq[15: 0], dqs[1:0]      );
208 
    ddr U2   (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], dqs[12:11]    , dq[31:16], dqs[3:2]      );
209 
    ddr U4   (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], dqs[14:13]    , dq[47:32], dqs[5:4]      );
210 
    ddr U5   (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], dqs[16:15]    , dq[63:48], dqs[7:6]      );
211 
    `ifdef ECC
212 
    ddr U3   (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], {one, dqs[17]}, {{8{zero}}, cb}, {zero, dqs[8]});
213 
    `endif
214 
    `ifdef DUAL_RANK
215 
    ddr U10  (rck[1], rck_n[1], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], dqs[10: 9]    , dq[15: 0], dqs[1:0]      );
216 
    ddr U9   (rck[1], rck_n[1], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], dqs[12:11]    , dq[31:16], dqs[3:2]      );
217 
    ddr U7   (rck[2], rck_n[2], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], dqs[14:13]    , dq[47:32], dqs[5:4]      );
218 
    ddr U6   (rck[2], rck_n[2], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], dqs[16:15]    , dq[63:48], dqs[7:6]      );
219 
        `ifdef ECC
220 
    ddr U8   (rck[0], rck_n[0], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, rba, raddr[ADDR_BITS-1:0], {one, dqs[17]}, {{8{zero}}, cb}, {zero, dqs[8]});
221 
        `endif
222 
    `endif
223 
`endif `endif `endif
224 
 
225 
endmodule

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