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Disclaimer of Warranty:
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-----------------------
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This software code and all associated documentation, comments or other
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information (collectively "Software") is provided "AS IS" without
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warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
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DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
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TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
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OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
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WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
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OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
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FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
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THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
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ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
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OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
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ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
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INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
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WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
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OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
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THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
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DAMAGES. Because some jurisdictions prohibit the exclusion or
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limitation of liability for consequential or incidental damages, the
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above limitation may not apply to you.
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Copyright 2003 Micron Technology, Inc. All rights reserved.
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Getting Started:
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----------------
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Unzip the included files to a folder.
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Compile ddr.v and tb.v using a verilog simulator.
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Simulate the top level test bench tb.
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Or, if you are using the ModelSim simulator, type "do tb.do" at the prompt.
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File Descriptions:
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------------------
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ddr.v -ddr component model
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ddr_dimm.v -structural wrapper that instantiates ddr components
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ddr_parameters.vh -file that contains all parameters used by the model
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readme.txt -this file
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tb.v -component test bench
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subtest.vh -example test included by the test bench.
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tb.do -compiles and runs the component model and test bench
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Defining the Speed Grade:
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-------------------------
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The verilog compiler directive "`define" may be used to choose between
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multiple speed grades supported by the ddr model. Allowable speed
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grades are listed in the ddr_parameters.vh file and begin with the
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letters "sg". The speed grade is used to select a set of timing
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parameters for the ddr model. The following are examples of defining
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the speed grade.
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simulator command line
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--------- ------------
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ModelSim vlog +define+sg5 ddr.v
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VCS vcs +define+sg5 ddr.v
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NC-Verilog ncverilog +define+sg5 ddr.v
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Defining the Organization:
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--------------------------
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The verilog compiler directive "`define" may be used to choose between
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multiple organizations supported by the ddr model. Valid
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organizations include "x4", "x8", "x16", and "x32", and are listed in the
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ddr_parameters.vh file. The organization is used to select the amount
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of memory and the port sizes of the ddr model. The following are
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examples of defining the organization.
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simulator command line
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--------- ------------
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ModelSim vlog +define+x8 ddr.v
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VCS vcs +define+x8 ddr.v
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NC-Verilog ncverilog +define+x8 ddr.v
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All combinations of speed grade and organization are considered valid
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by the ddr model even though a Micron part may not exist for every
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combination.
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Allocating Memory:
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------------------
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An associative array has been implemented to reduce the amount of
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static memory allocated by the DDR model. The number of
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entries in the associative array is controlled by the part_mem_bits
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parameter, and is equal to 2^part_mem_bits. For example, if the
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part_mem_bits parameter is equal to 10, the associative array will be
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large enough to store 1024 write data transfers to unique addresses.
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The following are examples of setting the part_mem_bits parameter to 8.
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simulator command line
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--------- ------------
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ModelSim vsim -Gpart_mem_bits=8 ddr
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VCS vcs -pvalue+part_mem_bits=8 ddr.v
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NC-Verilog ncverilog +defparam+ddr.part_mem_bits=8 ddr.v
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It is possible to allocate memory for every address supported by the
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ddr model by using the verilog compiler directive "`define FULL_MEM".
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This procedure will improve simulation performance at the expense of
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system memory. The following are examples of allocating memory for
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every address.
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Simulator command line
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--------- ------------
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ModelSim vlog +define+FULL_MEM ddr.v
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VCS vcs +define+FULL_MEM ddr.v
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NC-Verilog ncverilog +define+FULL_MEM ddr.v
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Defining the Number of Ranks on a DIMM:
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--------------------------------------
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The verilog compiler directive "`define" may be used to choose between
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single rank and dual rank DIMM configurations. The default is single
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rank if nothing is defined. Dual rank configuration can be selected by
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defining "DUAL_RANK" when the ddr_dimm is compiled. The following are
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examples of defining a dual rank DIMM configuration.
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simulator command line
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--------- ------------
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ModelSim vlog +define+DUAL_RANK ddr_dimm.v
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VCS vcs +define+DUAL_RANK ddr_dimm.v
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NC-Verilog ncverilog +define+DUAL_RANK ddr_dimm.v
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Defining the Buffering for a DIMM:
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---------------------------------
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The verilog compiler directive "`define" may be used to choose between
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registered and unregistered DIMM configurations. The default is
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unregistered if nothing is defined. Registered configuration can be
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selected by defining "RDIMM" when the ddr_dimm is compiled. The
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following are examples of defining a registered DIMM configuration.
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simulator command line
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--------- ------------
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ModelSim vlog +define+RDIMM ddr_dimm.v
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VCS vcs +define+RDIMM ddr_dimm.v
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NC-Verilog ncverilog +define+RDIMM ddr_dimm.v
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Defining the ECC for a DIMM:
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---------------------------
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The verilog compiler directive "`define" may be used to choose between
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ECC and nonECC DIMM configurations. The default is nonECC if nothing
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is defined. ECC configuration can be selected by defining "ECC" when
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the ddr_dimm is compiled. The following are examples of defining an
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ECC DIMM configuration.
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simulator command line
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--------- ------------
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ModelSim vlog +define+ECC ddr_dimm.v
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VCS vcs +define+ECC ddr_dimm.v
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NC-Verilog ncverilog +define+ECC ddr_dimm.v
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All combinations of ranks, buffering, and ECC are considered valid by
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the ddr_dimm model even though a Micron part may not exist for every
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combination.
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