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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [bench/] [MT46V16M16/] [tb.v] - Blame information for rev 12

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/****************************************************************************************
*
*    File Name:  tb.v
*      Version:  5.7
*        Model:  BUS Functional
*
* Dependencies:  ddr.v, ddr_parameters.v
*
*  Description:  Micron SDRAM DDR (Double Data Rate) test bench
*
*         Note:  - Set simulator resolution to "ps" accuracy
*                - Set Debug = 0 to disable $display messages
*
*   Disclaimer   This software code and all associated documentation, comments or other
*  of Warranty:  information (collectively "Software") is provided "AS IS" without
*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
*                DAMAGES. Because some jurisdictions prohibit the exclusion or
*                limitation of liability for consequential or incidental damages, the
*                above limitation may not apply to you.
*
*                Copyright 2003 Micron Technology, Inc. All rights reserved.
*
* Rev  Author Date        Changes
* --------------------------------------------------------------------------------
* 2.1  SPH    03/19/2002  - Second Release
*                         - Fix tWR and several incompatability
*                           between different simulators
* 3.0  TFK    02/18/2003  - Added tDSS and tDSH timing checks.
*                         - Added tDQSH and tDQSL timing checks.
* 3.1  CAH    05/28/2003  - update all models to release version 3.1
*                           (no changes to this model)
* 3.2  JMK    06/16/2003  - updated all DDR400 models to support CAS Latency 3
* 3.3  JMK    09/11/2003  - Added initialization sequence checks.
* 4.0  JMK    12/01/2003  - Grouped parameters into "ddr_parameters.v"
*                         - Fixed tWTR check
* 4.1  JMK    01/14/2001  - Grouped specify parameters by speed grade
*                         - Fixed mem_sizes parameter
* 4.2  JMK    03/19/2004  - Fixed pulse width checking on Dqs
* 4.3  JMK    04/27/2004  - Changed BL wire size in tb module
*                         - Changed Dq_buf size to [15:0]
* 5.0  JMK    06/16/2004  - Added read to write checking.
*                         - Added read with precharge truncation to write checking.
*                         - Added associative memory array to reduce memory consumption.
*                         - Added checking for required DQS edges during write.
* 5.1  JMK    08/16/2004  - Fixed checking for required DQS edges during write.
*                         - Fixed wdqs_valid window.
* 5.2  JMK    09/24/2004  - Read or Write without activate will be ignored.
* 5.3  JMK    10/27/2004  - Added tMRD checking during Auto Refresh and Activate.
*                         - Added tRFC checking during Load Mode and Precharge.
* 5.4  JMK    12/13/2004  - The model will not respond to illegal command sequences.
* 5.5  SPH    01/13/2005  - The model will issue a halt on illegal command sequences.
*      JMK    02/11/2005  - Changed the display format for numbers to hex.
* 5.6  JMK    04/22/2005  - Fixed Write with auto precharge calculation.
* 5.7  JMK    08/05/2005  - Changed conditions for read with precharge truncation error.
*                         - Renamed parameters file with .vh extension.
* 5.8  BAS    12/26/2006  - Added parameters for T46A part - 256Mb
*                         - Added x32 functionality
* 6.0  BAS    05/31/2007  - Added read_verify command
****************************************************************************************/
 
`timescale 1ns / 1ps
 
module tb;
 
`include "ddr_parameters.vh"
 
    reg                         clk         ;
    reg                         clk_n       ;
    reg                         cke         ;
    reg                         cs_n        ;
    reg                         ras_n       ;
    reg                         cas_n       ;
    reg                         we_n        ;
    reg       [BA_BITS - 1 : 0] ba          ;
    reg     [ADDR_BITS - 1 : 0] a           ;
    reg                         dq_en       ;
    reg       [DM_BITS - 1 : 0] dm_out      ;
    reg       [DQ_BITS - 1 : 0] dq_out      ;
    reg         [DM_BITS-1 : 0] dm_fifo [0 : 13];
    reg         [DQ_BITS-1 : 0] dq_fifo [0 : 13];
    reg         [DQ_BITS-1 : 0] dq_in_pos   ;
    reg         [DQ_BITS-1 : 0] dq_in_neg   ;
    reg                         dqs_en      ;
    reg      [DQS_BITS - 1 : 0] dqs_out     ;
 
    reg                [12 : 0] mode_reg    ;                   //Mode Register
    reg                [12 : 0] ext_mode_reg;                   //Extended Mode Register
 
    wire                        BO       = mode_reg[3];         //Burst Order
    wire                [7 : 0] BL       = (1<<mode_reg[2:0]);  //Burst Length
    wire                [2 : 0] CL       = (mode_reg[6:4] == 3'b110) ? 2.5 : mode_reg[6:4]; //CAS Latency
    wire                        dqs_n_en = ~ext_mode_reg[10];   //dqs# Enable
    wire                [2 : 0] AL       = ext_mode_reg[5:3];   //Additive Latency
    wire                [3 : 0] RL       = CL               ;   //Read Latency
    wire                [3 : 0] WL       = 1                ;   //Write Latency
 
    wire      [DM_BITS - 1 : 0] dm       = dq_en ? dm_out : {DM_BITS{1'bz}};
    wire      [DQ_BITS - 1 : 0] dq       = dq_en ? dq_out : {DQ_BITS{1'bz}};
    wire     [DQS_BITS - 1 : 0] dqs      = dqs_en ? dqs_out : {DQS_BITS{1'bz}};
    wire     [DQS_BITS - 1 : 0] dqs_n    = (dqs_en & dqs_n_en) ? ~dqs_out : {DQS_BITS{1'bz}};
    wire     [DQS_BITS - 1 : 0] rdqs_n   = {DM_BITS{1'bz}};
 
    wire               [15 : 0] dqs_in   = dqs;
    wire               [63 : 0] dq_in    = dq;
 
    ddr sdramddr (
        clk     ,
        clk_n   ,
        cke     ,
        cs_n    ,
        ras_n   ,
        cas_n   ,
        we_n    ,
        ba      ,
        a       ,
        dm      ,
        dq      ,
        dqs
    );
 
    // timing definition in tCK units
    real    tck   ;
    integer tmrd  ;
    integer trap  ;
    integer tras  ;
        integer trc   ;
    integer trfc  ;
    integer trcd  ;
    integer trp   ;
        integer trrd  ;
        integer twr   ;
 
    initial begin
`ifdef period
        tck = `period ;
`else
        tck =  tCK;
`endif
        tmrd   = ciel(tMRD/tck);
        trap   = ciel(tRAP/tck);
        tras   = ciel(tRAS/tck);
        trc    = ciel(tRC/tck);
        trfc   = ciel(tRFC/tck);
        trcd   = ciel(tRCD/tck);
        trp    = ciel(tRP/tck);
            trrd   = ciel(tRRD/tck);
            twr    = ciel(tWR/tck);
    end
 
    initial clk <= 1'b1;
    initial clk_n <= 1'b0;
    always @(posedge clk) begin
      clk   <= #(tck/2) 1'b0;
      clk_n <= #(tck/2) 1'b1;
      clk   <= #(tck) 1'b1;
      clk_n <= #(tck) 1'b0;
    end
 
    function integer ciel;
        input number;
        real number;
        if (number > $rtoi(number))
            ciel = $rtoi(number) + 1;
        else
            ciel = number;
    endfunction
 
    task power_up;
        begin
            cke    <=  1'b0;
            repeat(10) @(negedge clk);
            $display ("%m at time %t TB:  A 200 us delay is required before CKE can be brought high.", $time);
            @ (negedge clk) cke     =  1'b1;
            nop (400/tck+1);
        end
    endtask
 
    task load_mode;
        input [BA_BITS - 1 : 0] bank;
        input [ADDR_BITS - 1 : 0] addr;
        begin
            case (bank)
                0:     mode_reg = addr;
                1: ext_mode_reg = addr;
            endcase
            cke     = 1'b1;
            cs_n    = 1'b0;
            ras_n   = 1'b0;
            cas_n   = 1'b0;
            we_n    = 1'b0;
            ba      = bank;
            a       = addr;
            @(negedge clk);
        end
    endtask
 
    task refresh;
        begin
            cke     =  1'b1;
            cs_n    =  1'b0;
            ras_n   =  1'b0;
            cas_n   =  1'b0;
            we_n    =  1'b1;
            @(negedge clk);
        end
    endtask
 
    task burst_term;
        integer i;
        begin
            cke     = 1'b1;
            cs_n    = 1'b0;
            ras_n   = 1'b1;
            cas_n   = 1'b1;
            we_n    = 1'b0;
            @(negedge clk);
            for (i=0; i<BL; i=i+1) begin
                dm_fifo[2*RL + i] = {DM_BITS{1'bz}} ;
                dq_fifo[2*RL + i] = {DQ_BITS{1'bz}} ;
            end
        end
    endtask
 
    task self_refresh;
        input count;
        integer count;
        begin
            cke     =  1'b0;
            cs_n    =  1'b0;
            ras_n   =  1'b0;
            cas_n   =  1'b0;
            we_n    =  1'b1;
            repeat(count) @(negedge clk);
        end
    endtask
 
    task precharge;
        input       [BA_BITS - 1 : 0] bank;
        input       ap; //precharge all
        begin
            cke     = 1'b1;
            cs_n    = 1'b0;
            ras_n   = 1'b0;
            cas_n   = 1'b1;
            we_n    = 1'b0;
            ba      = bank;
            a       = (ap<<10);
            @(negedge clk);
        end
    endtask
 
    task activate;
        input [BA_BITS - 1 : 0] bank;
        input [ADDR_BITS - 1 : 0] row;
        begin
            cke     = 1'b1;
            cs_n    = 1'b0;
            ras_n   = 1'b0;
            cas_n   = 1'b1;
            we_n    = 1'b1;
            ba      =   bank;
            a    =  row;
            @(negedge clk);
        end
    endtask
 
    //write task supports burst lengths <= 16
    task write;
        input   [BA_BITS - 1 : 0] bank;
        input   [COL_BITS - 1 : 0] col;
        input                      ap; //Auto Precharge
        input [16*DM_BITS - 1 : 0] dm;
        input [16*DQ_BITS - 1 : 0] dq;
        reg    [ADDR_BITS - 1 : 0] atemp [1:0];
        reg      [DQ_BITS/DM_BITS - 1 : 0] dm_temp;
        integer i,j;
        begin
               cke     = 1'b1;
               cs_n    = 1'b0;
               ras_n   = 1'b1;
               cas_n   = 1'b0;
               we_n    = 1'b0;
               ba      =   bank;
               atemp[0] = col & 10'h3ff;   //ADDR[ 9: 0] = COL[ 9: 0]
               atemp[1] = (col>>10)<<11;   //ADDR[ N:11] = COL[ N:10]
               a = atemp[0] | atemp[1] | (ap<<10);
 
               for (i=0; i<=BL; i=i+1) begin
                        dqs_en <= #(WL*tck + i*tck/2) 1'b1;
                                if (i%2 === 0) begin
                                dqs_out <= #(WL*tck + i*tck/2) {DQS_BITS{1'b0}};
                                end else begin
                                         dqs_out <= #(WL*tck + i*tck/2) {DQS_BITS{1'b1}};
                   end
                      dq_en  <= #(WL*tck + i*tck/2 + tck/4) 1'b1;
                for (j=0; j<DM_BITS; j=j+1) begin
                    dm_temp = dm>>((i*DM_BITS + j)*DQ_BITS/DM_BITS);
                    dm_out[j] <= #(WL*tck + i*tck/2 + tck/4) &dm_temp;
                end
                dq_out <= #(WL*tck + i*tck/2 + tck/4) dq>>i*DQ_BITS;
                case (i)
                    15: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[16*DM_BITS-1 : 15*DM_BITS];
                    14: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[15*DM_BITS-1 : 14*DM_BITS];
                    13: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[14*DM_BITS-1 : 13*DM_BITS];
                    12: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[13*DM_BITS-1 : 12*DM_BITS];
                    11: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[12*DM_BITS-1 : 11*DM_BITS];
                    10: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[11*DM_BITS-1 : 10*DM_BITS];
                     9: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[10*DM_BITS-1 :  9*DM_BITS];
                     8: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 9*DM_BITS-1 :  8*DM_BITS];
                     7: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 8*DM_BITS-1 :  7*DM_BITS];
                     6: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 7*DM_BITS-1 :  6*DM_BITS];
                     5: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 6*DM_BITS-1 :  5*DM_BITS];
                     4: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 5*DM_BITS-1 :  4*DM_BITS];
                     3: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 4*DM_BITS-1 :  3*DM_BITS];
                     2: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 3*DM_BITS-1 :  2*DM_BITS];
                     1: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 2*DM_BITS-1 :  1*DM_BITS];
                     0: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 1*DM_BITS-1 :  0*DM_BITS];
                endcase
                case (i)
                    15: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[16*DQ_BITS-1 : 15*DQ_BITS];
                    14: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[15*DQ_BITS-1 : 14*DQ_BITS];
                    13: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[14*DQ_BITS-1 : 13*DQ_BITS];
                    12: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[13*DQ_BITS-1 : 12*DQ_BITS];
                    11: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[12*DQ_BITS-1 : 11*DQ_BITS];
                    10: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[11*DQ_BITS-1 : 10*DQ_BITS];
                     9: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[10*DQ_BITS-1 :  9*DQ_BITS];
                     8: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 9*DQ_BITS-1 :  8*DQ_BITS];
                     7: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 8*DQ_BITS-1 :  7*DQ_BITS];
                     6: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 7*DQ_BITS-1 :  6*DQ_BITS];
                     5: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 6*DQ_BITS-1 :  5*DQ_BITS];
                     4: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 5*DQ_BITS-1 :  4*DQ_BITS];
                     3: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 4*DQ_BITS-1 :  3*DQ_BITS];
                     2: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 3*DQ_BITS-1 :  2*DQ_BITS];
                     1: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 2*DQ_BITS-1 :  1*DQ_BITS];
                     0: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 1*DQ_BITS-1 :  0*DQ_BITS];
                endcase
                dq_en  <= #(WL*tck + i*tck/2 + tck/4) 1'b1;
            end
            dqs_en <= #(WL*tck + BL*tck/2 + tck/2) 1'b0;
            dq_en  <= #(WL*tck + BL*tck/2 + tck/4) 1'b0;
            @(negedge clk);
        end
    endtask
 
    task read;
        input   [BA_BITS - 1 : 0]bank;
        input   [COL_BITS - 1 : 0] col;
        input                      ap; //Auto Precharge
        reg    [ADDR_BITS - 1 : 0] atemp [1:0];
        begin
            cke     = 1'b1;
            cs_n    = 1'b0;
            ras_n   = 1'b1;
            cas_n   = 1'b0;
            we_n    = 1'b1;
            ba      =   bank;
            atemp[0] = col & 10'h3ff;   //ADDR[ 9: 0] = COL[ 9: 0]
            atemp[1] = (col>>10)<<11;   //ADDR[ N:11] = COL[ N:10]
            a = atemp[0] | atemp[1] | (ap<<10);
            @(negedge clk);
        end
    endtask
 
    // read with data verification
    task read_verify;
        input   [BA_BITS - 1 : 0] bank;
        input   [COL_BITS - 1 : 0] col;
        input                      ap; //Auto Precharge
        input [16*DM_BITS - 1 : 0] dm; //Expected Data Mask
        input [16*DQ_BITS - 1 : 0] dq; //Expected Data
        integer i;
        reg                  [2:0] brst_col;
        begin
            read (bank, col, ap);
            for (i=0; i<BL; i=i+1) begin
                // perform burst ordering
                brst_col = col ^ i;
                if (!BO) begin
                    brst_col = col + i;
                end
                if (BL == 4) begin
                    brst_col[2] = 1'b0 ;
                end else if (BL == 2) begin
                    brst_col[2:1] = 2'b00 ;
                end
                dm_fifo[2*RL + i] = dm >> (i*DM_BITS);
                dq_fifo[2*RL + i] = dq >> (i*DQ_BITS);
            end
        end
    endtask
 
    task nop;
        input  count;
        integer count;
        begin
            cke     =  1'b1;
            cs_n    =  1'b0;
            ras_n   =  1'b1;
            cas_n   =  1'b1;
            we_n    =  1'b1;
            repeat(count) @(negedge clk);
        end
    endtask
 
    task deselect;
        input  count;
        integer count;
        begin
            cke     =  1'b1;
            cs_n    =  1'b1;
            ras_n   =  1'b1;
            cas_n   =  1'b1;
            we_n    =  1'b1;
            repeat(count) @(negedge clk);
        end
    endtask
 
    task power_down;
        input  count;
        integer count;
        begin
            cke     =  1'b0;
            cs_n    =  1'b1;
            ras_n   =  1'b1;
            cas_n   =  1'b1;
            we_n    =  1'b1;
            repeat(count) @(negedge clk);
        end
    endtask
 
    function [16*DQ_BITS - 1 : 0] sort_data;
        input [16*DQ_BITS - 1 : 0] dq;
        input [2:0] col;
        integer i;
        reg   [2:0] brst_col;
        reg   [DQ_BITS - 1 :0] burst;
        begin
            sort_data = 0;
            for (i=0; i<BL; i=i+1) begin
                // perform burst ordering
                brst_col = col ^ i;
                if (!BO) begin
                    brst_col[1:0] = col + i;
                end
                burst = dq >> (brst_col*DQ_BITS);
                sort_data = sort_data | burst<<(i*DQ_BITS);
            end
        end
    endfunction
 
    // receiver(s) for data_verify process
    always @(dqs_in[0]) begin #(tDQSQ); dqs_receiver(0); end
    always @(dqs_in[1]) begin #(tDQSQ); dqs_receiver(1); end
    always @(dqs_in[2]) begin #(tDQSQ); dqs_receiver(2); end
    always @(dqs_in[3]) begin #(tDQSQ); dqs_receiver(3); end
    always @(dqs_in[4]) begin #(tDQSQ); dqs_receiver(4); end
    always @(dqs_in[5]) begin #(tDQSQ); dqs_receiver(5); end
    always @(dqs_in[6]) begin #(tDQSQ); dqs_receiver(6); end
    always @(dqs_in[7]) begin #(tDQSQ); dqs_receiver(7); end
 
    task dqs_receiver;
    input i;
    integer i;
    begin
        if (dqs_in[i]) begin
            case (i)
                0: dq_in_pos[ 7: 0] <= dq_in[ 7: 0];
                1: dq_in_pos[15: 8] <= dq_in[15: 8];
                2: dq_in_pos[23:16] <= dq_in[23:16];
                3: dq_in_pos[31:24] <= dq_in[31:24];
                4: dq_in_pos[39:32] <= dq_in[39:32];
                5: dq_in_pos[47:40] <= dq_in[47:40];
                6: dq_in_pos[55:48] <= dq_in[55:48];
                7: dq_in_pos[63:56] <= dq_in[63:56];
            endcase
        end else if (!dqs_in[i]) begin
            case (i)
                0: dq_in_neg[ 7: 0] <= dq_in[ 7: 0];
                1: dq_in_neg[15: 8] <= dq_in[15: 8];
                2: dq_in_neg[23:16] <= dq_in[23:16];
                3: dq_in_neg[31:24] <= dq_in[31:24];
                4: dq_in_pos[39:32] <= dq_in[39:32];
                5: dq_in_pos[47:40] <= dq_in[47:40];
                6: dq_in_pos[55:48] <= dq_in[55:48];
                7: dq_in_pos[63:56] <= dq_in[63:56];
            endcase
        end
    end
    endtask
 
 
    // perform data verification as a result of read_verify task call
    always @(clk) begin : data_verify
        integer i;
        reg [DM_BITS-1 : 0] data_mask;
        reg [8*DM_BITS-1 : 0] bit_mask;
 
        for (i=0; i<=14; i=i+1) begin
            dm_fifo[i] = dm_fifo[i+1];
            dq_fifo[i] = dq_fifo[i+1];
        end
        dm_fifo[13] = 'bz;
        dq_fifo[13] = 'bz;
//        dm_fifo[30] = 0;
//        dq_fifo[30] = 0;
        data_mask = dm_fifo[0];
 
        data_mask = dm_fifo[0];
       for (i=0; i<DM_BITS; i=i+1) begin
            bit_mask = {bit_mask, {8{~data_mask[i]}}};
       end
        if (clk) begin
            if ((dq_in_neg & bit_mask) != (dq_fifo[0] & bit_mask))
                $display ("%m at time %t: ERROR: Read data miscompare: Expected = %h, Actual = %h, Mask = %h", $time, dq_fifo[0], dq_in_neg, bit_mask);
        end else begin
            if ((dq_in_pos & bit_mask) != (dq_fifo[0] & bit_mask))
                $display ("%m at time %t: ERROR: Read data miscompare: Expected = %h, Actual = %h, Mask = %h", $time, dq_fifo[0], dq_in_pos, bit_mask);
        end
    end
 
 
 
    reg test_done;
        initial test_done = 0;
 
    // End-of-test triggered in 'subtest.vh'
    always @(test_done) begin : all_done
                if (test_done == 1) begin
      #5000
                        $display ("Simulation is Complete");
                        $stop(0);
                        $finish;
                end
        end
 
        // Test included from external file
    `include "subtest.vh"
 
endmodule

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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [bench/] [MT46V16M16/] [tb.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	xianfeng	`/****************************************************************************************`
2			`*`
3			`* File Name: tb.v`
4			`* Version: 5.7`
5			`* Model: BUS Functional`
6			`*`
7			`* Dependencies: ddr.v, ddr_parameters.v`
8			`*`
9			`* Description: Micron SDRAM DDR (Double Data Rate) test bench`
10			`*`
11			`* Note: - Set simulator resolution to "ps" accuracy`
12			`* - Set Debug = 0 to disable $display messages`
13			`*`
14			`* Disclaimer This software code and all associated documentation, comments or other`
15			`* of Warranty: information (collectively "Software") is provided "AS IS" without`
16			`* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY`
17			`* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED`
18			`* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES`
19			`* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT`
20			`* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE`
21			`* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.`
22			`* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR`
23			`* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,`
24			`* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE`
25			`* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,`
26			`* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,`
27			`* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,`
28			`* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,`
29			`* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE`
30			`* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH`
31			`* DAMAGES. Because some jurisdictions prohibit the exclusion or`
32			`* limitation of liability for consequential or incidental damages, the`
33			`* above limitation may not apply to you.`
34			`*`
35			`* Copyright 2003 Micron Technology, Inc. All rights reserved.`
36			`*`
37			`* Rev Author Date Changes`
38			`* --------------------------------------------------------------------------------`
39			`* 2.1 SPH 03/19/2002 - Second Release`
40			`* - Fix tWR and several incompatability`
41			`* between different simulators`
42			`* 3.0 TFK 02/18/2003 - Added tDSS and tDSH timing checks.`
43			`* - Added tDQSH and tDQSL timing checks.`
44			`* 3.1 CAH 05/28/2003 - update all models to release version 3.1`
45			`* (no changes to this model)`
46			`* 3.2 JMK 06/16/2003 - updated all DDR400 models to support CAS Latency 3`
47			`* 3.3 JMK 09/11/2003 - Added initialization sequence checks.`
48			`* 4.0 JMK 12/01/2003 - Grouped parameters into "ddr_parameters.v"`
49			`* - Fixed tWTR check`
50			`* 4.1 JMK 01/14/2001 - Grouped specify parameters by speed grade`
51			`* - Fixed mem_sizes parameter`
52			`* 4.2 JMK 03/19/2004 - Fixed pulse width checking on Dqs`
53			`* 4.3 JMK 04/27/2004 - Changed BL wire size in tb module`
54			`* - Changed Dq_buf size to [15:0]`
55			`* 5.0 JMK 06/16/2004 - Added read to write checking.`
56			`* - Added read with precharge truncation to write checking.`
57			`* - Added associative memory array to reduce memory consumption.`
58			`* - Added checking for required DQS edges during write.`
59			`* 5.1 JMK 08/16/2004 - Fixed checking for required DQS edges during write.`
60			`* - Fixed wdqs_valid window.`
61			`* 5.2 JMK 09/24/2004 - Read or Write without activate will be ignored.`
62			`* 5.3 JMK 10/27/2004 - Added tMRD checking during Auto Refresh and Activate.`
63			`* - Added tRFC checking during Load Mode and Precharge.`
64			`* 5.4 JMK 12/13/2004 - The model will not respond to illegal command sequences.`
65			`* 5.5 SPH 01/13/2005 - The model will issue a halt on illegal command sequences.`
66			`* JMK 02/11/2005 - Changed the display format for numbers to hex.`
67			`* 5.6 JMK 04/22/2005 - Fixed Write with auto precharge calculation.`
68			`* 5.7 JMK 08/05/2005 - Changed conditions for read with precharge truncation error.`
69			`* - Renamed parameters file with .vh extension.`
70			`* 5.8 BAS 12/26/2006 - Added parameters for T46A part - 256Mb`
71			`* - Added x32 functionality`
72			`* 6.0 BAS 05/31/2007 - Added read_verify command`
73			`****************************************************************************************/`
74
75			`timescale 1ns / 1ps
76
77			`module tb;`
78
79			`include "ddr_parameters.vh"
80
81			`reg clk ;`
82			`reg clk_n ;`
83			`reg cke ;`
84			`reg cs_n ;`
85			`reg ras_n ;`
86			`reg cas_n ;`
87			`reg we_n ;`
88			`reg [BA_BITS - 1 : 0] ba ;`
89			`reg [ADDR_BITS - 1 : 0] a ;`
90			`reg dq_en ;`
91			`reg [DM_BITS - 1 : 0] dm_out ;`
92			`reg [DQ_BITS - 1 : 0] dq_out ;`
93			`reg [DM_BITS-1 : 0] dm_fifo [0 : 13];`
94			`reg [DQ_BITS-1 : 0] dq_fifo [0 : 13];`
95			`reg [DQ_BITS-1 : 0] dq_in_pos ;`
96			`reg [DQ_BITS-1 : 0] dq_in_neg ;`
97			`reg dqs_en ;`
98			`reg [DQS_BITS - 1 : 0] dqs_out ;`
99
100			`reg [12 : 0] mode_reg ; //Mode Register`
101			`reg [12 : 0] ext_mode_reg; //Extended Mode Register`
102
103			`wire BO = mode_reg[3]; //Burst Order`
104			`wire [7 : 0] BL = (1<<mode_reg[2:0]); //Burst Length`
105			`wire [2 : 0] CL = (mode_reg[6:4] == 3'b110) ? 2.5 : mode_reg[6:4]; //CAS Latency`
106			`wire dqs_n_en = ~ext_mode_reg[10]; //dqs# Enable`
107			`wire [2 : 0] AL = ext_mode_reg[5:3]; //Additive Latency`
108			`wire [3 : 0] RL = CL ; //Read Latency`
109			`wire [3 : 0] WL = 1 ; //Write Latency`
110
111			`wire [DM_BITS - 1 : 0] dm = dq_en ? dm_out : {DM_BITS{1'bz}};`
112			`wire [DQ_BITS - 1 : 0] dq = dq_en ? dq_out : {DQ_BITS{1'bz}};`
113			`wire [DQS_BITS - 1 : 0] dqs = dqs_en ? dqs_out : {DQS_BITS{1'bz}};`
114			`wire [DQS_BITS - 1 : 0] dqs_n = (dqs_en & dqs_n_en) ? ~dqs_out : {DQS_BITS{1'bz}};`
115			`wire [DQS_BITS - 1 : 0] rdqs_n = {DM_BITS{1'bz}};`
116
117			`wire [15 : 0] dqs_in = dqs;`
118			`wire [63 : 0] dq_in = dq;`
119
120			`ddr sdramddr (`
121			`clk ,`
122			`clk_n ,`
123			`cke ,`
124			`cs_n ,`
125			`ras_n ,`
126			`cas_n ,`
127			`we_n ,`
128			`ba ,`
129			`a ,`
130			`dm ,`
131			`dq ,`
132			`dqs`
133			`);`
134
135			`// timing definition in tCK units`
136			`real tck ;`
137			`integer tmrd ;`
138			`integer trap ;`
139			`integer tras ;`
140			`integer trc ;`
141			`integer trfc ;`
142			`integer trcd ;`
143			`integer trp ;`
144			`integer trrd ;`
145			`integer twr ;`
146
147			`initial begin`
148			`ifdef period
149			tck = `period ;
150			`else
151			`tck = tCK;`
152			`endif
153			`tmrd = ciel(tMRD/tck);`
154			`trap = ciel(tRAP/tck);`
155			`tras = ciel(tRAS/tck);`
156			`trc = ciel(tRC/tck);`
157			`trfc = ciel(tRFC/tck);`
158			`trcd = ciel(tRCD/tck);`
159			`trp = ciel(tRP/tck);`
160			`trrd = ciel(tRRD/tck);`
161			`twr = ciel(tWR/tck);`
162			`end`
163
164			`initial clk <= 1'b1;`
165			`initial clk_n <= 1'b0;`
166			`always @(posedge clk) begin`
167			`clk <= #(tck/2) 1'b0;`
168			`clk_n <= #(tck/2) 1'b1;`
169			`clk <= #(tck) 1'b1;`
170			`clk_n <= #(tck) 1'b0;`
171			`end`
172
173			`function integer ciel;`
174			`input number;`
175			`real number;`
176			`if (number > $rtoi(number))`
177			`ciel = $rtoi(number) + 1;`
178			`else`
179			`ciel = number;`
180			`endfunction`
181
182			`task power_up;`
183			`begin`
184			`cke <= 1'b0;`
185			`repeat(10) @(negedge clk);`
186			`$display ("%m at time %t TB: A 200 us delay is required before CKE can be brought high.", $time);`
187			`@ (negedge clk) cke = 1'b1;`
188			`nop (400/tck+1);`
189			`end`
190			`endtask`
191
192			`task load_mode;`
193			`input [BA_BITS - 1 : 0] bank;`
194			`input [ADDR_BITS - 1 : 0] addr;`
195			`begin`
196			`case (bank)`
197			`0: mode_reg = addr;`
198			`1: ext_mode_reg = addr;`
199			`endcase`
200			`cke = 1'b1;`
201			`cs_n = 1'b0;`
202			`ras_n = 1'b0;`
203			`cas_n = 1'b0;`
204			`we_n = 1'b0;`
205			`ba = bank;`
206			`a = addr;`
207			`@(negedge clk);`
208			`end`
209			`endtask`
210
211			`task refresh;`
212			`begin`
213			`cke = 1'b1;`
214			`cs_n = 1'b0;`
215			`ras_n = 1'b0;`
216			`cas_n = 1'b0;`
217			`we_n = 1'b1;`
218			`@(negedge clk);`
219			`end`
220			`endtask`
221
222			`task burst_term;`
223			`integer i;`
224			`begin`
225			`cke = 1'b1;`
226			`cs_n = 1'b0;`
227			`ras_n = 1'b1;`
228			`cas_n = 1'b1;`
229			`we_n = 1'b0;`
230			`@(negedge clk);`
231			`for (i=0; i<BL; i=i+1) begin`
232			`dm_fifo[2*RL + i] = {DM_BITS{1'bz}} ;`
233			`dq_fifo[2*RL + i] = {DQ_BITS{1'bz}} ;`
234			`end`
235			`end`
236			`endtask`
237
238			`task self_refresh;`
239			`input count;`
240			`integer count;`
241			`begin`
242			`cke = 1'b0;`
243			`cs_n = 1'b0;`
244			`ras_n = 1'b0;`
245			`cas_n = 1'b0;`
246			`we_n = 1'b1;`
247			`repeat(count) @(negedge clk);`
248			`end`
249			`endtask`
250
251			`task precharge;`
252			`input [BA_BITS - 1 : 0] bank;`
253			`input ap; //precharge all`
254			`begin`
255			`cke = 1'b1;`
256			`cs_n = 1'b0;`
257			`ras_n = 1'b0;`
258			`cas_n = 1'b1;`
259			`we_n = 1'b0;`
260			`ba = bank;`
261			`a = (ap<<10);`
262			`@(negedge clk);`
263			`end`
264			`endtask`
265
266			`task activate;`
267			`input [BA_BITS - 1 : 0] bank;`
268			`input [ADDR_BITS - 1 : 0] row;`
269			`begin`
270			`cke = 1'b1;`
271			`cs_n = 1'b0;`
272			`ras_n = 1'b0;`
273			`cas_n = 1'b1;`
274			`we_n = 1'b1;`
275			`ba = bank;`
276			`a = row;`
277			`@(negedge clk);`
278			`end`
279			`endtask`
280
281			`//write task supports burst lengths <= 16`
282			`task write;`
283			`input [BA_BITS - 1 : 0] bank;`
284			`input [COL_BITS - 1 : 0] col;`
285			`input ap; //Auto Precharge`
286			`input [16*DM_BITS - 1 : 0] dm;`
287			`input [16*DQ_BITS - 1 : 0] dq;`
288			`reg [ADDR_BITS - 1 : 0] atemp [1:0];`
289			`reg [DQ_BITS/DM_BITS - 1 : 0] dm_temp;`
290			`integer i,j;`
291			`begin`
292			`cke = 1'b1;`
293			`cs_n = 1'b0;`
294			`ras_n = 1'b1;`
295			`cas_n = 1'b0;`
296			`we_n = 1'b0;`
297			`ba = bank;`
298			`atemp[0] = col & 10'h3ff; //ADDR[ 9: 0] = COL[ 9: 0]`
299			`atemp[1] = (col>>10)<<11; //ADDR[ N:11] = COL[ N:10]`
300			`a = atemp[0] \| atemp[1] \| (ap<<10);`
301
302			`for (i=0; i<=BL; i=i+1) begin`
303			`dqs_en <= #(WLtck + itck/2) 1'b1;`
304			`if (i%2 === 0) begin`
305			`dqs_out <= #(WLtck + itck/2) {DQS_BITS{1'b0}};`
306			`end else begin`
307			`dqs_out <= #(WLtck + itck/2) {DQS_BITS{1'b1}};`
308			`end`
309			`dq_en <= #(WLtck + itck/2 + tck/4) 1'b1;`
310			`for (j=0; j<DM_BITS; j=j+1) begin`
311			`dm_temp = dm>>((iDM_BITS + j)DQ_BITS/DM_BITS);`
312			`dm_out[j] <= #(WLtck + itck/2 + tck/4) &dm_temp;`
313			`end`
314			`dq_out <= #(WLtck + itck/2 + tck/4) dq>>i*DQ_BITS;`
315			`case (i)`
316			`15: dm_out <= #(WLtck + itck/2 + tck/4) dm[16DM_BITS-1 : 15DM_BITS];`
317			`14: dm_out <= #(WLtck + itck/2 + tck/4) dm[15DM_BITS-1 : 14DM_BITS];`
318			`13: dm_out <= #(WLtck + itck/2 + tck/4) dm[14DM_BITS-1 : 13DM_BITS];`
319			`12: dm_out <= #(WLtck + itck/2 + tck/4) dm[13DM_BITS-1 : 12DM_BITS];`
320			`11: dm_out <= #(WLtck + itck/2 + tck/4) dm[12DM_BITS-1 : 11DM_BITS];`
321			`10: dm_out <= #(WLtck + itck/2 + tck/4) dm[11DM_BITS-1 : 10DM_BITS];`
322			`9: dm_out <= #(WLtck + itck/2 + tck/4) dm[10DM_BITS-1 : 9DM_BITS];`
323			`8: dm_out <= #(WLtck + itck/2 + tck/4) dm[ 9DM_BITS-1 : 8DM_BITS];`
324			`7: dm_out <= #(WLtck + itck/2 + tck/4) dm[ 8DM_BITS-1 : 7DM_BITS];`
325			`6: dm_out <= #(WLtck + itck/2 + tck/4) dm[ 7DM_BITS-1 : 6DM_BITS];`
326			`5: dm_out <= #(WLtck + itck/2 + tck/4) dm[ 6DM_BITS-1 : 5DM_BITS];`
327			`4: dm_out <= #(WLtck + itck/2 + tck/4) dm[ 5DM_BITS-1 : 4DM_BITS];`
328			`3: dm_out <= #(WLtck + itck/2 + tck/4) dm[ 4DM_BITS-1 : 3DM_BITS];`
329			`2: dm_out <= #(WLtck + itck/2 + tck/4) dm[ 3DM_BITS-1 : 2DM_BITS];`
330			`1: dm_out <= #(WLtck + itck/2 + tck/4) dm[ 2DM_BITS-1 : 1DM_BITS];`
331			`0: dm_out <= #(WLtck + itck/2 + tck/4) dm[ 1DM_BITS-1 : 0DM_BITS];`
332			`endcase`
333			`case (i)`
334			`15: dq_out <= #(WLtck + itck/2 + tck/4) dq[16DQ_BITS-1 : 15DQ_BITS];`
335			`14: dq_out <= #(WLtck + itck/2 + tck/4) dq[15DQ_BITS-1 : 14DQ_BITS];`
336			`13: dq_out <= #(WLtck + itck/2 + tck/4) dq[14DQ_BITS-1 : 13DQ_BITS];`
337			`12: dq_out <= #(WLtck + itck/2 + tck/4) dq[13DQ_BITS-1 : 12DQ_BITS];`
338			`11: dq_out <= #(WLtck + itck/2 + tck/4) dq[12DQ_BITS-1 : 11DQ_BITS];`
339			`10: dq_out <= #(WLtck + itck/2 + tck/4) dq[11DQ_BITS-1 : 10DQ_BITS];`
340			`9: dq_out <= #(WLtck + itck/2 + tck/4) dq[10DQ_BITS-1 : 9DQ_BITS];`
341			`8: dq_out <= #(WLtck + itck/2 + tck/4) dq[ 9DQ_BITS-1 : 8DQ_BITS];`
342			`7: dq_out <= #(WLtck + itck/2 + tck/4) dq[ 8DQ_BITS-1 : 7DQ_BITS];`
343			`6: dq_out <= #(WLtck + itck/2 + tck/4) dq[ 7DQ_BITS-1 : 6DQ_BITS];`
344			`5: dq_out <= #(WLtck + itck/2 + tck/4) dq[ 6DQ_BITS-1 : 5DQ_BITS];`
345			`4: dq_out <= #(WLtck + itck/2 + tck/4) dq[ 5DQ_BITS-1 : 4DQ_BITS];`
346			`3: dq_out <= #(WLtck + itck/2 + tck/4) dq[ 4DQ_BITS-1 : 3DQ_BITS];`
347			`2: dq_out <= #(WLtck + itck/2 + tck/4) dq[ 3DQ_BITS-1 : 2DQ_BITS];`
348			`1: dq_out <= #(WLtck + itck/2 + tck/4) dq[ 2DQ_BITS-1 : 1DQ_BITS];`
349			`0: dq_out <= #(WLtck + itck/2 + tck/4) dq[ 1DQ_BITS-1 : 0DQ_BITS];`
350			`endcase`
351			`dq_en <= #(WLtck + itck/2 + tck/4) 1'b1;`
352			`end`
353			`dqs_en <= #(WLtck + BLtck/2 + tck/2) 1'b0;`
354			`dq_en <= #(WLtck + BLtck/2 + tck/4) 1'b0;`
355			`@(negedge clk);`
356			`end`
357			`endtask`
358
359			`task read;`
360			`input [BA_BITS - 1 : 0]bank;`
361			`input [COL_BITS - 1 : 0] col;`
362			`input ap; //Auto Precharge`
363			`reg [ADDR_BITS - 1 : 0] atemp [1:0];`
364			`begin`
365			`cke = 1'b1;`
366			`cs_n = 1'b0;`
367			`ras_n = 1'b1;`
368			`cas_n = 1'b0;`
369			`we_n = 1'b1;`
370			`ba = bank;`
371			`atemp[0] = col & 10'h3ff; //ADDR[ 9: 0] = COL[ 9: 0]`
372			`atemp[1] = (col>>10)<<11; //ADDR[ N:11] = COL[ N:10]`
373			`a = atemp[0] \| atemp[1] \| (ap<<10);`
374			`@(negedge clk);`
375			`end`
376			`endtask`
377
378			`// read with data verification`
379			`task read_verify;`
380			`input [BA_BITS - 1 : 0] bank;`
381			`input [COL_BITS - 1 : 0] col;`
382			`input ap; //Auto Precharge`
383			`input [16*DM_BITS - 1 : 0] dm; //Expected Data Mask`
384			`input [16*DQ_BITS - 1 : 0] dq; //Expected Data`
385			`integer i;`
386			`reg [2:0] brst_col;`
387			`begin`
388			`read (bank, col, ap);`
389			`for (i=0; i<BL; i=i+1) begin`
390			`// perform burst ordering`
391			`brst_col = col ^ i;`
392			`if (!BO) begin`
393			`brst_col = col + i;`
394			`end`
395			`if (BL == 4) begin`
396			`brst_col[2] = 1'b0 ;`
397			`end else if (BL == 2) begin`
398			`brst_col[2:1] = 2'b00 ;`
399			`end`
400			`dm_fifo[2RL + i] = dm >> (iDM_BITS);`
401			`dq_fifo[2RL + i] = dq >> (iDQ_BITS);`
402			`end`
403			`end`
404			`endtask`
405
406			`task nop;`
407			`input count;`
408			`integer count;`
409			`begin`
410			`cke = 1'b1;`
411			`cs_n = 1'b0;`
412			`ras_n = 1'b1;`
413			`cas_n = 1'b1;`
414			`we_n = 1'b1;`
415			`repeat(count) @(negedge clk);`
416			`end`
417			`endtask`
418
419			`task deselect;`
420			`input count;`
421			`integer count;`
422			`begin`
423			`cke = 1'b1;`
424			`cs_n = 1'b1;`
425			`ras_n = 1'b1;`
426			`cas_n = 1'b1;`
427			`we_n = 1'b1;`
428			`repeat(count) @(negedge clk);`
429			`end`
430			`endtask`
431
432			`task power_down;`
433			`input count;`
434			`integer count;`
435			`begin`
436			`cke = 1'b0;`
437			`cs_n = 1'b1;`
438			`ras_n = 1'b1;`
439			`cas_n = 1'b1;`
440			`we_n = 1'b1;`
441			`repeat(count) @(negedge clk);`
442			`end`
443			`endtask`
444
445			`function [16*DQ_BITS - 1 : 0] sort_data;`
446			`input [16*DQ_BITS - 1 : 0] dq;`
447			`input [2:0] col;`
448			`integer i;`
449			`reg [2:0] brst_col;`
450			`reg [DQ_BITS - 1 :0] burst;`
451			`begin`
452			`sort_data = 0;`
453			`for (i=0; i<BL; i=i+1) begin`
454			`// perform burst ordering`
455			`brst_col = col ^ i;`
456			`if (!BO) begin`
457			`brst_col[1:0] = col + i;`
458			`end`
459			`burst = dq >> (brst_col*DQ_BITS);`
460			`sort_data = sort_data \| burst<<(i*DQ_BITS);`
461			`end`
462			`end`
463			`endfunction`
464
465			`// receiver(s) for data_verify process`
466			`always @(dqs_in[0]) begin #(tDQSQ); dqs_receiver(0); end`
467			`always @(dqs_in[1]) begin #(tDQSQ); dqs_receiver(1); end`
468			`always @(dqs_in[2]) begin #(tDQSQ); dqs_receiver(2); end`
469			`always @(dqs_in[3]) begin #(tDQSQ); dqs_receiver(3); end`
470			`always @(dqs_in[4]) begin #(tDQSQ); dqs_receiver(4); end`
471			`always @(dqs_in[5]) begin #(tDQSQ); dqs_receiver(5); end`
472			`always @(dqs_in[6]) begin #(tDQSQ); dqs_receiver(6); end`
473			`always @(dqs_in[7]) begin #(tDQSQ); dqs_receiver(7); end`
474
475			`task dqs_receiver;`
476			`input i;`
477			`integer i;`
478			`begin`
479			`if (dqs_in[i]) begin`
480			`case (i)`
481			`0: dq_in_pos[ 7: 0] <= dq_in[ 7: 0];`
482			`1: dq_in_pos[15: 8] <= dq_in[15: 8];`
483			`2: dq_in_pos[23:16] <= dq_in[23:16];`
484			`3: dq_in_pos[31:24] <= dq_in[31:24];`
485			`4: dq_in_pos[39:32] <= dq_in[39:32];`
486			`5: dq_in_pos[47:40] <= dq_in[47:40];`
487			`6: dq_in_pos[55:48] <= dq_in[55:48];`
488			`7: dq_in_pos[63:56] <= dq_in[63:56];`
489			`endcase`
490			`end else if (!dqs_in[i]) begin`
491			`case (i)`
492			`0: dq_in_neg[ 7: 0] <= dq_in[ 7: 0];`
493			`1: dq_in_neg[15: 8] <= dq_in[15: 8];`
494			`2: dq_in_neg[23:16] <= dq_in[23:16];`
495			`3: dq_in_neg[31:24] <= dq_in[31:24];`
496			`4: dq_in_pos[39:32] <= dq_in[39:32];`
497			`5: dq_in_pos[47:40] <= dq_in[47:40];`
498			`6: dq_in_pos[55:48] <= dq_in[55:48];`
499			`7: dq_in_pos[63:56] <= dq_in[63:56];`
500			`endcase`
501			`end`
502			`end`
503			`endtask`
504
505
506			`// perform data verification as a result of read_verify task call`
507			`always @(clk) begin : data_verify`
508			`integer i;`
509			`reg [DM_BITS-1 : 0] data_mask;`
510			`reg [8*DM_BITS-1 : 0] bit_mask;`
511
512			`for (i=0; i<=14; i=i+1) begin`
513			`dm_fifo[i] = dm_fifo[i+1];`
514			`dq_fifo[i] = dq_fifo[i+1];`
515			`end`
516			`dm_fifo[13] = 'bz;`
517			`dq_fifo[13] = 'bz;`
518			`// dm_fifo[30] = 0;`
519			`// dq_fifo[30] = 0;`
520			`data_mask = dm_fifo[0];`
521
522			`data_mask = dm_fifo[0];`
523			`for (i=0; i<DM_BITS; i=i+1) begin`
524			`bit_mask = {bit_mask, {8{~data_mask[i]}}};`
525			`end`
526			`if (clk) begin`
527			`if ((dq_in_neg & bit_mask) != (dq_fifo[0] & bit_mask))`
528			`$display ("%m at time %t: ERROR: Read data miscompare: Expected = %h, Actual = %h, Mask = %h", $time, dq_fifo[0], dq_in_neg, bit_mask);`
529			`end else begin`
530			`if ((dq_in_pos & bit_mask) != (dq_fifo[0] & bit_mask))`
531			`$display ("%m at time %t: ERROR: Read data miscompare: Expected = %h, Actual = %h, Mask = %h", $time, dq_fifo[0], dq_in_pos, bit_mask);`
532			`end`
533			`end`
534
535
536
537			`reg test_done;`
538			`initial test_done = 0;`
539
540			`// End-of-test triggered in 'subtest.vh'`
541			`always @(test_done) begin : all_done`
542			`if (test_done == 1) begin`
543			`#5000`
544			`$display ("Simulation is Complete");`
545			`$stop(0);`
546			`$finish;`
547			`end`
548			`end`
549
550			`// Test included from external file`
551			`include "subtest.vh"
552
553			`endmodule`