URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [bench/] [bench_defines.v] - Blame information for rev 12

Details | Compare with Previous | View Log


`define FLASH_GENERIC
//`define FLASH_GENERIC_REGISTERED
 
`define SRAM_GENERIC
 
`define UART_DEBUG
 
// Set this to connect sram to slave0 intead of SDRAM for simulation
`define CONFIG_USE_SRAM

Browse

Tools

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [bench/] [bench_defines.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	xianfeng	`define FLASH_GENERIC
2			//`define FLASH_GENERIC_REGISTERED
3
4			`define SRAM_GENERIC
5
6			`define UART_DEBUG
7
8			`// Set this to connect sram to slave0 intead of SDRAM for simulation`
9			`define CONFIG_USE_SRAM