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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [bench/] [generic_pll/] [generic_pll.v] - Blame information for rev 12

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//generic clock generation "PLL" -- DEFINITELY NOT SYNTHESISABLE
//All outputs are synchronous with clk_in
//Divide for clkdiv output set by divider parameter
//Locked signal goes high 8 clocks after reset
//Note the timescale ^^^^^ - cannot be changed!
//19/5/08 - Julius Baxter
 
`timescale  1 ps / 1 ps
 
module generic_pll(/*AUTOARG*/
   // Outputs
   clk1x, clk2x, clkdiv, locked,
   // Inputs
   clk_in, rst_in
   );
 
   input clk_in;
   input rst_in;
   output reg clk1x;
   output reg clk2x;
   output reg clkdiv;
   output reg locked;
 
   parameter  DIVIDER = 8;
 
 
 
   // Locked shiftreg will hold locked low until 8 cycles after reset
   reg [7:0]       locked_shiftreg;
   always @(posedge clk_in or negedge rst_in)
     begin
        if (rst_in) locked_shiftreg <= 8'h0;
        else locked_shiftreg <= {1'b1, locked_shiftreg[7:1]};
     end
 
   always @(posedge clk_in or posedge rst_in)
     begin
        if (rst_in) locked <= 1'b0;
        else
          locked <= locked_shiftreg[0];
 
     end
 
   time   clk_in_edge; //variable to store the times at which we get our edges
   time   clk_in_period [3:0]; // array to store 4 calculated periods
   time   period; //period value used to generate output clocks
 
   // determine clock period
   always @(posedge clk_in or posedge rst_in)
     begin
        if (rst_in == 1) begin
           clk_in_period[0] <= 0;
           clk_in_period[1] <= 0;
           clk_in_period[2] <= 0;
           clk_in_period[3] <= 0;
           clk_in_edge <= 0;
        end
        else begin
           clk_in_edge <= $time;
           clk_in_period[3] <= clk_in_period[2];
           clk_in_period[2] <= clk_in_period[1];
           clk_in_period[1] <= clk_in_period[0];
           if (clk_in_edge != 0)
             clk_in_period[0] <= $time - clk_in_edge;
        end // else: !if(rst_in == 1)
     end // always @ (posedge clk_in or posedge rst_in)
 
   // Calculate average of our clk_in period
   always @(clk_in_period[3] or clk_in_period[2] or
            clk_in_period[1] or clk_in_period[0]) begin
      period <= ((clk_in_period[3] + clk_in_period[2] +
                  clk_in_period[1] + clk_in_period[0])/4);
   end
 
   // generate clk1x out
   always @(posedge clk_in or posedge rst_in)
     if (rst_in)
       clk1x <= 0;
     else begin
        if (clk_in == 1 && locked_shiftreg[0]) begin
           clk1x <= 1;
           #(period / 2) clk1x <= 0;
        end
        else
          clk1x <= 0;
     end
 // generate clk2x out
   always @(posedge clk_in or posedge rst_in)
     if (rst_in)
       clk2x <= 0;
     else begin
        if (clk_in == 1 && locked_shiftreg[0]) begin
           clk2x <= 1;
           #(period / 4) clk2x <= 0;
           #(period / 4) clk2x <= 1;
           #(period / 4) clk2x <= 0;
        end
        else
          clk2x <= 0;
     end
 
   //generate clkdiv out
   always @(posedge clk_in or posedge rst_in)
     if (rst_in)
        clkdiv <= 1'b0;
     else begin
        if (clk_in == 1 && locked_shiftreg[0]) begin
           clkdiv <= 1'b1;
           #(DIVIDER*period/2) clkdiv <= 1'b0;
           #(DIVIDER*period/2);
        end
     end
 
endmodule // generic_pll
 
 

Line No.	Rev	Author	Line
1	12	xianfeng	`//generic clock generation "PLL" -- DEFINITELY NOT SYNTHESISABLE`
2			`//All outputs are synchronous with clk_in`
3			`//Divide for clkdiv output set by divider parameter`
4			`//Locked signal goes high 8 clocks after reset`
5			`//Note the timescale ^^^^^ - cannot be changed!`
6			`//19/5/08 - Julius Baxter`
7
8			`timescale 1 ps / 1 ps
9
10			`module generic_pll(/AUTOARG/`
11			`// Outputs`
12			`clk1x, clk2x, clkdiv, locked,`
13			`// Inputs`
14			`clk_in, rst_in`
15			`);`
16
17			`input clk_in;`
18			`input rst_in;`
19			`output reg clk1x;`
20			`output reg clk2x;`
21			`output reg clkdiv;`
22			`output reg locked;`
23
24			`parameter DIVIDER = 8;`
25
26
27
28			`// Locked shiftreg will hold locked low until 8 cycles after reset`
29			`reg [7:0] locked_shiftreg;`
30			`always @(posedge clk_in or negedge rst_in)`
31			`begin`
32			`if (rst_in) locked_shiftreg <= 8'h0;`
33			`else locked_shiftreg <= {1'b1, locked_shiftreg[7:1]};`
34			`end`
35
36			`always @(posedge clk_in or posedge rst_in)`
37			`begin`
38			`if (rst_in) locked <= 1'b0;`
39			`else`
40			`locked <= locked_shiftreg[0];`
41
42			`end`
43
44			`time clk_in_edge; //variable to store the times at which we get our edges`
45			`time clk_in_period [3:0]; // array to store 4 calculated periods`
46			`time period; //period value used to generate output clocks`
47
48			`// determine clock period`
49			`always @(posedge clk_in or posedge rst_in)`
50			`begin`
51			`if (rst_in == 1) begin`
52			`clk_in_period[0] <= 0;`
53			`clk_in_period[1] <= 0;`
54			`clk_in_period[2] <= 0;`
55			`clk_in_period[3] <= 0;`
56			`clk_in_edge <= 0;`
57			`end`
58			`else begin`
59			`clk_in_edge <= $time;`
60			`clk_in_period[3] <= clk_in_period[2];`
61			`clk_in_period[2] <= clk_in_period[1];`
62			`clk_in_period[1] <= clk_in_period[0];`
63			`if (clk_in_edge != 0)`
64			`clk_in_period[0] <= $time - clk_in_edge;`
65			`end // else: !if(rst_in == 1)`
66			`end // always @ (posedge clk_in or posedge rst_in)`
67
68			`// Calculate average of our clk_in period`
69			`always @(clk_in_period[3] or clk_in_period[2] or`
70			`clk_in_period[1] or clk_in_period[0]) begin`
71			`period <= ((clk_in_period[3] + clk_in_period[2] +`
72			`clk_in_period[1] + clk_in_period[0])/4);`
73			`end`
74
75			`// generate clk1x out`
76			`always @(posedge clk_in or posedge rst_in)`
77			`if (rst_in)`
78			`clk1x <= 0;`
79			`else begin`
80			`if (clk_in == 1 && locked_shiftreg[0]) begin`
81			`clk1x <= 1;`
82			`#(period / 2) clk1x <= 0;`
83			`end`
84			`else`
85			`clk1x <= 0;`
86			`end`
87			`// generate clk2x out`
88			`always @(posedge clk_in or posedge rst_in)`
89			`if (rst_in)`
90			`clk2x <= 0;`
91			`else begin`
92			`if (clk_in == 1 && locked_shiftreg[0]) begin`
93			`clk2x <= 1;`
94			`#(period / 4) clk2x <= 0;`
95			`#(period / 4) clk2x <= 1;`
96			`#(period / 4) clk2x <= 0;`
97			`end`
98			`else`
99			`clk2x <= 0;`
100			`end`
101
102			`//generate clkdiv out`
103			`always @(posedge clk_in or posedge rst_in)`
104			`if (rst_in)`
105			`clkdiv <= 1'b0;`
106			`else begin`
107			`if (clk_in == 1 && locked_shiftreg[0]) begin`
108			`clkdiv <= 1'b1;`
109			`#(DIVIDER*period/2) clkdiv <= 1'b0;`
110			`#(DIVIDER*period/2);`
111			`end`
112			`end`
113
114			`endmodule // generic_pll`
115
116

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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [bench/] [generic_pll/] [generic_pll.v] - Blame information for rev 12