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// This model is the property of Cypress Semiconductor Corp and is protected 
 
// by the US copyright laws, any unauthorized copying and distribution is prohibited.
 
// Cypress reserves the right to change any of the functional specifications without
 
// any prior notice.
 
// Cypress is not liable for any damages which may result from the use of this 
 
// functional model.
 
//This model checks for all the timimg violations and if any timing specifications are violated,the output might be undefined or go to a high impedance state while reading.Please note that the variable "tsim" in this model has to be changed as per your convenience for the simulation time.
 
//      Model:       256Kx16 model 
 
//      Contact:     mpd_apps@cypress.com  
 
//******************************************************************************
`timescale 1 ns/1 ps
 
 
module A256Kx16(Address,dataIO ,OE_bar,CE_bar,WE_bar,BLE_bar, BHE_bar);
 
`define tsim  30000
 
 
 
input [17:0] Address;
inout [15:0]  dataIO ;
input OE_bar,CE_bar,WE_bar, BLE_bar, BHE_bar;
reg   [7:0] temp_array0 [262143:0];
reg   [15:8] temp_array1 [262143:0];
reg   [7:0] mem_array0 [262143:0];
reg   [15:8] mem_array1 [262143:0];
reg   [15:0] data_temp;
reg   [17:0] Address1,Address2,Address3,Address4 ;
reg   [15:0] dataIO1;
reg   ini_cebar,ini_webar,ini_wecebar;
reg   initiate_write1,initiate_write2,initiate_write3;
reg   initiate_read1,initiate_read2;
reg   delayed_WE;
 
time twc ;
time tpwe;
time tsce;
time tsd ;
time trc;
time thzwe;
time tdoe;
 
 
time write_address1,write_data1,write_CE_bar_start1,write_WE_bar_start1;
time write_CE_bar_start,write_WE_bar_start,write_address,write_data;
time read_address,read_CE_bar_start,read_WE_bar_start;
 
initial
  begin
    initiate_write1 = 1'b0;
    initiate_write2 = 1'b0;
    initiate_write3 = 1'b0;
    initiate_read1 =1'b0;
    initiate_read2 =1'b0;
    read_address =0;
    twc =10 ;
    tpwe =7;
    tsce =7 ;
    tsd = 5 ;
    trc =10 ;
    thzwe = 5;
    tdoe = 5;
  end
 
// Added thzwe for WE_bar going low
 
wire [15:0] dataIO =  (!OE_bar && delayed_WE) ?  data_temp[15:0] : 16'bz ;
 
always@(CE_bar or WE_bar or OE_bar or Address or dataIO )
 begin
 
        if ((CE_bar==1'b0) && (WE_bar ==1'b0))
           begin
              Address1 <= Address;
              Address2 <= Address1;
              dataIO1  <= dataIO;
              temp_array0[Address1] <=  dataIO1[7:0] ;
              temp_array1[Address1] <=  dataIO1[15:8] ;
           end
 end
 
always@(negedge CE_bar)
   begin
     write_CE_bar_start <= $time;
     read_CE_bar_start <=$time;
     ini_cebar <= 1'b0;
     ini_wecebar<=1'b0;
   end
 
//*******************Write_cycle**********************
 
always@(posedge CE_bar)
   begin
      if (($time - write_CE_bar_start) >= tsce)
         begin
            if ( (WE_bar == 1'b0) && ( ($time - write_WE_bar_start) >=tpwe) )
              begin
               Address2 <= Address1;
               temp_array0[Address1] <= dataIO1[7:0];
               temp_array1[Address1] <= dataIO1[15:8] ;
               ini_cebar <= 1'b1;
              end
            else
               ini_cebar <= 1'b0;
         end
      else
         begin
           ini_cebar <= 1'b0;
         end
   end
 
always@(negedge WE_bar)
   begin
      write_WE_bar_start <= $time;
      ini_webar <= 1'b0;
      ini_wecebar<=1'b0;
#thzwe delayed_WE <= WE_bar;
 
   end
 
always@(posedge WE_bar  )
   begin
      delayed_WE <= WE_bar;
      read_WE_bar_start <=$time;
      if (($time - write_WE_bar_start) >=tpwe)
         begin
            if ( (CE_bar == 1'b0) && ( ($time - write_CE_bar_start) >= tsce) )
              begin
               Address2 <= Address1;
               temp_array0[Address1] <= dataIO1[7:0];
               temp_array1[Address1] <= dataIO1[15:8] ;
               ini_webar <= 1'b1;
              end
            else
               ini_webar <= 1'b0;
         end
      else
         begin
           ini_webar <= 1'b0;
         end
end
 
always@(CE_bar && WE_bar)
   begin
     if ( (CE_bar ==1'b1) && (WE_bar ==1'b1) )
        begin
           if ( ( ($time - write_WE_bar_start) >=tpwe) && (($time-write_CE_bar_start) >=tsce))
             ini_wecebar <=1'b1;
           else
             ini_wecebar <= 1'b0 ;
        end
     else
        ini_wecebar <=1'b0;
   end
 
always@(dataIO)
  begin
     write_data <= $time;
     write_data1 <=write_data;
     write_WE_bar_start1 <=$time;
     write_CE_bar_start1 <=$time;
     if ( ($time - write_data) >= tsd)
       begin
         if ( (WE_bar == 1'b0) && (CE_bar == 1'b0))
           begin
             if ( ( ($time - write_CE_bar_start) >=tsce) && ( ($time - write_WE_bar_start) >=tpwe) && (($time - write_address) >=twc) )
                initiate_write2 <= 1'b1;
             else
                initiate_write2 <= 1'b0;
           end
       end
  end
 
always@(Address)
  begin
     write_address <= $time;
     write_address1 <= write_address;
     write_WE_bar_start1 <=$time;
     write_CE_bar_start1 <=$time;
     if ( ($time - write_address) >= twc)
       begin
         if ( (WE_bar == 1'b0) &&  (CE_bar ==1'b0))
           begin
             if ( ( ($time - write_CE_bar_start) >=tsce) && ( ($time - write_WE_bar_start) >=tpwe) && (($time - write_data) >=tsd) )
                initiate_write3 <= 1'b1;
             else
                initiate_write3 <= 1'b0;
           end
         else
            initiate_write3 <= 1'b0;
       end
     else
        initiate_write3 <= 1'b0;
  end
 
always@(ini_cebar or ini_webar or ini_wecebar)
  begin
     if ( (ini_cebar == 1'b1) || (ini_webar == 1'b1) || (ini_wecebar == 1'b1) )
       begin
         if ( ( ($time - write_data1) >= tsd) && ( ($time - write_address1) >= twc) )
            initiate_write1 <= 1'b1;
         else
            initiate_write1 <= 1'b0;
       end
     else
       initiate_write1 <= 1'b0;
  end
 
//Removed address change completing a write
// removed initiate_write3
 
//always@(initiate_write2 or initiate_write3)   
 always @(initiate_write2)
begin
     if ( (initiate_write2==1'b1) || (initiate_write3==1'b1))
         begin
            if ( ( ($time - write_WE_bar_start) >=tpwe) && ( ($time - write_CE_bar_start) >=tsce))
              begin
                 if (BLE_bar == 1'b0)
                  mem_array0[Address2] <= temp_array0[Address2];
                 if(BHE_bar == 1'b0)
                  mem_array1[Address2] <= temp_array1[Address2];
              end
         end
      initiate_write2 <=1'b0;
      initiate_write3 <=1'b0;
  end
 
always@( initiate_write1 )
  begin
     if (initiate_write1==1'b1)
         begin
            if ( ( ($time - write_WE_bar_start) >=tpwe) && ( ($time - write_CE_bar_start) >=tsce) && (($time - write_WE_bar_start1) >=tpwe) && (($time - write_CE_bar_start1) >=tsce))
              begin
                 if (BLE_bar == 1'b0)
                  mem_array0[Address2] <= temp_array0[Address2];
 
                if(BHE_bar == 1'b0)
                  mem_array1[Address2] <= temp_array1[Address2];
              end
         end
      initiate_write1 <=1'b0;
   end
 
//*********************Read_cycle******************
 
always@(Address)
   begin
     read_address <=$time;
     Address3 <=Address;
     Address4 <=Address3;
     if ( ($time - read_address) == trc)
       begin
         if ( (CE_bar == 1'b0) && (WE_bar == 1'b1) )
           initiate_read1 <= 1'b1;
         else
           initiate_read1 <= 1'b0;
       end
     else
       initiate_read1 <= 1'b0;
   end
 
always
  #1
  begin
     if ( ($time - read_address) >= trc)
       begin
         if ( (CE_bar == 1'b0) && (WE_bar == 1'b1) )
           begin
             Address4 <=Address3;
             initiate_read2 <= 1'b1;
           end
         else
             initiate_read2 <= 1'b0;
       end
     else
       initiate_read2 <= 1'b0;
   end
initial # `tsim $finish;
 
always@(initiate_read1 or initiate_read2)
   begin
     if ( (initiate_read1 == 1'b1) || (initiate_read2 == 1'b1) )
       begin
         if ( (CE_bar == 1'b0) && (WE_bar ==1'b1) )
           begin
             if ( ( ($time - read_WE_bar_start) >=trc) && ( ($time -read_CE_bar_start) >=trc) )
               begin
                if(BLE_bar == 1'b0)
                  data_temp[7:0] <= mem_array0[Address4];
                else
                  data_temp[7:0] <= 8'bzz;
 
                if(BHE_bar == 1'b0)
                  data_temp[15:8] <= mem_array1[Address4];
                else
                  data_temp[15:8] <= 8'bzz;
               end
             else
               #thzwe data_temp <= 8'bzz;
           end
         else
           #thzwe data_temp <=8'bzz;
       end
        initiate_read1 <=1'b0;
        initiate_read2 <=1'b0;
   end
 
always @(Address)
 begin
   if (CE_bar == 1'b0 && WE_bar == 1'b1 && OE_bar == 1'b0)
     begin
      if (BLE_bar == 1'b0)
        #tdoe data_temp[7:0] <= mem_array0[Address];
      else
        data_temp[7:0] <= 8'bzz;
 
      if (BHE_bar == 1'b0)
        #tdoe data_temp[15:8] <= mem_array1[Address];
      else
        data_temp[15:8] <= 8'bzz;
     end
 end
 
always @(WE_bar or OE_bar or  CE_bar)
 begin
   if (CE_bar == 1'b0 && WE_bar == 1'b1 && OE_bar == 1'b0)
     begin
       if (BLE_bar == 1'b0)
         #tdoe data_temp[7:0] <= mem_array0[Address3];
       if (BHE_bar == 1'b0)
         #tdoe data_temp[15:8] <= mem_array1[Address3];
     end
 end
 
 
endmodule

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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [bench/] [models/] [256Kx16.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	xianfeng	`// This model is the property of Cypress Semiconductor Corp and is protected`
2
3			`// by the US copyright laws, any unauthorized copying and distribution is prohibited.`
4
5			`// Cypress reserves the right to change any of the functional specifications without`
6
7			`// any prior notice.`
8
9			`// Cypress is not liable for any damages which may result from the use of this`
10
11			`// functional model.`
12
13			`//This model checks for all the timimg violations and if any timing specifications are violated,the output might be undefined or go to a high impedance state while reading.Please note that the variable "tsim" in this model has to be changed as per your convenience for the simulation time.`
14
15			`// Model: 256Kx16 model`
16
17			`// Contact: mpd_apps@cypress.com`
18
19			`//******************************************************************************`
20			`timescale 1 ns/1 ps
21
22
23			`module A256Kx16(Address,dataIO ,OE_bar,CE_bar,WE_bar,BLE_bar, BHE_bar);`
24
25			`define tsim 30000
26
27
28
29			`input [17:0] Address;`
30			`inout [15:0] dataIO ;`
31			`input OE_bar,CE_bar,WE_bar, BLE_bar, BHE_bar;`
32			`reg [7:0] temp_array0 [262143:0];`
33			`reg [15:8] temp_array1 [262143:0];`
34			`reg [7:0] mem_array0 [262143:0];`
35			`reg [15:8] mem_array1 [262143:0];`
36			`reg [15:0] data_temp;`
37			`reg [17:0] Address1,Address2,Address3,Address4 ;`
38			`reg [15:0] dataIO1;`
39			`reg ini_cebar,ini_webar,ini_wecebar;`
40			`reg initiate_write1,initiate_write2,initiate_write3;`
41			`reg initiate_read1,initiate_read2;`
42			`reg delayed_WE;`
43
44			`time twc ;`
45			`time tpwe;`
46			`time tsce;`
47			`time tsd ;`
48			`time trc;`
49			`time thzwe;`
50			`time tdoe;`
51
52
53			`time write_address1,write_data1,write_CE_bar_start1,write_WE_bar_start1;`
54			`time write_CE_bar_start,write_WE_bar_start,write_address,write_data;`
55			`time read_address,read_CE_bar_start,read_WE_bar_start;`
56
57			`initial`
58			`begin`
59			`initiate_write1 = 1'b0;`
60			`initiate_write2 = 1'b0;`
61			`initiate_write3 = 1'b0;`
62			`initiate_read1 =1'b0;`
63			`initiate_read2 =1'b0;`
64			`read_address =0;`
65			`twc =10 ;`
66			`tpwe =7;`
67			`tsce =7 ;`
68			`tsd = 5 ;`
69			`trc =10 ;`
70			`thzwe = 5;`
71			`tdoe = 5;`
72			`end`
73
74			`// Added thzwe for WE_bar going low`
75
76			`wire [15:0] dataIO = (!OE_bar && delayed_WE) ? data_temp[15:0] : 16'bz ;`
77
78			`always@(CE_bar or WE_bar or OE_bar or Address or dataIO )`
79			`begin`
80
81			`if ((CE_bar==1'b0) && (WE_bar ==1'b0))`
82			`begin`
83			`Address1 <= Address;`
84			`Address2 <= Address1;`
85			`dataIO1 <= dataIO;`
86			`temp_array0[Address1] <= dataIO1[7:0] ;`
87			`temp_array1[Address1] <= dataIO1[15:8] ;`
88			`end`
89			`end`
90
91			`always@(negedge CE_bar)`
92			`begin`
93			`write_CE_bar_start <= $time;`
94			`read_CE_bar_start <=$time;`
95			`ini_cebar <= 1'b0;`
96			`ini_wecebar<=1'b0;`
97			`end`
98
99			`//*****************Write_cycle********************`
100
101			`always@(posedge CE_bar)`
102			`begin`
103			`if (($time - write_CE_bar_start) >= tsce)`
104			`begin`
105			`if ( (WE_bar == 1'b0) && ( ($time - write_WE_bar_start) >=tpwe) )`
106			`begin`
107			`Address2 <= Address1;`
108			`temp_array0[Address1] <= dataIO1[7:0];`
109			`temp_array1[Address1] <= dataIO1[15:8] ;`
110			`ini_cebar <= 1'b1;`
111			`end`
112			`else`
113			`ini_cebar <= 1'b0;`
114			`end`
115			`else`
116			`begin`
117			`ini_cebar <= 1'b0;`
118			`end`
119			`end`
120
121			`always@(negedge WE_bar)`
122			`begin`
123			`write_WE_bar_start <= $time;`
124			`ini_webar <= 1'b0;`
125			`ini_wecebar<=1'b0;`
126			`#thzwe delayed_WE <= WE_bar;`
127
128			`end`
129
130			`always@(posedge WE_bar )`
131			`begin`
132			`delayed_WE <= WE_bar;`
133			`read_WE_bar_start <=$time;`
134			`if (($time - write_WE_bar_start) >=tpwe)`
135			`begin`
136			`if ( (CE_bar == 1'b0) && ( ($time - write_CE_bar_start) >= tsce) )`
137			`begin`
138			`Address2 <= Address1;`
139			`temp_array0[Address1] <= dataIO1[7:0];`
140			`temp_array1[Address1] <= dataIO1[15:8] ;`
141			`ini_webar <= 1'b1;`
142			`end`
143			`else`
144			`ini_webar <= 1'b0;`
145			`end`
146			`else`
147			`begin`
148			`ini_webar <= 1'b0;`
149			`end`
150			`end`
151
152			`always@(CE_bar && WE_bar)`
153			`begin`
154			`if ( (CE_bar ==1'b1) && (WE_bar ==1'b1) )`
155			`begin`
156			`if ( ( ($time - write_WE_bar_start) >=tpwe) && (($time-write_CE_bar_start) >=tsce))`
157			`ini_wecebar <=1'b1;`
158			`else`
159			`ini_wecebar <= 1'b0 ;`
160			`end`
161			`else`
162			`ini_wecebar <=1'b0;`
163			`end`
164
165			`always@(dataIO)`
166			`begin`
167			`write_data <= $time;`
168			`write_data1 <=write_data;`
169			`write_WE_bar_start1 <=$time;`
170			`write_CE_bar_start1 <=$time;`
171			`if ( ($time - write_data) >= tsd)`
172			`begin`
173			`if ( (WE_bar == 1'b0) && (CE_bar == 1'b0))`
174			`begin`
175			`if ( ( ($time - write_CE_bar_start) >=tsce) && ( ($time - write_WE_bar_start) >=tpwe) && (($time - write_address) >=twc) )`
176			`initiate_write2 <= 1'b1;`
177			`else`
178			`initiate_write2 <= 1'b0;`
179			`end`
180			`end`
181			`end`
182
183			`always@(Address)`
184			`begin`
185			`write_address <= $time;`
186			`write_address1 <= write_address;`
187			`write_WE_bar_start1 <=$time;`
188			`write_CE_bar_start1 <=$time;`
189			`if ( ($time - write_address) >= twc)`
190			`begin`
191			`if ( (WE_bar == 1'b0) && (CE_bar ==1'b0))`
192			`begin`
193			`if ( ( ($time - write_CE_bar_start) >=tsce) && ( ($time - write_WE_bar_start) >=tpwe) && (($time - write_data) >=tsd) )`
194			`initiate_write3 <= 1'b1;`
195			`else`
196			`initiate_write3 <= 1'b0;`
197			`end`
198			`else`
199			`initiate_write3 <= 1'b0;`
200			`end`
201			`else`
202			`initiate_write3 <= 1'b0;`
203			`end`
204
205			`always@(ini_cebar or ini_webar or ini_wecebar)`
206			`begin`
207			`if ( (ini_cebar == 1'b1) \|\| (ini_webar == 1'b1) \|\| (ini_wecebar == 1'b1) )`
208			`begin`
209			`if ( ( ($time - write_data1) >= tsd) && ( ($time - write_address1) >= twc) )`
210			`initiate_write1 <= 1'b1;`
211			`else`
212			`initiate_write1 <= 1'b0;`
213			`end`
214			`else`
215			`initiate_write1 <= 1'b0;`
216			`end`
217
218			`//Removed address change completing a write`
219			`// removed initiate_write3`
220
221			`//always@(initiate_write2 or initiate_write3)`
222			`always @(initiate_write2)`
223			`begin`
224			`if ( (initiate_write2==1'b1) \|\| (initiate_write3==1'b1))`
225			`begin`
226			`if ( ( ($time - write_WE_bar_start) >=tpwe) && ( ($time - write_CE_bar_start) >=tsce))`
227			`begin`
228			`if (BLE_bar == 1'b0)`
229			`mem_array0[Address2] <= temp_array0[Address2];`
230			`if(BHE_bar == 1'b0)`
231			`mem_array1[Address2] <= temp_array1[Address2];`
232			`end`
233			`end`
234			`initiate_write2 <=1'b0;`
235			`initiate_write3 <=1'b0;`
236			`end`
237
238			`always@( initiate_write1 )`
239			`begin`
240			`if (initiate_write1==1'b1)`
241			`begin`
242			`if ( ( ($time - write_WE_bar_start) >=tpwe) && ( ($time - write_CE_bar_start) >=tsce) && (($time - write_WE_bar_start1) >=tpwe) && (($time - write_CE_bar_start1) >=tsce))`
243			`begin`
244			`if (BLE_bar == 1'b0)`
245			`mem_array0[Address2] <= temp_array0[Address2];`
246
247			`if(BHE_bar == 1'b0)`
248			`mem_array1[Address2] <= temp_array1[Address2];`
249			`end`
250			`end`
251			`initiate_write1 <=1'b0;`
252			`end`
253
254			`//*******************Read_cycle****************`
255
256			`always@(Address)`
257			`begin`
258			`read_address <=$time;`
259			`Address3 <=Address;`
260			`Address4 <=Address3;`
261			`if ( ($time - read_address) == trc)`
262			`begin`
263			`if ( (CE_bar == 1'b0) && (WE_bar == 1'b1) )`
264			`initiate_read1 <= 1'b1;`
265			`else`
266			`initiate_read1 <= 1'b0;`
267			`end`
268			`else`
269			`initiate_read1 <= 1'b0;`
270			`end`
271
272			`always`
273			`#1`
274			`begin`
275			`if ( ($time - read_address) >= trc)`
276			`begin`
277			`if ( (CE_bar == 1'b0) && (WE_bar == 1'b1) )`
278			`begin`
279			`Address4 <=Address3;`
280			`initiate_read2 <= 1'b1;`
281			`end`
282			`else`
283			`initiate_read2 <= 1'b0;`
284			`end`
285			`else`
286			`initiate_read2 <= 1'b0;`
287			`end`
288			initial # `tsim $finish;
289
290			`always@(initiate_read1 or initiate_read2)`
291			`begin`
292			`if ( (initiate_read1 == 1'b1) \|\| (initiate_read2 == 1'b1) )`
293			`begin`
294			`if ( (CE_bar == 1'b0) && (WE_bar ==1'b1) )`
295			`begin`
296			`if ( ( ($time - read_WE_bar_start) >=trc) && ( ($time -read_CE_bar_start) >=trc) )`
297			`begin`
298			`if(BLE_bar == 1'b0)`
299			`data_temp[7:0] <= mem_array0[Address4];`
300			`else`
301			`data_temp[7:0] <= 8'bzz;`
302
303			`if(BHE_bar == 1'b0)`
304			`data_temp[15:8] <= mem_array1[Address4];`
305			`else`
306			`data_temp[15:8] <= 8'bzz;`
307			`end`
308			`else`
309			`#thzwe data_temp <= 8'bzz;`
310			`end`
311			`else`
312			`#thzwe data_temp <=8'bzz;`
313			`end`
314			`initiate_read1 <=1'b0;`
315			`initiate_read2 <=1'b0;`
316			`end`
317
318			`always @(Address)`
319			`begin`
320			`if (CE_bar == 1'b0 && WE_bar == 1'b1 && OE_bar == 1'b0)`
321			`begin`
322			`if (BLE_bar == 1'b0)`
323			`#tdoe data_temp[7:0] <= mem_array0[Address];`
324			`else`
325			`data_temp[7:0] <= 8'bzz;`
326
327			`if (BHE_bar == 1'b0)`
328			`#tdoe data_temp[15:8] <= mem_array1[Address];`
329			`else`
330			`data_temp[15:8] <= 8'bzz;`
331			`end`
332			`end`
333
334			`always @(WE_bar or OE_bar or CE_bar)`
335			`begin`
336			`if (CE_bar == 1'b0 && WE_bar == 1'b1 && OE_bar == 1'b0)`
337			`begin`
338			`if (BLE_bar == 1'b0)`
339			`#tdoe data_temp[7:0] <= mem_array0[Address3];`
340			`if (BHE_bar == 1'b0)`
341			`#tdoe data_temp[15:8] <= mem_array1[Address3];`
342			`end`
343			`end`
344
345
346			`endmodule`