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 INTEL DEVELOPER'S SOFTWARE LICENSE AGREEMENT
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TO THE TERMS OF THIS AGREEMENT, PROMPTLY RETURN THE SOFTWARE PACKAGE AND
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ANY ACCOMPANYING ITEMS.
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IF YOU USE THIS SOFTWARE, YOU WILL BE BOUND BY THE TERMS OF THIS
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AGREEMENT
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LICENSE: Intel Corporation ("Intel") grants you the non-exclusive right
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to use the enclosed software program ("Software").  You will not use,
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System OEM Developers may:
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Intel's Byte-Wide SmartVoltage FlashFile(tm) flash memory verilog models
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consist of 4 files.  One file, "bwsvff.v", contains the basic model for
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the flash memory family.  The other files depend upon the device being
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modeled.  One file is used to parametize the model (dp*.v) for the specific
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device.  This file will call out other files to be loaded which include:
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        *.bkb   block beginning addresses
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        *.bke   block ending addresses
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The parameterization file must be loaded into the simulator before the main
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model file "bwsvff.v" as it contains definitions required for the model.
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A test file, test1s3.v, which illustrates the interaction between the
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microprocessor and the flash memory is also included.  This test file can be
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changed to test different scenarios representative of specific applications.
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Another test file, test_bad.v, illustrates the different scenarios resulting
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in the status register signaling error conditions were encountered.

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