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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [bench/] [models/] [512Kx8.v] - Blame information for rev 12

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// This model is the property of Cypress Semiconductor Corp and is protected 
 
// by the US copyright laws, any unauthorized copying and distribution is prohibited.
 
// Cypress reserves the right to change any of the functional specifications without
 
// any prior notice.
 
// Cypress is not liable for any damages which may result from the use of this 
 
// functional model.
 
//This model checks for all the timimg violations and if any timing specifications 
//are violated,the output might be undefined or go to a high impedance state while 
//reading.Please note that the variable "tsim" in this model has to be changed as 
//per your convenience for the simulation time.
 
//      Model:       512Kx8
 
 
//      Contact:     mpd_apps@cypress.com   
 
//******************************************************************************
`timescale 1 ns/1 ps
 
 
module A512Kx8(Address,dataIO ,OE_bar,CE_bar,WE_bar);
 
`define tsim  30000
 
 
 
input [18:0] Address;
inout [7:0]  dataIO ;
input OE_bar,CE_bar,WE_bar;
reg   [7:0] temp_array [524287:0];
reg   [7:0] mem_array [524287:0];
reg   [7:0] data_temp;
reg   [18:0] Address1,Address2,Address3,Address4 ;
reg   [7:0] dataIO1;
reg   ini_cebar,ini_webar,ini_wecebar;
reg   initiate_write1,initiate_write2,initiate_write3;
reg   initiate_read1,initiate_read2;
reg   delayed_WE;
 
integer fsram1;
 
time twc ;
time tpwe;
time tsce;
time tsd ;
time trc;
time thzwe;
time tdoe;
 
 
time write_address1,write_data1,write_CE_bar_start1,write_WE_bar_start1;
time write_CE_bar_start,write_WE_bar_start,write_address,write_data;
time read_address,read_CE_bar_start,read_WE_bar_start;
 
initial
  begin
    initiate_write1 = 1'b0;
    initiate_write2 = 1'b0;
    initiate_write3 = 1'b0;
    initiate_read1 =1'b0;
    initiate_read2 =1'b0;
    read_address =0;
    twc =10 ;
    tpwe =7;
    tsce =7 ;
    tsd = 5 ;
    trc =10 ;
    thzwe = 5;
    tdoe = 5;
//    fsram1 = $fopen("sram1.log");
 
  end
 
// Added thzwe for WE_bar going low
 
wire [7:0] dataIO =  (!OE_bar && delayed_WE) ?  data_temp[7:0] : 8'bz ;
 
always@(CE_bar or WE_bar or OE_bar or Address or dataIO )
 begin
 
        if ((CE_bar==1'b0) && (WE_bar ==1'b0))
           begin
              Address1 <= Address;
              Address2 <= Address1;
              dataIO1  <= dataIO;
              temp_array[Address1] <=  dataIO1[7:0] ;
           end
 end
 
always@(negedge CE_bar)
   begin
     write_CE_bar_start <= $time;
     read_CE_bar_start <=$time;
     ini_cebar <= 1'b0;
     ini_wecebar<=1'b0;
   end
 
//*******************Write_cycle**********************
 
always@(posedge CE_bar)
   begin
      if (($time - write_CE_bar_start) >= tsce)
         begin
            if ( (WE_bar == 1'b0) && ( ($time - write_WE_bar_start) >=tpwe) )
              begin
               Address2 <= Address1;
               temp_array[Address1] <= dataIO1[7:0];
                ini_cebar <= 1'b1;
              end
            else
               ini_cebar <= 1'b0;
         end
      else
         begin
           ini_cebar <= 1'b0;
         end
   end
 
always@(negedge WE_bar)
   begin
      write_WE_bar_start <= $time;
      ini_webar <= 1'b0;
      ini_wecebar<=1'b0;
#thzwe delayed_WE <= WE_bar;
 
   end
 
always@(posedge WE_bar  )
   begin
      delayed_WE <= WE_bar;
      read_WE_bar_start <=$time;
      if (($time - write_WE_bar_start) >=tpwe)
         begin
            if ( (CE_bar == 1'b0) && ( ($time - write_CE_bar_start) >= tsce) )
              begin
               Address2 <= Address1;
               temp_array[Address1] <= dataIO1[7:0];
               ini_webar <= 1'b1;
              end
            else
               ini_webar <= 1'b0;
         end
      else
         begin
           ini_webar <= 1'b0;
         end
end
 
always@(CE_bar && WE_bar)
   begin
     if ( (CE_bar ==1'b1) && (WE_bar ==1'b1) )
        begin
           if ( ( ($time - write_WE_bar_start) >=tpwe) && (($time-write_CE_bar_start) >=tsce))
             ini_wecebar <=1'b1;
           else
             ini_wecebar <= 1'b0 ;
        end
     else
        ini_wecebar <=1'b0;
   end
 
always@(dataIO)
  begin
     write_data <= $time;
     write_data1 <=write_data;
     write_WE_bar_start1 <=$time;
     write_CE_bar_start1 <=$time;
     if ( ($time - write_data) >= tsd)
       begin
         if ( (WE_bar == 1'b0) && (CE_bar == 1'b0))
           begin
             if ( ( ($time - write_CE_bar_start) >=tsce) && ( ($time - write_WE_bar_start) >=tpwe) && (($time - write_address) >=twc) )
                initiate_write2 <= 1'b1;
             else
                initiate_write2 <= 1'b0;
           end
       end
  end
 
always@(Address)
  begin
     write_address <= $time;
     write_address1 <= write_address;
     write_WE_bar_start1 <=$time;
     write_CE_bar_start1 <=$time;
     if ( ($time - write_address) >= twc)
       begin
         if ( (WE_bar == 1'b0) &&  (CE_bar ==1'b0))
           begin
             if ( ( ($time - write_CE_bar_start) >=tsce) && ( ($time - write_WE_bar_start) >=tpwe) && (($time - write_data) >=tsd) )
                initiate_write3 <= 1'b1;
             else
                initiate_write3 <= 1'b0;
           end
         else
            initiate_write3 <= 1'b0;
       end
     else
        initiate_write3 <= 1'b0;
  end
 
always@(ini_cebar or ini_webar or ini_wecebar)
  begin
     if ( (ini_cebar == 1'b1) || (ini_webar == 1'b1) || (ini_wecebar == 1'b1) )
       begin
         if ( ( ($time - write_data1) >= tsd) && ( ($time - write_address1) >= twc) )
            initiate_write1 <= 1'b1;
         else
            initiate_write1 <= 1'b0;
       end
     else
       initiate_write1 <= 1'b0;
  end
 
//Removed address change completing a write
//removed initiate_write3
//always@(initiate_write2 or initiate_write3)   
 
always @(initiate_write2)
  begin
     if ( (initiate_write2==1'b1) || (initiate_write3==1'b1))
         begin
            if ( ( ($time - write_WE_bar_start) >=tpwe) && ( ($time - write_CE_bar_start) >=tsce))
              begin
//               $fdisplay(fsram1, "%t initiate_write2 [%h] <- %h", $time, Address2, temp_array[Address2]);
                  mem_array[Address2] <= temp_array[Address2];
              end
         end
      initiate_write2 <=1'b0;
      initiate_write3 <=1'b0;
  end
 
always@( initiate_write1 )
  begin
     if (initiate_write1==1'b1)
         begin
            if ( ( ($time - write_WE_bar_start) >=tpwe) && ( ($time - write_CE_bar_start) >=tsce)) begin
//&& (($time - write_WE_bar_start1) >=tpwe) && (($time - write_CE_bar_start1) >=tsce))     
//             $fdisplay(fsram1, "%t initiate_write1 [%h] <- %h", $time, Address2, temp_array[Address2]);
               mem_array[Address2] <= temp_array[Address2];
            end
         end
      initiate_write1 <=1'b0;
   end
 
//*********************Read_cycle******************
 
always@(Address)
   begin
     read_address <=$time;
     Address3 <=Address;
     Address4 <=Address3;
     if ( ($time - read_address) == trc)
       begin
         if ( (CE_bar == 1'b0) && (WE_bar == 1'b1) )
           initiate_read1 <= 1'b1;
         else
           initiate_read1 <= 1'b0;
       end
     else
       initiate_read1 <= 1'b0;
   end
 
always
  #1
  begin
     if ( ($time - read_address) >= trc)
       begin
         if ( (CE_bar == 1'b0) && (WE_bar == 1'b1) )
           begin
             Address4 <=Address3;
             initiate_read2 <= 1'b1;
           end
         else
             initiate_read2 <= 1'b0;
       end
     else
       initiate_read2 <= 1'b0;
   end
// initial # `tsim $finish;    
 
always@(initiate_read1 or initiate_read2)
   begin
     if ( (initiate_read1 == 1'b1) || (initiate_read2 == 1'b1) )
       begin
         if ( (CE_bar == 1'b0) && (WE_bar ==1'b1) )
           begin
             if ( ( ($time - read_WE_bar_start) >=trc) && ( ($time -read_CE_bar_start) >=trc) ) begin
//             $fdisplay(fsram1, "%t initiate_read1/2 [%h] -> %h", $time, Address4, mem_array[Address4]);
               data_temp[7:0] <= mem_array[Address4];
             end
           end
         else
           #thzwe data_temp <=8'bzz;
       end
        initiate_read1 <=1'b0;
        initiate_read2 <=1'b0;
   end
 
always @(Address)
 begin
   if (CE_bar == 1'b0 && WE_bar == 1'b1 && OE_bar == 1'b0) begin
        #tdoe data_temp[7:0] <= mem_array[Address];
//        $fdisplay(fsram1, "%m %t Address [%h] -> %h", $time, Address, mem_array[Address]);
   end
 end
 
always @(WE_bar or OE_bar or  CE_bar)
 begin
   if (CE_bar == 1'b0 && WE_bar == 1'b1 && OE_bar == 1'b0) begin
//        $fdisplay(fsram1, "%t WE_bar/OE_bar/CE_bar [%h] -> %h", $time, Address3, mem_array[Address3]);       
         #tdoe data_temp[7:0] <= mem_array[Address3];
   end
 end
 
 
endmodule

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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [bench/] [models/] [512Kx8.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	xianfeng	`// This model is the property of Cypress Semiconductor Corp and is protected`
2
3			`// by the US copyright laws, any unauthorized copying and distribution is prohibited.`
4
5			`// Cypress reserves the right to change any of the functional specifications without`
6
7			`// any prior notice.`
8
9			`// Cypress is not liable for any damages which may result from the use of this`
10
11			`// functional model.`
12
13			`//This model checks for all the timimg violations and if any timing specifications`
14			`//are violated,the output might be undefined or go to a high impedance state while`
15			`//reading.Please note that the variable "tsim" in this model has to be changed as`
16			`//per your convenience for the simulation time.`
17
18			`// Model: 512Kx8`
19
20
21			`// Contact: mpd_apps@cypress.com`
22
23			`//******************************************************************************`
24			`timescale 1 ns/1 ps
25
26
27			`module A512Kx8(Address,dataIO ,OE_bar,CE_bar,WE_bar);`
28
29			`define tsim 30000
30
31
32
33			`input [18:0] Address;`
34			`inout [7:0] dataIO ;`
35			`input OE_bar,CE_bar,WE_bar;`
36			`reg [7:0] temp_array [524287:0];`
37			`reg [7:0] mem_array [524287:0];`
38			`reg [7:0] data_temp;`
39			`reg [18:0] Address1,Address2,Address3,Address4 ;`
40			`reg [7:0] dataIO1;`
41			`reg ini_cebar,ini_webar,ini_wecebar;`
42			`reg initiate_write1,initiate_write2,initiate_write3;`
43			`reg initiate_read1,initiate_read2;`
44			`reg delayed_WE;`
45
46			`integer fsram1;`
47
48			`time twc ;`
49			`time tpwe;`
50			`time tsce;`
51			`time tsd ;`
52			`time trc;`
53			`time thzwe;`
54			`time tdoe;`
55
56
57			`time write_address1,write_data1,write_CE_bar_start1,write_WE_bar_start1;`
58			`time write_CE_bar_start,write_WE_bar_start,write_address,write_data;`
59			`time read_address,read_CE_bar_start,read_WE_bar_start;`
60
61			`initial`
62			`begin`
63			`initiate_write1 = 1'b0;`
64			`initiate_write2 = 1'b0;`
65			`initiate_write3 = 1'b0;`
66			`initiate_read1 =1'b0;`
67			`initiate_read2 =1'b0;`
68			`read_address =0;`
69			`twc =10 ;`
70			`tpwe =7;`
71			`tsce =7 ;`
72			`tsd = 5 ;`
73			`trc =10 ;`
74			`thzwe = 5;`
75			`tdoe = 5;`
76			`// fsram1 = $fopen("sram1.log");`
77
78			`end`
79
80			`// Added thzwe for WE_bar going low`
81
82			`wire [7:0] dataIO = (!OE_bar && delayed_WE) ? data_temp[7:0] : 8'bz ;`
83
84			`always@(CE_bar or WE_bar or OE_bar or Address or dataIO )`
85			`begin`
86
87			`if ((CE_bar==1'b0) && (WE_bar ==1'b0))`
88			`begin`
89			`Address1 <= Address;`
90			`Address2 <= Address1;`
91			`dataIO1 <= dataIO;`
92			`temp_array[Address1] <= dataIO1[7:0] ;`
93			`end`
94			`end`
95
96			`always@(negedge CE_bar)`
97			`begin`
98			`write_CE_bar_start <= $time;`
99			`read_CE_bar_start <=$time;`
100			`ini_cebar <= 1'b0;`
101			`ini_wecebar<=1'b0;`
102			`end`
103
104			`//*****************Write_cycle********************`
105
106			`always@(posedge CE_bar)`
107			`begin`
108			`if (($time - write_CE_bar_start) >= tsce)`
109			`begin`
110			`if ( (WE_bar == 1'b0) && ( ($time - write_WE_bar_start) >=tpwe) )`
111			`begin`
112			`Address2 <= Address1;`
113			`temp_array[Address1] <= dataIO1[7:0];`
114			`ini_cebar <= 1'b1;`
115			`end`
116			`else`
117			`ini_cebar <= 1'b0;`
118			`end`
119			`else`
120			`begin`
121			`ini_cebar <= 1'b0;`
122			`end`
123			`end`
124
125			`always@(negedge WE_bar)`
126			`begin`
127			`write_WE_bar_start <= $time;`
128			`ini_webar <= 1'b0;`
129			`ini_wecebar<=1'b0;`
130			`#thzwe delayed_WE <= WE_bar;`
131
132			`end`
133
134			`always@(posedge WE_bar )`
135			`begin`
136			`delayed_WE <= WE_bar;`
137			`read_WE_bar_start <=$time;`
138			`if (($time - write_WE_bar_start) >=tpwe)`
139			`begin`
140			`if ( (CE_bar == 1'b0) && ( ($time - write_CE_bar_start) >= tsce) )`
141			`begin`
142			`Address2 <= Address1;`
143			`temp_array[Address1] <= dataIO1[7:0];`
144			`ini_webar <= 1'b1;`
145			`end`
146			`else`
147			`ini_webar <= 1'b0;`
148			`end`
149			`else`
150			`begin`
151			`ini_webar <= 1'b0;`
152			`end`
153			`end`
154
155			`always@(CE_bar && WE_bar)`
156			`begin`
157			`if ( (CE_bar ==1'b1) && (WE_bar ==1'b1) )`
158			`begin`
159			`if ( ( ($time - write_WE_bar_start) >=tpwe) && (($time-write_CE_bar_start) >=tsce))`
160			`ini_wecebar <=1'b1;`
161			`else`
162			`ini_wecebar <= 1'b0 ;`
163			`end`
164			`else`
165			`ini_wecebar <=1'b0;`
166			`end`
167
168			`always@(dataIO)`
169			`begin`
170			`write_data <= $time;`
171			`write_data1 <=write_data;`
172			`write_WE_bar_start1 <=$time;`
173			`write_CE_bar_start1 <=$time;`
174			`if ( ($time - write_data) >= tsd)`
175			`begin`
176			`if ( (WE_bar == 1'b0) && (CE_bar == 1'b0))`
177			`begin`
178			`if ( ( ($time - write_CE_bar_start) >=tsce) && ( ($time - write_WE_bar_start) >=tpwe) && (($time - write_address) >=twc) )`
179			`initiate_write2 <= 1'b1;`
180			`else`
181			`initiate_write2 <= 1'b0;`
182			`end`
183			`end`
184			`end`
185
186			`always@(Address)`
187			`begin`
188			`write_address <= $time;`
189			`write_address1 <= write_address;`
190			`write_WE_bar_start1 <=$time;`
191			`write_CE_bar_start1 <=$time;`
192			`if ( ($time - write_address) >= twc)`
193			`begin`
194			`if ( (WE_bar == 1'b0) && (CE_bar ==1'b0))`
195			`begin`
196			`if ( ( ($time - write_CE_bar_start) >=tsce) && ( ($time - write_WE_bar_start) >=tpwe) && (($time - write_data) >=tsd) )`
197			`initiate_write3 <= 1'b1;`
198			`else`
199			`initiate_write3 <= 1'b0;`
200			`end`
201			`else`
202			`initiate_write3 <= 1'b0;`
203			`end`
204			`else`
205			`initiate_write3 <= 1'b0;`
206			`end`
207
208			`always@(ini_cebar or ini_webar or ini_wecebar)`
209			`begin`
210			`if ( (ini_cebar == 1'b1) \|\| (ini_webar == 1'b1) \|\| (ini_wecebar == 1'b1) )`
211			`begin`
212			`if ( ( ($time - write_data1) >= tsd) && ( ($time - write_address1) >= twc) )`
213			`initiate_write1 <= 1'b1;`
214			`else`
215			`initiate_write1 <= 1'b0;`
216			`end`
217			`else`
218			`initiate_write1 <= 1'b0;`
219			`end`
220
221			`//Removed address change completing a write`
222			`//removed initiate_write3`
223			`//always@(initiate_write2 or initiate_write3)`
224
225			`always @(initiate_write2)`
226			`begin`
227			`if ( (initiate_write2==1'b1) \|\| (initiate_write3==1'b1))`
228			`begin`
229			`if ( ( ($time - write_WE_bar_start) >=tpwe) && ( ($time - write_CE_bar_start) >=tsce))`
230			`begin`
231			`// $fdisplay(fsram1, "%t initiate_write2 [%h] <- %h", $time, Address2, temp_array[Address2]);`
232			`mem_array[Address2] <= temp_array[Address2];`
233			`end`
234			`end`
235			`initiate_write2 <=1'b0;`
236			`initiate_write3 <=1'b0;`
237			`end`
238
239			`always@( initiate_write1 )`
240			`begin`
241			`if (initiate_write1==1'b1)`
242			`begin`
243			`if ( ( ($time - write_WE_bar_start) >=tpwe) && ( ($time - write_CE_bar_start) >=tsce)) begin`
244			`//&& (($time - write_WE_bar_start1) >=tpwe) && (($time - write_CE_bar_start1) >=tsce))`
245			`// $fdisplay(fsram1, "%t initiate_write1 [%h] <- %h", $time, Address2, temp_array[Address2]);`
246			`mem_array[Address2] <= temp_array[Address2];`
247			`end`
248			`end`
249			`initiate_write1 <=1'b0;`
250			`end`
251
252			`//*******************Read_cycle****************`
253
254			`always@(Address)`
255			`begin`
256			`read_address <=$time;`
257			`Address3 <=Address;`
258			`Address4 <=Address3;`
259			`if ( ($time - read_address) == trc)`
260			`begin`
261			`if ( (CE_bar == 1'b0) && (WE_bar == 1'b1) )`
262			`initiate_read1 <= 1'b1;`
263			`else`
264			`initiate_read1 <= 1'b0;`
265			`end`
266			`else`
267			`initiate_read1 <= 1'b0;`
268			`end`
269
270			`always`
271			`#1`
272			`begin`
273			`if ( ($time - read_address) >= trc)`
274			`begin`
275			`if ( (CE_bar == 1'b0) && (WE_bar == 1'b1) )`
276			`begin`
277			`Address4 <=Address3;`
278			`initiate_read2 <= 1'b1;`
279			`end`
280			`else`
281			`initiate_read2 <= 1'b0;`
282			`end`
283			`else`
284			`initiate_read2 <= 1'b0;`
285			`end`
286			// initial # `tsim $finish;
287
288			`always@(initiate_read1 or initiate_read2)`
289			`begin`
290			`if ( (initiate_read1 == 1'b1) \|\| (initiate_read2 == 1'b1) )`
291			`begin`
292			`if ( (CE_bar == 1'b0) && (WE_bar ==1'b1) )`
293			`begin`
294			`if ( ( ($time - read_WE_bar_start) >=trc) && ( ($time -read_CE_bar_start) >=trc) ) begin`
295			`// $fdisplay(fsram1, "%t initiate_read1/2 [%h] -> %h", $time, Address4, mem_array[Address4]);`
296			`data_temp[7:0] <= mem_array[Address4];`
297			`end`
298			`end`
299			`else`
300			`#thzwe data_temp <=8'bzz;`
301			`end`
302			`initiate_read1 <=1'b0;`
303			`initiate_read2 <=1'b0;`
304			`end`
305
306			`always @(Address)`
307			`begin`
308			`if (CE_bar == 1'b0 && WE_bar == 1'b1 && OE_bar == 1'b0) begin`
309			`#tdoe data_temp[7:0] <= mem_array[Address];`
310			`// $fdisplay(fsram1, "%m %t Address [%h] -> %h", $time, Address, mem_array[Address]);`
311			`end`
312			`end`
313
314			`always @(WE_bar or OE_bar or CE_bar)`
315			`begin`
316			`if (CE_bar == 1'b0 && WE_bar == 1'b1 && OE_bar == 1'b0) begin`
317			`// $fdisplay(fsram1, "%t WE_bar/OE_bar/CE_bar [%h] -> %h", $time, Address3, mem_array[Address3]);`
318			`#tdoe data_temp[7:0] <= mem_array[Address3];`
319			`end`
320			`end`
321
322
323			`endmodule`