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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [bench/] [models/] [vga_model.v] - Blame information for rev 12

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`include "timescale.v"
 
module vga_model (
        pclk,
        hsyncn,
        vsyncn,
        r,g,b
        );
 
input           pclk;
input           hsyncn;
input           vsyncn;
input [1:0]      r;
input [1:0]      g;
input [1:0]      b;
 
 
endmodule

Line No.	Rev	Author	Line
1	12	xianfeng	`include "timescale.v"
2
3			`module vga_model (`
4			`pclk,`
5			`hsyncn,`
6			`vsyncn,`
7			`r,g,b`
8			`);`
9
10			`input pclk;`
11			`input hsyncn;`
12			`input vsyncn;`
13			`input [1:0] r;`
14			`input [1:0] g;`
15			`input [1:0] b;`
16
17
18			`endmodule`

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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [bench/] [models/] [vga_model.v] - Blame information for rev 12