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xianfeng |
// Copyright (C) 1991-2009 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// *****************************************************************************
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// This file contains a Verilog test bench with test vectors .The test vectors
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// are exported from a vector file in the Quartus Waveform Editor and apply to
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// the top level entity of the current Quartus project .The user can use this
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// testbench to simulate his design using a third-party simulation tool .
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// *****************************************************************************
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// Generated on "10/07/2009 15:47:19"
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// Verilog Self-Checking Test Bench (with test vectors) for design : altera_ram_top
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//
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// Simulation tool : 3rd Party
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//
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`timescale 1 ps/ 1 ps
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module altera_ram_top_vlg_sample_tst(
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wb_adr_i,
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wb_clk_i,
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wb_cyc_i,
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wb_dat_i,
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wb_rst_i,
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wb_sel_i,
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wb_stb_i,
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wb_we_i,
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sampler_tx
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);
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input [31:0] wb_adr_i;
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input wb_clk_i;
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input wb_cyc_i;
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input [31:0] wb_dat_i;
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input wb_rst_i;
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input [3:0] wb_sel_i;
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input wb_stb_i;
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input wb_we_i;
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output sampler_tx;
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reg sample;
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time current_time;
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always @(wb_adr_i or wb_clk_i or wb_cyc_i or wb_dat_i or wb_rst_i or wb_sel_i or wb_stb_i or wb_we_i)
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begin
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if ($time > 0)
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begin
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if ($time == 0 || $time != current_time)
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begin
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if (sample === 1'bx)
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sample = 0;
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else
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sample = ~sample;
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end
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current_time = $time;
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end
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end
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assign sampler_tx = sample;
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endmodule
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module altera_ram_top_vlg_check_tst (
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wb_ack_o,wb_dat_o,wb_err_o,sampler_rx
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);
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input wb_ack_o;
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input [31:0] wb_dat_o;
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input wb_err_o;
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input sampler_rx;
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reg wb_ack_o_expected;
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reg [31:0] wb_dat_o_expected;
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reg wb_err_o_expected;
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reg wb_ack_o_prev;
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reg [31:0] wb_dat_o_prev;
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reg wb_err_o_prev;
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reg wb_ack_o_expected_prev;
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reg [31:0] wb_dat_o_expected_prev;
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reg wb_err_o_expected_prev;
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reg last_wb_ack_o_exp;
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reg [31:0] last_wb_dat_o_exp;
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reg last_wb_err_o_exp;
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reg trigger;
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integer i;
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integer nummismatches;
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reg [1:3] on_first_change ;
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initial
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begin
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trigger = 0;
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i = 0;
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nummismatches = 0;
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on_first_change = 3'b1;
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end
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// update real /o prevs
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always @(trigger)
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begin
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wb_ack_o_prev = wb_ack_o;
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wb_dat_o_prev = wb_dat_o;
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wb_err_o_prev = wb_err_o;
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end
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// update expected /o prevs
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always @(trigger)
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begin
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wb_ack_o_expected_prev = wb_ack_o_expected;
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wb_dat_o_expected_prev = wb_dat_o_expected;
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wb_err_o_expected_prev = wb_err_o_expected;
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end
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// expected wb_ack_o
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initial
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begin
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wb_ack_o_expected = 1'bX;
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end
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// expected wb_dat_o[ 31 ]
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initial
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begin
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wb_dat_o_expected[31] = 1'bX;
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end
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// expected wb_dat_o[ 30 ]
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initial
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begin
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wb_dat_o_expected[30] = 1'bX;
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end
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// expected wb_dat_o[ 29 ]
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initial
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begin
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wb_dat_o_expected[29] = 1'bX;
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end
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// expected wb_dat_o[ 28 ]
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initial
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begin
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wb_dat_o_expected[28] = 1'bX;
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end
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// expected wb_dat_o[ 27 ]
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initial
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begin
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wb_dat_o_expected[27] = 1'bX;
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end
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// expected wb_dat_o[ 26 ]
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initial
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begin
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wb_dat_o_expected[26] = 1'bX;
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end
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// expected wb_dat_o[ 25 ]
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initial
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begin
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wb_dat_o_expected[25] = 1'bX;
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end
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// expected wb_dat_o[ 24 ]
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initial
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begin
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wb_dat_o_expected[24] = 1'bX;
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end
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// expected wb_dat_o[ 23 ]
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initial
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begin
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wb_dat_o_expected[23] = 1'bX;
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end
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// expected wb_dat_o[ 22 ]
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initial
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begin
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wb_dat_o_expected[22] = 1'bX;
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end
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// expected wb_dat_o[ 21 ]
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initial
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begin
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wb_dat_o_expected[21] = 1'bX;
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end
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// expected wb_dat_o[ 20 ]
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initial
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begin
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wb_dat_o_expected[20] = 1'bX;
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end
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// expected wb_dat_o[ 19 ]
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initial
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begin
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wb_dat_o_expected[19] = 1'bX;
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end
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// expected wb_dat_o[ 18 ]
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initial
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begin
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wb_dat_o_expected[18] = 1'bX;
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end
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// expected wb_dat_o[ 17 ]
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initial
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begin
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wb_dat_o_expected[17] = 1'bX;
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end
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// expected wb_dat_o[ 16 ]
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initial
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begin
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wb_dat_o_expected[16] = 1'bX;
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end
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// expected wb_dat_o[ 15 ]
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initial
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begin
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wb_dat_o_expected[15] = 1'bX;
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end
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// expected wb_dat_o[ 14 ]
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initial
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begin
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wb_dat_o_expected[14] = 1'bX;
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end
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// expected wb_dat_o[ 13 ]
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initial
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begin
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wb_dat_o_expected[13] = 1'bX;
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end
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// expected wb_dat_o[ 12 ]
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initial
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begin
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wb_dat_o_expected[12] = 1'bX;
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end
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// expected wb_dat_o[ 11 ]
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initial
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begin
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wb_dat_o_expected[11] = 1'bX;
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end
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// expected wb_dat_o[ 10 ]
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initial
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begin
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wb_dat_o_expected[10] = 1'bX;
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end
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// expected wb_dat_o[ 9 ]
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initial
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begin
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wb_dat_o_expected[9] = 1'bX;
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end
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// expected wb_dat_o[ 8 ]
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initial
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begin
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wb_dat_o_expected[8] = 1'bX;
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end
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// expected wb_dat_o[ 7 ]
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initial
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begin
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wb_dat_o_expected[7] = 1'bX;
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end
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// expected wb_dat_o[ 6 ]
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initial
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begin
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wb_dat_o_expected[6] = 1'bX;
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end
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// expected wb_dat_o[ 5 ]
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initial
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begin
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wb_dat_o_expected[5] = 1'bX;
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end
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// expected wb_dat_o[ 4 ]
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initial
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begin
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wb_dat_o_expected[4] = 1'bX;
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end
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// expected wb_dat_o[ 3 ]
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initial
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begin
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wb_dat_o_expected[3] = 1'bX;
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end
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// expected wb_dat_o[ 2 ]
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initial
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begin
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wb_dat_o_expected[2] = 1'bX;
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end
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// expected wb_dat_o[ 1 ]
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initial
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begin
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wb_dat_o_expected[1] = 1'bX;
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end
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// expected wb_dat_o[ 0 ]
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initial
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begin
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wb_dat_o_expected[0] = 1'bX;
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end
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| 297 |
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// expected wb_err_o
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initial
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begin
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wb_err_o_expected = 1'bX;
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end
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// generate trigger
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always @(wb_ack_o_expected or wb_ack_o or wb_dat_o_expected or wb_dat_o or wb_err_o_expected or wb_err_o)
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begin
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trigger <= ~trigger;
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end
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| 308 |
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always @(posedge sampler_rx or negedge sampler_rx)
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begin
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`ifdef debug_tbench
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$display("Scanning pattern %d @time = %t",i,$realtime );
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i = i + 1;
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$display("| expected wb_ack_o = %b | expected wb_dat_o = %b | expected wb_err_o = %b | ",wb_ack_o_expected_prev,wb_dat_o_expected_prev,wb_err_o_expected_prev);
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$display("| real wb_ack_o = %b | real wb_dat_o = %b | real wb_err_o = %b | ",wb_ack_o_prev,wb_dat_o_prev,wb_err_o_prev);
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`endif
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if (
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| 317 |
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( wb_ack_o_expected_prev !== 1'bx ) && ( wb_ack_o_prev !== wb_ack_o_expected_prev )
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&& ((wb_ack_o_expected_prev !== last_wb_ack_o_exp) ||
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on_first_change[1])
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)
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| 321 |
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begin
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| 322 |
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$display ("ERROR! Vector Mismatch for output port wb_ack_o :: @time = %t", $realtime);
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| 323 |
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$display (" Expected value = %b", wb_ack_o_expected_prev);
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| 324 |
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$display (" Real value = %b", wb_ack_o_prev);
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nummismatches = nummismatches + 1;
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on_first_change[1] = 1'b0;
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last_wb_ack_o_exp = wb_ack_o_expected_prev;
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end
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if (
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| 330 |
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( wb_dat_o_expected_prev[0] !== 1'bx ) && ( wb_dat_o_prev[0] !== wb_dat_o_expected_prev[0] )
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| 331 |
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&& ((wb_dat_o_expected_prev[0] !== last_wb_dat_o_exp[0]) ||
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on_first_change[2])
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| 333 |
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)
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| 334 |
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begin
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| 335 |
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$display ("ERROR! Vector Mismatch for output port wb_dat_o[0] :: @time = %t", $realtime);
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| 336 |
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$display (" Expected value = %b", wb_dat_o_expected_prev);
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| 337 |
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$display (" Real value = %b", wb_dat_o_prev);
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| 338 |
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nummismatches = nummismatches + 1;
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| 339 |
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on_first_change[2] = 1'b0;
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| 340 |
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last_wb_dat_o_exp[0] = wb_dat_o_expected_prev[0];
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| 341 |
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end
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| 342 |
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if (
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| 343 |
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( wb_dat_o_expected_prev[1] !== 1'bx ) && ( wb_dat_o_prev[1] !== wb_dat_o_expected_prev[1] )
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| 344 |
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&& ((wb_dat_o_expected_prev[1] !== last_wb_dat_o_exp[1]) ||
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on_first_change[2])
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| 346 |
|
|
)
|
| 347 |
|
|
begin
|
| 348 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[1] :: @time = %t", $realtime);
|
| 349 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 350 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 351 |
|
|
nummismatches = nummismatches + 1;
|
| 352 |
|
|
on_first_change[2] = 1'b0;
|
| 353 |
|
|
last_wb_dat_o_exp[1] = wb_dat_o_expected_prev[1];
|
| 354 |
|
|
end
|
| 355 |
|
|
if (
|
| 356 |
|
|
( wb_dat_o_expected_prev[2] !== 1'bx ) && ( wb_dat_o_prev[2] !== wb_dat_o_expected_prev[2] )
|
| 357 |
|
|
&& ((wb_dat_o_expected_prev[2] !== last_wb_dat_o_exp[2]) ||
|
| 358 |
|
|
on_first_change[2])
|
| 359 |
|
|
)
|
| 360 |
|
|
begin
|
| 361 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[2] :: @time = %t", $realtime);
|
| 362 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 363 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 364 |
|
|
nummismatches = nummismatches + 1;
|
| 365 |
|
|
on_first_change[2] = 1'b0;
|
| 366 |
|
|
last_wb_dat_o_exp[2] = wb_dat_o_expected_prev[2];
|
| 367 |
|
|
end
|
| 368 |
|
|
if (
|
| 369 |
|
|
( wb_dat_o_expected_prev[3] !== 1'bx ) && ( wb_dat_o_prev[3] !== wb_dat_o_expected_prev[3] )
|
| 370 |
|
|
&& ((wb_dat_o_expected_prev[3] !== last_wb_dat_o_exp[3]) ||
|
| 371 |
|
|
on_first_change[2])
|
| 372 |
|
|
)
|
| 373 |
|
|
begin
|
| 374 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[3] :: @time = %t", $realtime);
|
| 375 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 376 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 377 |
|
|
nummismatches = nummismatches + 1;
|
| 378 |
|
|
on_first_change[2] = 1'b0;
|
| 379 |
|
|
last_wb_dat_o_exp[3] = wb_dat_o_expected_prev[3];
|
| 380 |
|
|
end
|
| 381 |
|
|
if (
|
| 382 |
|
|
( wb_dat_o_expected_prev[4] !== 1'bx ) && ( wb_dat_o_prev[4] !== wb_dat_o_expected_prev[4] )
|
| 383 |
|
|
&& ((wb_dat_o_expected_prev[4] !== last_wb_dat_o_exp[4]) ||
|
| 384 |
|
|
on_first_change[2])
|
| 385 |
|
|
)
|
| 386 |
|
|
begin
|
| 387 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[4] :: @time = %t", $realtime);
|
| 388 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 389 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 390 |
|
|
nummismatches = nummismatches + 1;
|
| 391 |
|
|
on_first_change[2] = 1'b0;
|
| 392 |
|
|
last_wb_dat_o_exp[4] = wb_dat_o_expected_prev[4];
|
| 393 |
|
|
end
|
| 394 |
|
|
if (
|
| 395 |
|
|
( wb_dat_o_expected_prev[5] !== 1'bx ) && ( wb_dat_o_prev[5] !== wb_dat_o_expected_prev[5] )
|
| 396 |
|
|
&& ((wb_dat_o_expected_prev[5] !== last_wb_dat_o_exp[5]) ||
|
| 397 |
|
|
on_first_change[2])
|
| 398 |
|
|
)
|
| 399 |
|
|
begin
|
| 400 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[5] :: @time = %t", $realtime);
|
| 401 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 402 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 403 |
|
|
nummismatches = nummismatches + 1;
|
| 404 |
|
|
on_first_change[2] = 1'b0;
|
| 405 |
|
|
last_wb_dat_o_exp[5] = wb_dat_o_expected_prev[5];
|
| 406 |
|
|
end
|
| 407 |
|
|
if (
|
| 408 |
|
|
( wb_dat_o_expected_prev[6] !== 1'bx ) && ( wb_dat_o_prev[6] !== wb_dat_o_expected_prev[6] )
|
| 409 |
|
|
&& ((wb_dat_o_expected_prev[6] !== last_wb_dat_o_exp[6]) ||
|
| 410 |
|
|
on_first_change[2])
|
| 411 |
|
|
)
|
| 412 |
|
|
begin
|
| 413 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[6] :: @time = %t", $realtime);
|
| 414 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 415 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 416 |
|
|
nummismatches = nummismatches + 1;
|
| 417 |
|
|
on_first_change[2] = 1'b0;
|
| 418 |
|
|
last_wb_dat_o_exp[6] = wb_dat_o_expected_prev[6];
|
| 419 |
|
|
end
|
| 420 |
|
|
if (
|
| 421 |
|
|
( wb_dat_o_expected_prev[7] !== 1'bx ) && ( wb_dat_o_prev[7] !== wb_dat_o_expected_prev[7] )
|
| 422 |
|
|
&& ((wb_dat_o_expected_prev[7] !== last_wb_dat_o_exp[7]) ||
|
| 423 |
|
|
on_first_change[2])
|
| 424 |
|
|
)
|
| 425 |
|
|
begin
|
| 426 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[7] :: @time = %t", $realtime);
|
| 427 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 428 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 429 |
|
|
nummismatches = nummismatches + 1;
|
| 430 |
|
|
on_first_change[2] = 1'b0;
|
| 431 |
|
|
last_wb_dat_o_exp[7] = wb_dat_o_expected_prev[7];
|
| 432 |
|
|
end
|
| 433 |
|
|
if (
|
| 434 |
|
|
( wb_dat_o_expected_prev[8] !== 1'bx ) && ( wb_dat_o_prev[8] !== wb_dat_o_expected_prev[8] )
|
| 435 |
|
|
&& ((wb_dat_o_expected_prev[8] !== last_wb_dat_o_exp[8]) ||
|
| 436 |
|
|
on_first_change[2])
|
| 437 |
|
|
)
|
| 438 |
|
|
begin
|
| 439 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[8] :: @time = %t", $realtime);
|
| 440 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 441 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 442 |
|
|
nummismatches = nummismatches + 1;
|
| 443 |
|
|
on_first_change[2] = 1'b0;
|
| 444 |
|
|
last_wb_dat_o_exp[8] = wb_dat_o_expected_prev[8];
|
| 445 |
|
|
end
|
| 446 |
|
|
if (
|
| 447 |
|
|
( wb_dat_o_expected_prev[9] !== 1'bx ) && ( wb_dat_o_prev[9] !== wb_dat_o_expected_prev[9] )
|
| 448 |
|
|
&& ((wb_dat_o_expected_prev[9] !== last_wb_dat_o_exp[9]) ||
|
| 449 |
|
|
on_first_change[2])
|
| 450 |
|
|
)
|
| 451 |
|
|
begin
|
| 452 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[9] :: @time = %t", $realtime);
|
| 453 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 454 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 455 |
|
|
nummismatches = nummismatches + 1;
|
| 456 |
|
|
on_first_change[2] = 1'b0;
|
| 457 |
|
|
last_wb_dat_o_exp[9] = wb_dat_o_expected_prev[9];
|
| 458 |
|
|
end
|
| 459 |
|
|
if (
|
| 460 |
|
|
( wb_dat_o_expected_prev[10] !== 1'bx ) && ( wb_dat_o_prev[10] !== wb_dat_o_expected_prev[10] )
|
| 461 |
|
|
&& ((wb_dat_o_expected_prev[10] !== last_wb_dat_o_exp[10]) ||
|
| 462 |
|
|
on_first_change[2])
|
| 463 |
|
|
)
|
| 464 |
|
|
begin
|
| 465 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[10] :: @time = %t", $realtime);
|
| 466 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 467 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 468 |
|
|
nummismatches = nummismatches + 1;
|
| 469 |
|
|
on_first_change[2] = 1'b0;
|
| 470 |
|
|
last_wb_dat_o_exp[10] = wb_dat_o_expected_prev[10];
|
| 471 |
|
|
end
|
| 472 |
|
|
if (
|
| 473 |
|
|
( wb_dat_o_expected_prev[11] !== 1'bx ) && ( wb_dat_o_prev[11] !== wb_dat_o_expected_prev[11] )
|
| 474 |
|
|
&& ((wb_dat_o_expected_prev[11] !== last_wb_dat_o_exp[11]) ||
|
| 475 |
|
|
on_first_change[2])
|
| 476 |
|
|
)
|
| 477 |
|
|
begin
|
| 478 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[11] :: @time = %t", $realtime);
|
| 479 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 480 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 481 |
|
|
nummismatches = nummismatches + 1;
|
| 482 |
|
|
on_first_change[2] = 1'b0;
|
| 483 |
|
|
last_wb_dat_o_exp[11] = wb_dat_o_expected_prev[11];
|
| 484 |
|
|
end
|
| 485 |
|
|
if (
|
| 486 |
|
|
( wb_dat_o_expected_prev[12] !== 1'bx ) && ( wb_dat_o_prev[12] !== wb_dat_o_expected_prev[12] )
|
| 487 |
|
|
&& ((wb_dat_o_expected_prev[12] !== last_wb_dat_o_exp[12]) ||
|
| 488 |
|
|
on_first_change[2])
|
| 489 |
|
|
)
|
| 490 |
|
|
begin
|
| 491 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[12] :: @time = %t", $realtime);
|
| 492 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 493 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 494 |
|
|
nummismatches = nummismatches + 1;
|
| 495 |
|
|
on_first_change[2] = 1'b0;
|
| 496 |
|
|
last_wb_dat_o_exp[12] = wb_dat_o_expected_prev[12];
|
| 497 |
|
|
end
|
| 498 |
|
|
if (
|
| 499 |
|
|
( wb_dat_o_expected_prev[13] !== 1'bx ) && ( wb_dat_o_prev[13] !== wb_dat_o_expected_prev[13] )
|
| 500 |
|
|
&& ((wb_dat_o_expected_prev[13] !== last_wb_dat_o_exp[13]) ||
|
| 501 |
|
|
on_first_change[2])
|
| 502 |
|
|
)
|
| 503 |
|
|
begin
|
| 504 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[13] :: @time = %t", $realtime);
|
| 505 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 506 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 507 |
|
|
nummismatches = nummismatches + 1;
|
| 508 |
|
|
on_first_change[2] = 1'b0;
|
| 509 |
|
|
last_wb_dat_o_exp[13] = wb_dat_o_expected_prev[13];
|
| 510 |
|
|
end
|
| 511 |
|
|
if (
|
| 512 |
|
|
( wb_dat_o_expected_prev[14] !== 1'bx ) && ( wb_dat_o_prev[14] !== wb_dat_o_expected_prev[14] )
|
| 513 |
|
|
&& ((wb_dat_o_expected_prev[14] !== last_wb_dat_o_exp[14]) ||
|
| 514 |
|
|
on_first_change[2])
|
| 515 |
|
|
)
|
| 516 |
|
|
begin
|
| 517 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[14] :: @time = %t", $realtime);
|
| 518 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 519 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 520 |
|
|
nummismatches = nummismatches + 1;
|
| 521 |
|
|
on_first_change[2] = 1'b0;
|
| 522 |
|
|
last_wb_dat_o_exp[14] = wb_dat_o_expected_prev[14];
|
| 523 |
|
|
end
|
| 524 |
|
|
if (
|
| 525 |
|
|
( wb_dat_o_expected_prev[15] !== 1'bx ) && ( wb_dat_o_prev[15] !== wb_dat_o_expected_prev[15] )
|
| 526 |
|
|
&& ((wb_dat_o_expected_prev[15] !== last_wb_dat_o_exp[15]) ||
|
| 527 |
|
|
on_first_change[2])
|
| 528 |
|
|
)
|
| 529 |
|
|
begin
|
| 530 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[15] :: @time = %t", $realtime);
|
| 531 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 532 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 533 |
|
|
nummismatches = nummismatches + 1;
|
| 534 |
|
|
on_first_change[2] = 1'b0;
|
| 535 |
|
|
last_wb_dat_o_exp[15] = wb_dat_o_expected_prev[15];
|
| 536 |
|
|
end
|
| 537 |
|
|
if (
|
| 538 |
|
|
( wb_dat_o_expected_prev[16] !== 1'bx ) && ( wb_dat_o_prev[16] !== wb_dat_o_expected_prev[16] )
|
| 539 |
|
|
&& ((wb_dat_o_expected_prev[16] !== last_wb_dat_o_exp[16]) ||
|
| 540 |
|
|
on_first_change[2])
|
| 541 |
|
|
)
|
| 542 |
|
|
begin
|
| 543 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[16] :: @time = %t", $realtime);
|
| 544 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 545 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 546 |
|
|
nummismatches = nummismatches + 1;
|
| 547 |
|
|
on_first_change[2] = 1'b0;
|
| 548 |
|
|
last_wb_dat_o_exp[16] = wb_dat_o_expected_prev[16];
|
| 549 |
|
|
end
|
| 550 |
|
|
if (
|
| 551 |
|
|
( wb_dat_o_expected_prev[17] !== 1'bx ) && ( wb_dat_o_prev[17] !== wb_dat_o_expected_prev[17] )
|
| 552 |
|
|
&& ((wb_dat_o_expected_prev[17] !== last_wb_dat_o_exp[17]) ||
|
| 553 |
|
|
on_first_change[2])
|
| 554 |
|
|
)
|
| 555 |
|
|
begin
|
| 556 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[17] :: @time = %t", $realtime);
|
| 557 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 558 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 559 |
|
|
nummismatches = nummismatches + 1;
|
| 560 |
|
|
on_first_change[2] = 1'b0;
|
| 561 |
|
|
last_wb_dat_o_exp[17] = wb_dat_o_expected_prev[17];
|
| 562 |
|
|
end
|
| 563 |
|
|
if (
|
| 564 |
|
|
( wb_dat_o_expected_prev[18] !== 1'bx ) && ( wb_dat_o_prev[18] !== wb_dat_o_expected_prev[18] )
|
| 565 |
|
|
&& ((wb_dat_o_expected_prev[18] !== last_wb_dat_o_exp[18]) ||
|
| 566 |
|
|
on_first_change[2])
|
| 567 |
|
|
)
|
| 568 |
|
|
begin
|
| 569 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[18] :: @time = %t", $realtime);
|
| 570 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 571 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 572 |
|
|
nummismatches = nummismatches + 1;
|
| 573 |
|
|
on_first_change[2] = 1'b0;
|
| 574 |
|
|
last_wb_dat_o_exp[18] = wb_dat_o_expected_prev[18];
|
| 575 |
|
|
end
|
| 576 |
|
|
if (
|
| 577 |
|
|
( wb_dat_o_expected_prev[19] !== 1'bx ) && ( wb_dat_o_prev[19] !== wb_dat_o_expected_prev[19] )
|
| 578 |
|
|
&& ((wb_dat_o_expected_prev[19] !== last_wb_dat_o_exp[19]) ||
|
| 579 |
|
|
on_first_change[2])
|
| 580 |
|
|
)
|
| 581 |
|
|
begin
|
| 582 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[19] :: @time = %t", $realtime);
|
| 583 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 584 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 585 |
|
|
nummismatches = nummismatches + 1;
|
| 586 |
|
|
on_first_change[2] = 1'b0;
|
| 587 |
|
|
last_wb_dat_o_exp[19] = wb_dat_o_expected_prev[19];
|
| 588 |
|
|
end
|
| 589 |
|
|
if (
|
| 590 |
|
|
( wb_dat_o_expected_prev[20] !== 1'bx ) && ( wb_dat_o_prev[20] !== wb_dat_o_expected_prev[20] )
|
| 591 |
|
|
&& ((wb_dat_o_expected_prev[20] !== last_wb_dat_o_exp[20]) ||
|
| 592 |
|
|
on_first_change[2])
|
| 593 |
|
|
)
|
| 594 |
|
|
begin
|
| 595 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[20] :: @time = %t", $realtime);
|
| 596 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 597 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 598 |
|
|
nummismatches = nummismatches + 1;
|
| 599 |
|
|
on_first_change[2] = 1'b0;
|
| 600 |
|
|
last_wb_dat_o_exp[20] = wb_dat_o_expected_prev[20];
|
| 601 |
|
|
end
|
| 602 |
|
|
if (
|
| 603 |
|
|
( wb_dat_o_expected_prev[21] !== 1'bx ) && ( wb_dat_o_prev[21] !== wb_dat_o_expected_prev[21] )
|
| 604 |
|
|
&& ((wb_dat_o_expected_prev[21] !== last_wb_dat_o_exp[21]) ||
|
| 605 |
|
|
on_first_change[2])
|
| 606 |
|
|
)
|
| 607 |
|
|
begin
|
| 608 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[21] :: @time = %t", $realtime);
|
| 609 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 610 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 611 |
|
|
nummismatches = nummismatches + 1;
|
| 612 |
|
|
on_first_change[2] = 1'b0;
|
| 613 |
|
|
last_wb_dat_o_exp[21] = wb_dat_o_expected_prev[21];
|
| 614 |
|
|
end
|
| 615 |
|
|
if (
|
| 616 |
|
|
( wb_dat_o_expected_prev[22] !== 1'bx ) && ( wb_dat_o_prev[22] !== wb_dat_o_expected_prev[22] )
|
| 617 |
|
|
&& ((wb_dat_o_expected_prev[22] !== last_wb_dat_o_exp[22]) ||
|
| 618 |
|
|
on_first_change[2])
|
| 619 |
|
|
)
|
| 620 |
|
|
begin
|
| 621 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[22] :: @time = %t", $realtime);
|
| 622 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 623 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 624 |
|
|
nummismatches = nummismatches + 1;
|
| 625 |
|
|
on_first_change[2] = 1'b0;
|
| 626 |
|
|
last_wb_dat_o_exp[22] = wb_dat_o_expected_prev[22];
|
| 627 |
|
|
end
|
| 628 |
|
|
if (
|
| 629 |
|
|
( wb_dat_o_expected_prev[23] !== 1'bx ) && ( wb_dat_o_prev[23] !== wb_dat_o_expected_prev[23] )
|
| 630 |
|
|
&& ((wb_dat_o_expected_prev[23] !== last_wb_dat_o_exp[23]) ||
|
| 631 |
|
|
on_first_change[2])
|
| 632 |
|
|
)
|
| 633 |
|
|
begin
|
| 634 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[23] :: @time = %t", $realtime);
|
| 635 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 636 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 637 |
|
|
nummismatches = nummismatches + 1;
|
| 638 |
|
|
on_first_change[2] = 1'b0;
|
| 639 |
|
|
last_wb_dat_o_exp[23] = wb_dat_o_expected_prev[23];
|
| 640 |
|
|
end
|
| 641 |
|
|
if (
|
| 642 |
|
|
( wb_dat_o_expected_prev[24] !== 1'bx ) && ( wb_dat_o_prev[24] !== wb_dat_o_expected_prev[24] )
|
| 643 |
|
|
&& ((wb_dat_o_expected_prev[24] !== last_wb_dat_o_exp[24]) ||
|
| 644 |
|
|
on_first_change[2])
|
| 645 |
|
|
)
|
| 646 |
|
|
begin
|
| 647 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[24] :: @time = %t", $realtime);
|
| 648 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 649 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 650 |
|
|
nummismatches = nummismatches + 1;
|
| 651 |
|
|
on_first_change[2] = 1'b0;
|
| 652 |
|
|
last_wb_dat_o_exp[24] = wb_dat_o_expected_prev[24];
|
| 653 |
|
|
end
|
| 654 |
|
|
if (
|
| 655 |
|
|
( wb_dat_o_expected_prev[25] !== 1'bx ) && ( wb_dat_o_prev[25] !== wb_dat_o_expected_prev[25] )
|
| 656 |
|
|
&& ((wb_dat_o_expected_prev[25] !== last_wb_dat_o_exp[25]) ||
|
| 657 |
|
|
on_first_change[2])
|
| 658 |
|
|
)
|
| 659 |
|
|
begin
|
| 660 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[25] :: @time = %t", $realtime);
|
| 661 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 662 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 663 |
|
|
nummismatches = nummismatches + 1;
|
| 664 |
|
|
on_first_change[2] = 1'b0;
|
| 665 |
|
|
last_wb_dat_o_exp[25] = wb_dat_o_expected_prev[25];
|
| 666 |
|
|
end
|
| 667 |
|
|
if (
|
| 668 |
|
|
( wb_dat_o_expected_prev[26] !== 1'bx ) && ( wb_dat_o_prev[26] !== wb_dat_o_expected_prev[26] )
|
| 669 |
|
|
&& ((wb_dat_o_expected_prev[26] !== last_wb_dat_o_exp[26]) ||
|
| 670 |
|
|
on_first_change[2])
|
| 671 |
|
|
)
|
| 672 |
|
|
begin
|
| 673 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[26] :: @time = %t", $realtime);
|
| 674 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 675 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 676 |
|
|
nummismatches = nummismatches + 1;
|
| 677 |
|
|
on_first_change[2] = 1'b0;
|
| 678 |
|
|
last_wb_dat_o_exp[26] = wb_dat_o_expected_prev[26];
|
| 679 |
|
|
end
|
| 680 |
|
|
if (
|
| 681 |
|
|
( wb_dat_o_expected_prev[27] !== 1'bx ) && ( wb_dat_o_prev[27] !== wb_dat_o_expected_prev[27] )
|
| 682 |
|
|
&& ((wb_dat_o_expected_prev[27] !== last_wb_dat_o_exp[27]) ||
|
| 683 |
|
|
on_first_change[2])
|
| 684 |
|
|
)
|
| 685 |
|
|
begin
|
| 686 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[27] :: @time = %t", $realtime);
|
| 687 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 688 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 689 |
|
|
nummismatches = nummismatches + 1;
|
| 690 |
|
|
on_first_change[2] = 1'b0;
|
| 691 |
|
|
last_wb_dat_o_exp[27] = wb_dat_o_expected_prev[27];
|
| 692 |
|
|
end
|
| 693 |
|
|
if (
|
| 694 |
|
|
( wb_dat_o_expected_prev[28] !== 1'bx ) && ( wb_dat_o_prev[28] !== wb_dat_o_expected_prev[28] )
|
| 695 |
|
|
&& ((wb_dat_o_expected_prev[28] !== last_wb_dat_o_exp[28]) ||
|
| 696 |
|
|
on_first_change[2])
|
| 697 |
|
|
)
|
| 698 |
|
|
begin
|
| 699 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[28] :: @time = %t", $realtime);
|
| 700 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 701 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 702 |
|
|
nummismatches = nummismatches + 1;
|
| 703 |
|
|
on_first_change[2] = 1'b0;
|
| 704 |
|
|
last_wb_dat_o_exp[28] = wb_dat_o_expected_prev[28];
|
| 705 |
|
|
end
|
| 706 |
|
|
if (
|
| 707 |
|
|
( wb_dat_o_expected_prev[29] !== 1'bx ) && ( wb_dat_o_prev[29] !== wb_dat_o_expected_prev[29] )
|
| 708 |
|
|
&& ((wb_dat_o_expected_prev[29] !== last_wb_dat_o_exp[29]) ||
|
| 709 |
|
|
on_first_change[2])
|
| 710 |
|
|
)
|
| 711 |
|
|
begin
|
| 712 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[29] :: @time = %t", $realtime);
|
| 713 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 714 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 715 |
|
|
nummismatches = nummismatches + 1;
|
| 716 |
|
|
on_first_change[2] = 1'b0;
|
| 717 |
|
|
last_wb_dat_o_exp[29] = wb_dat_o_expected_prev[29];
|
| 718 |
|
|
end
|
| 719 |
|
|
if (
|
| 720 |
|
|
( wb_dat_o_expected_prev[30] !== 1'bx ) && ( wb_dat_o_prev[30] !== wb_dat_o_expected_prev[30] )
|
| 721 |
|
|
&& ((wb_dat_o_expected_prev[30] !== last_wb_dat_o_exp[30]) ||
|
| 722 |
|
|
on_first_change[2])
|
| 723 |
|
|
)
|
| 724 |
|
|
begin
|
| 725 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[30] :: @time = %t", $realtime);
|
| 726 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 727 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 728 |
|
|
nummismatches = nummismatches + 1;
|
| 729 |
|
|
on_first_change[2] = 1'b0;
|
| 730 |
|
|
last_wb_dat_o_exp[30] = wb_dat_o_expected_prev[30];
|
| 731 |
|
|
end
|
| 732 |
|
|
if (
|
| 733 |
|
|
( wb_dat_o_expected_prev[31] !== 1'bx ) && ( wb_dat_o_prev[31] !== wb_dat_o_expected_prev[31] )
|
| 734 |
|
|
&& ((wb_dat_o_expected_prev[31] !== last_wb_dat_o_exp[31]) ||
|
| 735 |
|
|
on_first_change[2])
|
| 736 |
|
|
)
|
| 737 |
|
|
begin
|
| 738 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_dat_o[31] :: @time = %t", $realtime);
|
| 739 |
|
|
$display (" Expected value = %b", wb_dat_o_expected_prev);
|
| 740 |
|
|
$display (" Real value = %b", wb_dat_o_prev);
|
| 741 |
|
|
nummismatches = nummismatches + 1;
|
| 742 |
|
|
on_first_change[2] = 1'b0;
|
| 743 |
|
|
last_wb_dat_o_exp[31] = wb_dat_o_expected_prev[31];
|
| 744 |
|
|
end
|
| 745 |
|
|
if (
|
| 746 |
|
|
( wb_err_o_expected_prev !== 1'bx ) && ( wb_err_o_prev !== wb_err_o_expected_prev )
|
| 747 |
|
|
&& ((wb_err_o_expected_prev !== last_wb_err_o_exp) ||
|
| 748 |
|
|
on_first_change[3])
|
| 749 |
|
|
)
|
| 750 |
|
|
begin
|
| 751 |
|
|
$display ("ERROR! Vector Mismatch for output port wb_err_o :: @time = %t", $realtime);
|
| 752 |
|
|
$display (" Expected value = %b", wb_err_o_expected_prev);
|
| 753 |
|
|
$display (" Real value = %b", wb_err_o_prev);
|
| 754 |
|
|
nummismatches = nummismatches + 1;
|
| 755 |
|
|
on_first_change[3] = 1'b0;
|
| 756 |
|
|
last_wb_err_o_exp = wb_err_o_expected_prev;
|
| 757 |
|
|
end
|
| 758 |
|
|
|
| 759 |
|
|
trigger <= ~trigger;
|
| 760 |
|
|
end
|
| 761 |
|
|
initial
|
| 762 |
|
|
|
| 763 |
|
|
begin
|
| 764 |
|
|
$timeformat(-12,3," ps",6);
|
| 765 |
|
|
#2000000;
|
| 766 |
|
|
if (nummismatches > 0)
|
| 767 |
|
|
$display ("%d mismatched vectors : Simulation failed !",nummismatches);
|
| 768 |
|
|
else
|
| 769 |
|
|
$display ("Simulation passed !");
|
| 770 |
|
|
$stop;
|
| 771 |
|
|
end
|
| 772 |
|
|
endmodule
|
| 773 |
|
|
|
| 774 |
|
|
module altera_ram_top_vlg_vec_tst();
|
| 775 |
|
|
// constants
|
| 776 |
|
|
// general purpose registers
|
| 777 |
|
|
reg [31:0] wb_adr_i;
|
| 778 |
|
|
reg wb_clk_i;
|
| 779 |
|
|
reg wb_cyc_i;
|
| 780 |
|
|
reg [31:0] wb_dat_i;
|
| 781 |
|
|
reg wb_rst_i;
|
| 782 |
|
|
reg [3:0] wb_sel_i;
|
| 783 |
|
|
reg wb_stb_i;
|
| 784 |
|
|
reg wb_we_i;
|
| 785 |
|
|
// wires
|
| 786 |
|
|
wire wb_ack_o;
|
| 787 |
|
|
wire [31:0] wb_dat_o;
|
| 788 |
|
|
wire wb_err_o;
|
| 789 |
|
|
|
| 790 |
|
|
wire sampler;
|
| 791 |
|
|
|
| 792 |
|
|
// assign statements (if any)
|
| 793 |
|
|
altera_ram_top i1 (
|
| 794 |
|
|
// port map - connection between master ports and signals/registers
|
| 795 |
|
|
.wb_ack_o(wb_ack_o),
|
| 796 |
|
|
.wb_adr_i(wb_adr_i),
|
| 797 |
|
|
.wb_clk_i(wb_clk_i),
|
| 798 |
|
|
.wb_cyc_i(wb_cyc_i),
|
| 799 |
|
|
.wb_dat_i(wb_dat_i),
|
| 800 |
|
|
.wb_dat_o(wb_dat_o),
|
| 801 |
|
|
.wb_err_o(wb_err_o),
|
| 802 |
|
|
.wb_rst_i(wb_rst_i),
|
| 803 |
|
|
.wb_sel_i(wb_sel_i),
|
| 804 |
|
|
.wb_stb_i(wb_stb_i),
|
| 805 |
|
|
.wb_we_i(wb_we_i)
|
| 806 |
|
|
);
|
| 807 |
|
|
|
| 808 |
|
|
// wb_clk_i
|
| 809 |
|
|
always
|
| 810 |
|
|
begin
|
| 811 |
|
|
wb_clk_i = 1'b0;
|
| 812 |
|
|
wb_clk_i = #10000 1'b1;
|
| 813 |
|
|
#10000;
|
| 814 |
|
|
end
|
| 815 |
|
|
|
| 816 |
|
|
// wb_rst_i
|
| 817 |
|
|
initial
|
| 818 |
|
|
begin
|
| 819 |
|
|
wb_rst_i = 1'b0;
|
| 820 |
|
|
wb_rst_i = #20000 1'b1;
|
| 821 |
|
|
wb_rst_i = #20000 1'b0;
|
| 822 |
|
|
wb_rst_i = #980000 1'b1;
|
| 823 |
|
|
wb_rst_i = #20000 1'b0;
|
| 824 |
|
|
end
|
| 825 |
|
|
// wb_adr_i[ 31 ]
|
| 826 |
|
|
initial
|
| 827 |
|
|
begin
|
| 828 |
|
|
wb_adr_i[31] = 1'b0;
|
| 829 |
|
|
end
|
| 830 |
|
|
// wb_adr_i[ 30 ]
|
| 831 |
|
|
initial
|
| 832 |
|
|
begin
|
| 833 |
|
|
wb_adr_i[30] = 1'b0;
|
| 834 |
|
|
end
|
| 835 |
|
|
// wb_adr_i[ 29 ]
|
| 836 |
|
|
initial
|
| 837 |
|
|
begin
|
| 838 |
|
|
wb_adr_i[29] = 1'b0;
|
| 839 |
|
|
end
|
| 840 |
|
|
// wb_adr_i[ 28 ]
|
| 841 |
|
|
initial
|
| 842 |
|
|
begin
|
| 843 |
|
|
wb_adr_i[28] = 1'b0;
|
| 844 |
|
|
end
|
| 845 |
|
|
// wb_adr_i[ 27 ]
|
| 846 |
|
|
initial
|
| 847 |
|
|
begin
|
| 848 |
|
|
wb_adr_i[27] = 1'b0;
|
| 849 |
|
|
end
|
| 850 |
|
|
// wb_adr_i[ 26 ]
|
| 851 |
|
|
initial
|
| 852 |
|
|
begin
|
| 853 |
|
|
wb_adr_i[26] = 1'b0;
|
| 854 |
|
|
end
|
| 855 |
|
|
// wb_adr_i[ 25 ]
|
| 856 |
|
|
initial
|
| 857 |
|
|
begin
|
| 858 |
|
|
wb_adr_i[25] = 1'b0;
|
| 859 |
|
|
end
|
| 860 |
|
|
// wb_adr_i[ 24 ]
|
| 861 |
|
|
initial
|
| 862 |
|
|
begin
|
| 863 |
|
|
wb_adr_i[24] = 1'b0;
|
| 864 |
|
|
end
|
| 865 |
|
|
// wb_adr_i[ 23 ]
|
| 866 |
|
|
initial
|
| 867 |
|
|
begin
|
| 868 |
|
|
wb_adr_i[23] = 1'b0;
|
| 869 |
|
|
end
|
| 870 |
|
|
// wb_adr_i[ 22 ]
|
| 871 |
|
|
initial
|
| 872 |
|
|
begin
|
| 873 |
|
|
wb_adr_i[22] = 1'b0;
|
| 874 |
|
|
end
|
| 875 |
|
|
// wb_adr_i[ 21 ]
|
| 876 |
|
|
initial
|
| 877 |
|
|
begin
|
| 878 |
|
|
wb_adr_i[21] = 1'b0;
|
| 879 |
|
|
end
|
| 880 |
|
|
// wb_adr_i[ 20 ]
|
| 881 |
|
|
initial
|
| 882 |
|
|
begin
|
| 883 |
|
|
wb_adr_i[20] = 1'b0;
|
| 884 |
|
|
end
|
| 885 |
|
|
// wb_adr_i[ 19 ]
|
| 886 |
|
|
initial
|
| 887 |
|
|
begin
|
| 888 |
|
|
wb_adr_i[19] = 1'b0;
|
| 889 |
|
|
end
|
| 890 |
|
|
// wb_adr_i[ 18 ]
|
| 891 |
|
|
initial
|
| 892 |
|
|
begin
|
| 893 |
|
|
wb_adr_i[18] = 1'b0;
|
| 894 |
|
|
end
|
| 895 |
|
|
// wb_adr_i[ 17 ]
|
| 896 |
|
|
initial
|
| 897 |
|
|
begin
|
| 898 |
|
|
wb_adr_i[17] = 1'b0;
|
| 899 |
|
|
end
|
| 900 |
|
|
// wb_adr_i[ 16 ]
|
| 901 |
|
|
initial
|
| 902 |
|
|
begin
|
| 903 |
|
|
wb_adr_i[16] = 1'b0;
|
| 904 |
|
|
end
|
| 905 |
|
|
// wb_adr_i[ 15 ]
|
| 906 |
|
|
initial
|
| 907 |
|
|
begin
|
| 908 |
|
|
wb_adr_i[15] = 1'b0;
|
| 909 |
|
|
end
|
| 910 |
|
|
// wb_adr_i[ 14 ]
|
| 911 |
|
|
initial
|
| 912 |
|
|
begin
|
| 913 |
|
|
wb_adr_i[14] = 1'b0;
|
| 914 |
|
|
end
|
| 915 |
|
|
// wb_adr_i[ 13 ]
|
| 916 |
|
|
initial
|
| 917 |
|
|
begin
|
| 918 |
|
|
wb_adr_i[13] = 1'b0;
|
| 919 |
|
|
end
|
| 920 |
|
|
// wb_adr_i[ 12 ]
|
| 921 |
|
|
initial
|
| 922 |
|
|
begin
|
| 923 |
|
|
wb_adr_i[12] = 1'b0;
|
| 924 |
|
|
end
|
| 925 |
|
|
// wb_adr_i[ 11 ]
|
| 926 |
|
|
initial
|
| 927 |
|
|
begin
|
| 928 |
|
|
wb_adr_i[11] = 1'b0;
|
| 929 |
|
|
end
|
| 930 |
|
|
// wb_adr_i[ 10 ]
|
| 931 |
|
|
initial
|
| 932 |
|
|
begin
|
| 933 |
|
|
wb_adr_i[10] = 1'b0;
|
| 934 |
|
|
end
|
| 935 |
|
|
// wb_adr_i[ 9 ]
|
| 936 |
|
|
initial
|
| 937 |
|
|
begin
|
| 938 |
|
|
wb_adr_i[9] = 1'b0;
|
| 939 |
|
|
end
|
| 940 |
|
|
// wb_adr_i[ 8 ]
|
| 941 |
|
|
initial
|
| 942 |
|
|
begin
|
| 943 |
|
|
wb_adr_i[8] = 1'b1;
|
| 944 |
|
|
end
|
| 945 |
|
|
// wb_adr_i[ 7 ]
|
| 946 |
|
|
initial
|
| 947 |
|
|
begin
|
| 948 |
|
|
wb_adr_i[7] = 1'b0;
|
| 949 |
|
|
end
|
| 950 |
|
|
// wb_adr_i[ 6 ]
|
| 951 |
|
|
initial
|
| 952 |
|
|
begin
|
| 953 |
|
|
wb_adr_i[6] = 1'b0;
|
| 954 |
|
|
end
|
| 955 |
|
|
// wb_adr_i[ 5 ]
|
| 956 |
|
|
initial
|
| 957 |
|
|
begin
|
| 958 |
|
|
wb_adr_i[5] = 1'b0;
|
| 959 |
|
|
wb_adr_i[5] = #640000 1'b1;
|
| 960 |
|
|
wb_adr_i[5] = #80000 1'b0;
|
| 961 |
|
|
wb_adr_i[5] = #80000 1'b1;
|
| 962 |
|
|
wb_adr_i[5] = #200000 1'b0;
|
| 963 |
|
|
wb_adr_i[5] = #640000 1'b1;
|
| 964 |
|
|
wb_adr_i[5] = #80000 1'b0;
|
| 965 |
|
|
wb_adr_i[5] = #80000 1'b1;
|
| 966 |
|
|
end
|
| 967 |
|
|
// wb_adr_i[ 4 ]
|
| 968 |
|
|
initial
|
| 969 |
|
|
begin
|
| 970 |
|
|
wb_adr_i[4] = 1'b0;
|
| 971 |
|
|
wb_adr_i[4] = #320000 1'b1;
|
| 972 |
|
|
wb_adr_i[4] = #320000 1'b0;
|
| 973 |
|
|
wb_adr_i[4] = #80000 1'b1;
|
| 974 |
|
|
wb_adr_i[4] = #80000 1'b0;
|
| 975 |
|
|
wb_adr_i[4] = #160000 1'b1;
|
| 976 |
|
|
wb_adr_i[4] = #40000 1'b0;
|
| 977 |
|
|
wb_adr_i[4] = #320000 1'b1;
|
| 978 |
|
|
wb_adr_i[4] = #160000 1'b0;
|
| 979 |
|
|
wb_adr_i[4] = #80000 1'b1;
|
| 980 |
|
|
wb_adr_i[4] = #80000 1'b0;
|
| 981 |
|
|
wb_adr_i[4] = #80000 1'b1;
|
| 982 |
|
|
wb_adr_i[4] = #80000 1'b0;
|
| 983 |
|
|
wb_adr_i[4] = #160000 1'b1;
|
| 984 |
|
|
end
|
| 985 |
|
|
// wb_adr_i[ 3 ]
|
| 986 |
|
|
initial
|
| 987 |
|
|
begin
|
| 988 |
|
|
repeat(2)
|
| 989 |
|
|
begin
|
| 990 |
|
|
wb_adr_i[3] = 1'b0;
|
| 991 |
|
|
wb_adr_i[3] = #160000 1'b1;
|
| 992 |
|
|
# 160000;
|
| 993 |
|
|
end
|
| 994 |
|
|
wb_adr_i[3] = 1'b0;
|
| 995 |
|
|
wb_adr_i[3] = #80000 1'b1;
|
| 996 |
|
|
wb_adr_i[3] = #240000 1'b0;
|
| 997 |
|
|
wb_adr_i[3] = #200000 1'b1;
|
| 998 |
|
|
wb_adr_i[3] = #160000 1'b0;
|
| 999 |
|
|
wb_adr_i[3] = #240000 1'b1;
|
| 1000 |
|
|
wb_adr_i[3] = #80000 1'b0;
|
| 1001 |
|
|
wb_adr_i[3] = #160000 1'b1;
|
| 1002 |
|
|
wb_adr_i[3] = #160000 1'b0;
|
| 1003 |
|
|
end
|
| 1004 |
|
|
// wb_adr_i[ 2 ]
|
| 1005 |
|
|
initial
|
| 1006 |
|
|
begin
|
| 1007 |
|
|
repeat(4)
|
| 1008 |
|
|
begin
|
| 1009 |
|
|
wb_adr_i[2] = 1'b0;
|
| 1010 |
|
|
wb_adr_i[2] = #80000 1'b1;
|
| 1011 |
|
|
# 80000;
|
| 1012 |
|
|
end
|
| 1013 |
|
|
wb_adr_i[2] = 1'b0;
|
| 1014 |
|
|
wb_adr_i[2] = #240000 1'b1;
|
| 1015 |
|
|
wb_adr_i[2] = #80000 1'b0;
|
| 1016 |
|
|
wb_adr_i[2] = #120000 1'b1;
|
| 1017 |
|
|
wb_adr_i[2] = #80000 1'b0;
|
| 1018 |
|
|
wb_adr_i[2] = #80000 1'b1;
|
| 1019 |
|
|
wb_adr_i[2] = #80000 1'b0;
|
| 1020 |
|
|
wb_adr_i[2] = #80000 1'b1;
|
| 1021 |
|
|
wb_adr_i[2] = #240000 1'b0;
|
| 1022 |
|
|
wb_adr_i[2] = #80000 1'b1;
|
| 1023 |
|
|
wb_adr_i[2] = #80000 1'b0;
|
| 1024 |
|
|
wb_adr_i[2] = #80000 1'b1;
|
| 1025 |
|
|
wb_adr_i[2] = #80000 1'b0;
|
| 1026 |
|
|
end
|
| 1027 |
|
|
// wb_adr_i[ 1 ]
|
| 1028 |
|
|
initial
|
| 1029 |
|
|
begin
|
| 1030 |
|
|
wb_adr_i[1] = 1'b0;
|
| 1031 |
|
|
end
|
| 1032 |
|
|
// wb_adr_i[ 0 ]
|
| 1033 |
|
|
initial
|
| 1034 |
|
|
begin
|
| 1035 |
|
|
wb_adr_i[0] = 1'b0;
|
| 1036 |
|
|
end
|
| 1037 |
|
|
// wb_sel_i[ 3 ]
|
| 1038 |
|
|
initial
|
| 1039 |
|
|
begin
|
| 1040 |
|
|
wb_sel_i[3] = 1'b1;
|
| 1041 |
|
|
wb_sel_i[3] = #1080000 1'b0;
|
| 1042 |
|
|
wb_sel_i[3] = #50000 1'b1;
|
| 1043 |
|
|
end
|
| 1044 |
|
|
// wb_sel_i[ 2 ]
|
| 1045 |
|
|
initial
|
| 1046 |
|
|
begin
|
| 1047 |
|
|
wb_sel_i[2] = 1'b1;
|
| 1048 |
|
|
wb_sel_i[2] = #1080000 1'b0;
|
| 1049 |
|
|
wb_sel_i[2] = #50000 1'b1;
|
| 1050 |
|
|
end
|
| 1051 |
|
|
// wb_sel_i[ 1 ]
|
| 1052 |
|
|
initial
|
| 1053 |
|
|
begin
|
| 1054 |
|
|
wb_sel_i[1] = 1'b1;
|
| 1055 |
|
|
end
|
| 1056 |
|
|
// wb_sel_i[ 0 ]
|
| 1057 |
|
|
initial
|
| 1058 |
|
|
begin
|
| 1059 |
|
|
wb_sel_i[0] = 1'b1;
|
| 1060 |
|
|
wb_sel_i[0] = #1080000 1'b0;
|
| 1061 |
|
|
wb_sel_i[0] = #50000 1'b1;
|
| 1062 |
|
|
end
|
| 1063 |
|
|
|
| 1064 |
|
|
// wb_stb_i
|
| 1065 |
|
|
initial
|
| 1066 |
|
|
begin
|
| 1067 |
|
|
wb_stb_i = 1'b0;
|
| 1068 |
|
|
wb_stb_i = #80000 1'b1;
|
| 1069 |
|
|
wb_stb_i = #50000 1'b0;
|
| 1070 |
|
|
wb_stb_i = #120000 1'b1;
|
| 1071 |
|
|
wb_stb_i = #40000 1'b0;
|
| 1072 |
|
|
wb_stb_i = #200000 1'b1;
|
| 1073 |
|
|
wb_stb_i = #40000 1'b0;
|
| 1074 |
|
|
wb_stb_i = #200000 1'b1;
|
| 1075 |
|
|
wb_stb_i = #40000 1'b0;
|
| 1076 |
|
|
wb_stb_i = #310000 1'b1;
|
| 1077 |
|
|
wb_stb_i = #50000 1'b0;
|
| 1078 |
|
|
wb_stb_i = #360000 1'b1;
|
| 1079 |
|
|
wb_stb_i = #40000 1'b0;
|
| 1080 |
|
|
wb_stb_i = #200000 1'b1;
|
| 1081 |
|
|
wb_stb_i = #40000 1'b0;
|
| 1082 |
|
|
end
|
| 1083 |
|
|
|
| 1084 |
|
|
// wb_cyc_i
|
| 1085 |
|
|
initial
|
| 1086 |
|
|
begin
|
| 1087 |
|
|
wb_cyc_i = 1'b0;
|
| 1088 |
|
|
wb_cyc_i = #80000 1'b1;
|
| 1089 |
|
|
wb_cyc_i = #50000 1'b0;
|
| 1090 |
|
|
wb_cyc_i = #120000 1'b1;
|
| 1091 |
|
|
wb_cyc_i = #40000 1'b0;
|
| 1092 |
|
|
wb_cyc_i = #200000 1'b1;
|
| 1093 |
|
|
wb_cyc_i = #40000 1'b0;
|
| 1094 |
|
|
wb_cyc_i = #200000 1'b1;
|
| 1095 |
|
|
wb_cyc_i = #40000 1'b0;
|
| 1096 |
|
|
wb_cyc_i = #310000 1'b1;
|
| 1097 |
|
|
wb_cyc_i = #50000 1'b0;
|
| 1098 |
|
|
wb_cyc_i = #360000 1'b1;
|
| 1099 |
|
|
wb_cyc_i = #40000 1'b0;
|
| 1100 |
|
|
wb_cyc_i = #200000 1'b1;
|
| 1101 |
|
|
wb_cyc_i = #40000 1'b0;
|
| 1102 |
|
|
end
|
| 1103 |
|
|
|
| 1104 |
|
|
// wb_we_i
|
| 1105 |
|
|
initial
|
| 1106 |
|
|
begin
|
| 1107 |
|
|
wb_we_i = 1'b0;
|
| 1108 |
|
|
wb_we_i = #490000 1'b1;
|
| 1109 |
|
|
wb_we_i = #40000 1'b0;
|
| 1110 |
|
|
wb_we_i = #550000 1'b1;
|
| 1111 |
|
|
wb_we_i = #50000 1'b0;
|
| 1112 |
|
|
end
|
| 1113 |
|
|
// wb_dat_i[ 31 ]
|
| 1114 |
|
|
initial
|
| 1115 |
|
|
begin
|
| 1116 |
|
|
wb_dat_i[31] = 1'b0;
|
| 1117 |
|
|
wb_dat_i[31] = #480000 1'b1;
|
| 1118 |
|
|
wb_dat_i[31] = #50000 1'b0;
|
| 1119 |
|
|
wb_dat_i[31] = #550000 1'b1;
|
| 1120 |
|
|
wb_dat_i[31] = #50000 1'b0;
|
| 1121 |
|
|
wb_dat_i[31] = #350000 1'b1;
|
| 1122 |
|
|
wb_dat_i[31] = #50000 1'b0;
|
| 1123 |
|
|
end
|
| 1124 |
|
|
// wb_dat_i[ 30 ]
|
| 1125 |
|
|
initial
|
| 1126 |
|
|
begin
|
| 1127 |
|
|
wb_dat_i[30] = 1'b0;
|
| 1128 |
|
|
wb_dat_i[30] = #1080000 1'b1;
|
| 1129 |
|
|
wb_dat_i[30] = #50000 1'b0;
|
| 1130 |
|
|
end
|
| 1131 |
|
|
// wb_dat_i[ 29 ]
|
| 1132 |
|
|
initial
|
| 1133 |
|
|
begin
|
| 1134 |
|
|
wb_dat_i[29] = 1'b0;
|
| 1135 |
|
|
wb_dat_i[29] = #480000 1'b1;
|
| 1136 |
|
|
wb_dat_i[29] = #50000 1'b0;
|
| 1137 |
|
|
wb_dat_i[29] = #550000 1'b1;
|
| 1138 |
|
|
wb_dat_i[29] = #50000 1'b0;
|
| 1139 |
|
|
wb_dat_i[29] = #350000 1'b1;
|
| 1140 |
|
|
wb_dat_i[29] = #50000 1'b0;
|
| 1141 |
|
|
end
|
| 1142 |
|
|
// wb_dat_i[ 28 ]
|
| 1143 |
|
|
initial
|
| 1144 |
|
|
begin
|
| 1145 |
|
|
wb_dat_i[28] = 1'b0;
|
| 1146 |
|
|
wb_dat_i[28] = #1080000 1'b1;
|
| 1147 |
|
|
wb_dat_i[28] = #50000 1'b0;
|
| 1148 |
|
|
end
|
| 1149 |
|
|
// wb_dat_i[ 27 ]
|
| 1150 |
|
|
initial
|
| 1151 |
|
|
begin
|
| 1152 |
|
|
wb_dat_i[27] = 1'b0;
|
| 1153 |
|
|
wb_dat_i[27] = #480000 1'b1;
|
| 1154 |
|
|
wb_dat_i[27] = #50000 1'b0;
|
| 1155 |
|
|
wb_dat_i[27] = #550000 1'b1;
|
| 1156 |
|
|
wb_dat_i[27] = #50000 1'b0;
|
| 1157 |
|
|
wb_dat_i[27] = #350000 1'b1;
|
| 1158 |
|
|
wb_dat_i[27] = #50000 1'b0;
|
| 1159 |
|
|
end
|
| 1160 |
|
|
// wb_dat_i[ 26 ]
|
| 1161 |
|
|
initial
|
| 1162 |
|
|
begin
|
| 1163 |
|
|
wb_dat_i[26] = 1'b0;
|
| 1164 |
|
|
wb_dat_i[26] = #1080000 1'b1;
|
| 1165 |
|
|
wb_dat_i[26] = #50000 1'b0;
|
| 1166 |
|
|
end
|
| 1167 |
|
|
// wb_dat_i[ 25 ]
|
| 1168 |
|
|
initial
|
| 1169 |
|
|
begin
|
| 1170 |
|
|
wb_dat_i[25] = 1'b0;
|
| 1171 |
|
|
wb_dat_i[25] = #480000 1'b1;
|
| 1172 |
|
|
wb_dat_i[25] = #50000 1'b0;
|
| 1173 |
|
|
wb_dat_i[25] = #550000 1'b1;
|
| 1174 |
|
|
wb_dat_i[25] = #50000 1'b0;
|
| 1175 |
|
|
wb_dat_i[25] = #350000 1'b1;
|
| 1176 |
|
|
wb_dat_i[25] = #50000 1'b0;
|
| 1177 |
|
|
end
|
| 1178 |
|
|
// wb_dat_i[ 24 ]
|
| 1179 |
|
|
initial
|
| 1180 |
|
|
begin
|
| 1181 |
|
|
wb_dat_i[24] = 1'b0;
|
| 1182 |
|
|
wb_dat_i[24] = #480000 1'b1;
|
| 1183 |
|
|
wb_dat_i[24] = #50000 1'b0;
|
| 1184 |
|
|
wb_dat_i[24] = #950000 1'b1;
|
| 1185 |
|
|
wb_dat_i[24] = #50000 1'b0;
|
| 1186 |
|
|
end
|
| 1187 |
|
|
// wb_dat_i[ 23 ]
|
| 1188 |
|
|
initial
|
| 1189 |
|
|
begin
|
| 1190 |
|
|
wb_dat_i[23] = 1'b0;
|
| 1191 |
|
|
wb_dat_i[23] = #480000 1'b1;
|
| 1192 |
|
|
wb_dat_i[23] = #50000 1'b0;
|
| 1193 |
|
|
wb_dat_i[23] = #550000 1'b1;
|
| 1194 |
|
|
wb_dat_i[23] = #50000 1'b0;
|
| 1195 |
|
|
wb_dat_i[23] = #350000 1'b1;
|
| 1196 |
|
|
wb_dat_i[23] = #50000 1'b0;
|
| 1197 |
|
|
end
|
| 1198 |
|
|
// wb_dat_i[ 22 ]
|
| 1199 |
|
|
initial
|
| 1200 |
|
|
begin
|
| 1201 |
|
|
wb_dat_i[22] = 1'b0;
|
| 1202 |
|
|
wb_dat_i[22] = #480000 1'b1;
|
| 1203 |
|
|
wb_dat_i[22] = #50000 1'b0;
|
| 1204 |
|
|
wb_dat_i[22] = #550000 1'b1;
|
| 1205 |
|
|
wb_dat_i[22] = #50000 1'b0;
|
| 1206 |
|
|
wb_dat_i[22] = #350000 1'b1;
|
| 1207 |
|
|
wb_dat_i[22] = #50000 1'b0;
|
| 1208 |
|
|
end
|
| 1209 |
|
|
// wb_dat_i[ 21 ]
|
| 1210 |
|
|
initial
|
| 1211 |
|
|
begin
|
| 1212 |
|
|
wb_dat_i[21] = 1'b0;
|
| 1213 |
|
|
end
|
| 1214 |
|
|
// wb_dat_i[ 20 ]
|
| 1215 |
|
|
initial
|
| 1216 |
|
|
begin
|
| 1217 |
|
|
wb_dat_i[20] = 1'b0;
|
| 1218 |
|
|
wb_dat_i[20] = #1080000 1'b1;
|
| 1219 |
|
|
wb_dat_i[20] = #50000 1'b0;
|
| 1220 |
|
|
end
|
| 1221 |
|
|
// wb_dat_i[ 19 ]
|
| 1222 |
|
|
initial
|
| 1223 |
|
|
begin
|
| 1224 |
|
|
wb_dat_i[19] = 1'b0;
|
| 1225 |
|
|
wb_dat_i[19] = #480000 1'b1;
|
| 1226 |
|
|
wb_dat_i[19] = #50000 1'b0;
|
| 1227 |
|
|
wb_dat_i[19] = #550000 1'b1;
|
| 1228 |
|
|
wb_dat_i[19] = #50000 1'b0;
|
| 1229 |
|
|
wb_dat_i[19] = #350000 1'b1;
|
| 1230 |
|
|
wb_dat_i[19] = #50000 1'b0;
|
| 1231 |
|
|
end
|
| 1232 |
|
|
// wb_dat_i[ 18 ]
|
| 1233 |
|
|
initial
|
| 1234 |
|
|
begin
|
| 1235 |
|
|
wb_dat_i[18] = 1'b0;
|
| 1236 |
|
|
wb_dat_i[18] = #480000 1'b1;
|
| 1237 |
|
|
wb_dat_i[18] = #50000 1'b0;
|
| 1238 |
|
|
wb_dat_i[18] = #550000 1'b1;
|
| 1239 |
|
|
wb_dat_i[18] = #50000 1'b0;
|
| 1240 |
|
|
wb_dat_i[18] = #350000 1'b1;
|
| 1241 |
|
|
wb_dat_i[18] = #50000 1'b0;
|
| 1242 |
|
|
end
|
| 1243 |
|
|
// wb_dat_i[ 17 ]
|
| 1244 |
|
|
initial
|
| 1245 |
|
|
begin
|
| 1246 |
|
|
wb_dat_i[17] = 1'b0;
|
| 1247 |
|
|
end
|
| 1248 |
|
|
// wb_dat_i[ 16 ]
|
| 1249 |
|
|
initial
|
| 1250 |
|
|
begin
|
| 1251 |
|
|
wb_dat_i[16] = 1'b0;
|
| 1252 |
|
|
wb_dat_i[16] = #480000 1'b1;
|
| 1253 |
|
|
wb_dat_i[16] = #50000 1'b0;
|
| 1254 |
|
|
wb_dat_i[16] = #950000 1'b1;
|
| 1255 |
|
|
wb_dat_i[16] = #50000 1'b0;
|
| 1256 |
|
|
end
|
| 1257 |
|
|
// wb_dat_i[ 15 ]
|
| 1258 |
|
|
initial
|
| 1259 |
|
|
begin
|
| 1260 |
|
|
wb_dat_i[15] = 1'b0;
|
| 1261 |
|
|
wb_dat_i[15] = #480000 1'b1;
|
| 1262 |
|
|
wb_dat_i[15] = #50000 1'b0;
|
| 1263 |
|
|
wb_dat_i[15] = #550000 1'b1;
|
| 1264 |
|
|
wb_dat_i[15] = #50000 1'b0;
|
| 1265 |
|
|
wb_dat_i[15] = #350000 1'b1;
|
| 1266 |
|
|
wb_dat_i[15] = #50000 1'b0;
|
| 1267 |
|
|
end
|
| 1268 |
|
|
// wb_dat_i[ 14 ]
|
| 1269 |
|
|
initial
|
| 1270 |
|
|
begin
|
| 1271 |
|
|
wb_dat_i[14] = 1'b0;
|
| 1272 |
|
|
wb_dat_i[14] = #480000 1'b1;
|
| 1273 |
|
|
wb_dat_i[14] = #50000 1'b0;
|
| 1274 |
|
|
wb_dat_i[14] = #950000 1'b1;
|
| 1275 |
|
|
wb_dat_i[14] = #50000 1'b0;
|
| 1276 |
|
|
end
|
| 1277 |
|
|
// wb_dat_i[ 13 ]
|
| 1278 |
|
|
initial
|
| 1279 |
|
|
begin
|
| 1280 |
|
|
wb_dat_i[13] = 1'b0;
|
| 1281 |
|
|
wb_dat_i[13] = #480000 1'b1;
|
| 1282 |
|
|
wb_dat_i[13] = #50000 1'b0;
|
| 1283 |
|
|
wb_dat_i[13] = #550000 1'b1;
|
| 1284 |
|
|
wb_dat_i[13] = #50000 1'b0;
|
| 1285 |
|
|
wb_dat_i[13] = #350000 1'b1;
|
| 1286 |
|
|
wb_dat_i[13] = #50000 1'b0;
|
| 1287 |
|
|
end
|
| 1288 |
|
|
// wb_dat_i[ 12 ]
|
| 1289 |
|
|
initial
|
| 1290 |
|
|
begin
|
| 1291 |
|
|
wb_dat_i[12] = 1'b0;
|
| 1292 |
|
|
wb_dat_i[12] = #1080000 1'b1;
|
| 1293 |
|
|
wb_dat_i[12] = #50000 1'b0;
|
| 1294 |
|
|
end
|
| 1295 |
|
|
// wb_dat_i[ 11 ]
|
| 1296 |
|
|
initial
|
| 1297 |
|
|
begin
|
| 1298 |
|
|
wb_dat_i[11] = 1'b0;
|
| 1299 |
|
|
wb_dat_i[11] = #480000 1'b1;
|
| 1300 |
|
|
wb_dat_i[11] = #50000 1'b0;
|
| 1301 |
|
|
wb_dat_i[11] = #550000 1'b1;
|
| 1302 |
|
|
wb_dat_i[11] = #50000 1'b0;
|
| 1303 |
|
|
wb_dat_i[11] = #350000 1'b1;
|
| 1304 |
|
|
wb_dat_i[11] = #50000 1'b0;
|
| 1305 |
|
|
end
|
| 1306 |
|
|
// wb_dat_i[ 10 ]
|
| 1307 |
|
|
initial
|
| 1308 |
|
|
begin
|
| 1309 |
|
|
wb_dat_i[10] = 1'b0;
|
| 1310 |
|
|
wb_dat_i[10] = #480000 1'b1;
|
| 1311 |
|
|
wb_dat_i[10] = #50000 1'b0;
|
| 1312 |
|
|
wb_dat_i[10] = #950000 1'b1;
|
| 1313 |
|
|
wb_dat_i[10] = #50000 1'b0;
|
| 1314 |
|
|
end
|
| 1315 |
|
|
// wb_dat_i[ 9 ]
|
| 1316 |
|
|
initial
|
| 1317 |
|
|
begin
|
| 1318 |
|
|
wb_dat_i[9] = 1'b0;
|
| 1319 |
|
|
wb_dat_i[9] = #480000 1'b1;
|
| 1320 |
|
|
wb_dat_i[9] = #50000 1'b0;
|
| 1321 |
|
|
wb_dat_i[9] = #550000 1'b1;
|
| 1322 |
|
|
wb_dat_i[9] = #50000 1'b0;
|
| 1323 |
|
|
wb_dat_i[9] = #350000 1'b1;
|
| 1324 |
|
|
wb_dat_i[9] = #50000 1'b0;
|
| 1325 |
|
|
end
|
| 1326 |
|
|
// wb_dat_i[ 8 ]
|
| 1327 |
|
|
initial
|
| 1328 |
|
|
begin
|
| 1329 |
|
|
wb_dat_i[8] = 1'b0;
|
| 1330 |
|
|
wb_dat_i[8] = #480000 1'b1;
|
| 1331 |
|
|
wb_dat_i[8] = #50000 1'b0;
|
| 1332 |
|
|
wb_dat_i[8] = #950000 1'b1;
|
| 1333 |
|
|
wb_dat_i[8] = #50000 1'b0;
|
| 1334 |
|
|
end
|
| 1335 |
|
|
// wb_dat_i[ 7 ]
|
| 1336 |
|
|
initial
|
| 1337 |
|
|
begin
|
| 1338 |
|
|
wb_dat_i[7] = 1'b0;
|
| 1339 |
|
|
wb_dat_i[7] = #480000 1'b1;
|
| 1340 |
|
|
wb_dat_i[7] = #50000 1'b0;
|
| 1341 |
|
|
wb_dat_i[7] = #550000 1'b1;
|
| 1342 |
|
|
wb_dat_i[7] = #50000 1'b0;
|
| 1343 |
|
|
wb_dat_i[7] = #350000 1'b1;
|
| 1344 |
|
|
wb_dat_i[7] = #50000 1'b0;
|
| 1345 |
|
|
end
|
| 1346 |
|
|
// wb_dat_i[ 6 ]
|
| 1347 |
|
|
initial
|
| 1348 |
|
|
begin
|
| 1349 |
|
|
wb_dat_i[6] = 1'b0;
|
| 1350 |
|
|
end
|
| 1351 |
|
|
// wb_dat_i[ 5 ]
|
| 1352 |
|
|
initial
|
| 1353 |
|
|
begin
|
| 1354 |
|
|
wb_dat_i[5] = 1'b0;
|
| 1355 |
|
|
end
|
| 1356 |
|
|
// wb_dat_i[ 4 ]
|
| 1357 |
|
|
initial
|
| 1358 |
|
|
begin
|
| 1359 |
|
|
wb_dat_i[4] = 1'b0;
|
| 1360 |
|
|
wb_dat_i[4] = #480000 1'b1;
|
| 1361 |
|
|
wb_dat_i[4] = #50000 1'b0;
|
| 1362 |
|
|
wb_dat_i[4] = #550000 1'b1;
|
| 1363 |
|
|
wb_dat_i[4] = #50000 1'b0;
|
| 1364 |
|
|
wb_dat_i[4] = #350000 1'b1;
|
| 1365 |
|
|
wb_dat_i[4] = #50000 1'b0;
|
| 1366 |
|
|
end
|
| 1367 |
|
|
// wb_dat_i[ 3 ]
|
| 1368 |
|
|
initial
|
| 1369 |
|
|
begin
|
| 1370 |
|
|
wb_dat_i[3] = 1'b0;
|
| 1371 |
|
|
wb_dat_i[3] = #480000 1'b1;
|
| 1372 |
|
|
wb_dat_i[3] = #50000 1'b0;
|
| 1373 |
|
|
wb_dat_i[3] = #550000 1'b1;
|
| 1374 |
|
|
wb_dat_i[3] = #50000 1'b0;
|
| 1375 |
|
|
wb_dat_i[3] = #350000 1'b1;
|
| 1376 |
|
|
wb_dat_i[3] = #50000 1'b0;
|
| 1377 |
|
|
end
|
| 1378 |
|
|
// wb_dat_i[ 2 ]
|
| 1379 |
|
|
initial
|
| 1380 |
|
|
begin
|
| 1381 |
|
|
wb_dat_i[2] = 1'b0;
|
| 1382 |
|
|
end
|
| 1383 |
|
|
// wb_dat_i[ 1 ]
|
| 1384 |
|
|
initial
|
| 1385 |
|
|
begin
|
| 1386 |
|
|
wb_dat_i[1] = 1'b0;
|
| 1387 |
|
|
end
|
| 1388 |
|
|
// wb_dat_i[ 0 ]
|
| 1389 |
|
|
initial
|
| 1390 |
|
|
begin
|
| 1391 |
|
|
wb_dat_i[0] = 1'b0;
|
| 1392 |
|
|
end
|
| 1393 |
|
|
|
| 1394 |
|
|
altera_ram_top_vlg_sample_tst tb_sample (
|
| 1395 |
|
|
.wb_adr_i(wb_adr_i),
|
| 1396 |
|
|
.wb_clk_i(wb_clk_i),
|
| 1397 |
|
|
.wb_cyc_i(wb_cyc_i),
|
| 1398 |
|
|
.wb_dat_i(wb_dat_i),
|
| 1399 |
|
|
.wb_rst_i(wb_rst_i),
|
| 1400 |
|
|
.wb_sel_i(wb_sel_i),
|
| 1401 |
|
|
.wb_stb_i(wb_stb_i),
|
| 1402 |
|
|
.wb_we_i(wb_we_i),
|
| 1403 |
|
|
.sampler_tx(sampler)
|
| 1404 |
|
|
);
|
| 1405 |
|
|
|
| 1406 |
|
|
altera_ram_top_vlg_check_tst tb_out(
|
| 1407 |
|
|
.wb_ack_o(wb_ack_o),
|
| 1408 |
|
|
.wb_dat_o(wb_dat_o),
|
| 1409 |
|
|
.wb_err_o(wb_err_o),
|
| 1410 |
|
|
.sampler_rx(sampler)
|
| 1411 |
|
|
);
|
| 1412 |
|
|
endmodule
|
| 1413 |
|
|
|
