Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

// Copyright (C) 1991-2009 Altera Corporation

// Your use of Altera Corporation's design tools, logic functions 

// and other software and tools, and its AMPP partner logic 

// functions, and any output files from any of the foregoing 

// (including device programming or simulation files), and any 

// associated documentation or information are expressly subject 

// to the terms and conditions of the Altera Program License 

// Subscription Agreement, Altera MegaCore Function License 

// Agreement, or other applicable license agreement, including, 

// without limitation, that your use is for the sole purpose of 

// programming logic devices manufactured by Altera and sold by 

// Altera or its authorized distributors.  Please refer to the 

// applicable agreement for further details.

// *****************************************************************************

// This file contains a Verilog test bench with test vectors .The test vectors  

// are exported from a vector file in the Quartus Waveform Editor and apply to  

// the top level entity of the current Quartus project .The user can use this   

// testbench to simulate his design using a third-party simulation tool .       

// *****************************************************************************

// Generated on "10/07/2009 23:14:09"

// Verilog Self-Checking Test Bench (with test vectors) for design :    or1k_soc_top

// 

// Simulation tool : 3rd Party

// 

`timescale 1 ps/ 1 ps

module or1k_soc_top_vlg_vec_tst();

// constants                                           

// general purpose registers

reg eth_col_pad_i;

reg eth_crs_pad_i;

//reg eth_fds_mdint_pad_i;

reg treg_eth_mdio_pad_io;

reg eth_rx_clk_pad_i;

reg eth_rx_dv_pad_i;

reg eth_rx_er_pad_i;

reg [3:0] eth_rxd_pad_i;

reg eth_tx_clk_pad_i;

reg [31:0] treg_gpio_a_pad_io;

reg rst_n_pad_i;

reg uart_srx_pad_i;

reg wb_clk_pad_i;

// wires                                               

//wire clk_cpu_o;

wire eth_mdc_pad_o;

wire eth_mdio_pad_io;

//wire eth_trste_pad_o;

wire eth_tx_en_pad_o;

wire eth_tx_er_pad_o;

wire [3:0] eth_txd_pad_o;

wire [31:0] gpio_a_pad_io;

wire uart_stx_pad_o;

wire wb_rst_pad_o;

wire sampler;

//ddr sdram

wire             ddr_global_reset_n;

wire    [ 15: 0] ddr_mem_dq;

wire    [  1: 0] ddr_mem_dqs;

wire    [ 12: 0] ddr_mem_addr;

wire    [  1: 0] ddr_mem_ba;

wire             ddr_mem_cas_n;

wire             ddr_mem_cke;

wire             ddr_mem_clk;

wire             ddr_mem_clk_n;

wire             ddr_mem_cs_n;

wire    [  1: 0] ddr_mem_dm;

wire             ddr_mem_ras_n;

wire             ddr_mem_we_n;

// assign statements (if any)                          

assign eth_mdio_pad_io = treg_eth_mdio_pad_io;

assign gpio_a_pad_io = treg_gpio_a_pad_io;

or1k_soc_top i1 (

// port map - connection between master ports and signals/registers   

//      .clk_cpu_o(clk_cpu_o),

        .eth_col_pad_i(eth_col_pad_i),

        .eth_crs_pad_i(eth_crs_pad_i),

//      .eth_fds_mdint_pad_i(eth_fds_mdint_pad_i),

        .eth_mdc_pad_o(eth_mdc_pad_o),

        .eth_mdio_pad_io(eth_mdio_pad_io),

        .eth_rx_clk_pad_i(eth_rx_clk_pad_i),

        .eth_rx_dv_pad_i(eth_rx_dv_pad_i),

        .eth_rx_er_pad_i(eth_rx_er_pad_i),

        .eth_rxd_pad_i(eth_rxd_pad_i),

//      .eth_trste_pad_o(eth_trste_pad_o),

        .eth_tx_clk_pad_i(eth_tx_clk_pad_i),

        .eth_tx_en_pad_o(eth_tx_en_pad_o),

        .eth_tx_er_pad_o(eth_tx_er_pad_o),

        .eth_txd_pad_o(eth_txd_pad_o),

        .gpio_a_pad_io(gpio_a_pad_io),

        .rst_n_pad_i(rst_n_pad_i),

        .uart_srx_pad_i(uart_srx_pad_i),

        .uart_stx_pad_o(uart_stx_pad_o),

        .wb_clk_pad_i(wb_clk_pad_i),

//      .wb_rst_pad_o(wb_rst_pad_o),

        //ddr sdram

        .ddr_pll_clk_pad_i      (wb_clk_pad_i),

        .ddr_mem_cs_n_o         (ddr_mem_cs_n),

        .ddr_mem_cke_o          (ddr_mem_cke),

        .ddr_mem_addr_o         (ddr_mem_addr),

        .ddr_mem_ba_o           (ddr_mem_ba),

        .ddr_mem_ras_n_o        (ddr_mem_ras_n),

        .ddr_mem_cas_n_o        (ddr_mem_cas_n),

        .ddr_mem_we_n_o         (ddr_mem_we_n),

        .ddr_mem_dm_o           (ddr_mem_dm),

        .ddr_mem_clk_io         (ddr_mem_clk),

        .ddr_mem_clk_n_io       (ddr_mem_clk_n),

        .ddr_mem_dq_io          (ddr_mem_dq),

        .ddr_mem_dqs_io         (ddr_mem_dqs)

);

// wb_clk_pad_i

always

begin

        wb_clk_pad_i = 1'b0;

        wb_clk_pad_i = #10000 1'b1;

        #10000;

end

// rst_n_pad_i

initial

begin

        rst_n_pad_i = 1'b0;

        rst_n_pad_i = #200000 1'b1;

end

// gpio_a_pad_io

initial

begin

        treg_gpio_a_pad_io = {32{1'bZ}};

end

// uart_srx_pad_i

initial

begin

        uart_srx_pad_i = 1'b1;

end

altera_ddr_mem_model ddr_inst(

                              // inputs:

                               .mem_addr        (ddr_mem_addr),

                               .mem_ba          (ddr_mem_ba),

                               .mem_cas_n       (ddr_mem_cas_n),

                               .mem_cke         (ddr_mem_cke),

                               .mem_clk         (ddr_mem_clk),

                               .mem_clk_n       (ddr_mem_clk_n),

                               .mem_cs_n        (ddr_mem_cs_n),

                               .mem_dm          (ddr_mem_dm),

                               .mem_ras_n       (ddr_mem_ras_n),

                               .mem_we_n        (ddr_mem_we_n),

                              // outputs:

                               .global_reset_n  (ddr_global_reset_n),

                               .mem_dq          (ddr_mem_dq),

                               .mem_dqs         (ddr_mem_dqs)

                            )

;

endmodule