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URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [prj/] [altera/] [setup_prj.tcl] - Blame information for rev 17

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Line No. Rev Author Line
1 12 xianfeng 
# Copyright (C) 1991-2009 Altera Corporation
2 
# Your use of Altera Corporation's design tools, logic functions
3 
# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
9 
# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors.  Please refer to the
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# applicable agreement for further details.
14 
 
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# Quartus II: Generate Tcl File for Project
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# File: setup_prj.tcl
17 17 xianfeng 
# Generated on: Sun Nov 29 16:35:34 2009
18 12 xianfeng 
 
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# Load Quartus II Tcl Project package
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package require ::quartus::project
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22 
set need_to_close_project 0
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set make_assignments 1
24 
 
25 
# Check that the right project is open
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if {[is_project_open]} {
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        if {[string compare $quartus(project) "or1k_soc_top"]} {
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                puts "Project or1k_soc_top is not open"
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                set make_assignments 0
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        }
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} else {
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        # Only open if not already open
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        if {[project_exists or1k_soc_top]} {
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                project_open -revision or1k_soc_top or1k_soc_top
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        } else {
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                project_new -revision or1k_soc_top or1k_soc_top
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        }
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        set need_to_close_project 1
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}
40 
 
41 
# Make assignments
42 
if {$make_assignments} {
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        set_global_assignment -name FAMILY "Cyclone III"
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        set_global_assignment -name DEVICE EP3C25F324C6
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        set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
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        set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:04:58  OCTOBER 02, 2009"
47 
        set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
48 
        set_global_assignment -name SIMULATION_MODE FUNCTIONAL
49 
        set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF
50 
        set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
51 
        set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
52 
        set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_simulation
53 
        set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
54 
        set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
55 
        set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
56 
        set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
57 
        set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
58 
        set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
59 
        set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
60 
        set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
61 
        set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
62 
        set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
63 
        set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
64 
        set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
65 
        set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
66 
        set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH or1k_soc_top -section_id eda_simulation
67 
        set_global_assignment -name EDA_TEST_BENCH_NAME or1k_soc_top -section_id eda_simulation
68 
        set_global_assignment -name EDA_DESIGN_INSTANCE_NAME i1 -section_id or1k_soc_top
69 
        set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "600 us" -section_id or1k_soc_top
70 
        set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME or1k_soc_top_vlg_vec_tst -section_id or1k_soc_top
71 17 xianfeng 
        set_global_assignment -name FITTER_EFFORT "AUTO FIT"
72 
        set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
73 
        set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
74 
        set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
75 
        set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
76 
        set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
77 
        set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
78 
        set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
79 12 xianfeng 
        set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
80 17 xianfeng 
        set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP OFF
81 12 xianfeng 
        set_global_assignment -name MISC_FILE /opt/workspace/xzeng/esig/trunk/or1k_soc/prj/altera/or1k_soc_top.dpf
82 
        set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_pll.v -section_id or1k_soc_top
83 
        set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_seq_wrapper.vo -section_id or1k_soc_top
84 
        set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_auk_ddr_hp_controller_wrapper.vo -section_id or1k_soc_top
85 
        set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr.v -section_id or1k_soc_top
86 
        set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_seq.vhd -section_id or1k_soc_top
87 
        set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy.v -section_id or1k_soc_top
88 
        set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_phy.v -section_id or1k_soc_top
89 
        set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_controller_phy.v -section_id or1k_soc_top
90 
        set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/testbench/altera_ddr_mem_model.v -section_id or1k_soc_top
91 
        set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/testbench/altera_ddr_full_mem_model.v -section_id or1k_soc_top
92 
        set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/testbench/altera_ddr_example_top_tb.v -section_id or1k_soc_top
93 
        set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_ex_lfsr8.v -section_id or1k_soc_top
94 
        set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_example_driver.v -section_id or1k_soc_top
95 
        set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_example_top.v -section_id or1k_soc_top
96 
        set_global_assignment -name EDA_TEST_BENCH_FILE or1k_soc_top_tb.v -section_id or1k_soc_top
97 
        set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
98 
        set_global_assignment -name MISC_FILE /home/xzeng/project/esig/or1k_soc/prj/altera/or1k_soc_top.dpf
99 
        set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
100 
        set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
101 
        set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/timescale.v
102 
        set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/initSD.v
103 
        set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/readWriteSDBlock.v
104 
        set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/readWriteSPIWireData.v
105 
        set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/sendCmd.v
106 
        set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/sm_dpMem_dc.v
107 
        set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/sm_fifoRTL.v
108 
        set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/sm_RxFifo.v
109 
        set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/sm_RxFifoBI.v
110 
        set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/sm_TxFifo.v
111 
        set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/sm_TxFifoBI.v
112 
        set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/spiCtrl.v
113 
        set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/spiMaster.v
114 
        set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/spiMaster_defines.v
115 
        set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/spiMasterWishBoneBI.v
116 
        set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/spiTxRxData.v
117 
        set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/ctrlStsRegBI.v
118 
        set_global_assignment -name SDC_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_phy_ddr_timing.sdc
119 
        set_global_assignment -name VERILOG_FILE ../../rtl/spi/rtl/verilog/timescale.v
120 
        set_global_assignment -name VERILOG_FILE ../../rtl/spi/rtl/verilog/spi_defines.v
121 
        set_global_assignment -name VERILOG_FILE ../../rtl/spi/rtl/verilog/spi_shift.v
122 
        set_global_assignment -name VERILOG_FILE ../../rtl/spi/rtl/verilog/spi_top.v
123 
        set_global_assignment -name VERILOG_FILE ../../rtl/spi/rtl/verilog/spi_clgen.v
124 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/xilinx_dist_ram_16x32.v
125 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_cop.v
126 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_crc.v
127 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_defines.v
128 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_fifo.v
129 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_maccontrol.v
130 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_macstatus.v
131 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_miim.v
132 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_outputcontrol.v
133 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_random.v
134 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_receivecontrol.v
135 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_register.v
136 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_registers.v
137 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_rxaddrcheck.v
138 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_rxcounters.v
139 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_rxethmac.v
140 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_rxstatem.v
141 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_shiftreg.v
142 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_spram_256x32.v
143 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_top.v
144 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_transmitcontrol.v
145 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_txcounters.v
146 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_txethmac.v
147 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_txstatem.v
148 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_wishbone.v
149 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/timescale.v
150 
        set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_clockgen.v
151 
        set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_wb.v
152 
        set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/timescale.v
153 
        set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_debug_if.v
154 
        set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_defines.v
155 
        set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_receiver.v
156 
        set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_regs.v
157 
        set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_rfifo.v
158 
        set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_sync_flops.v
159 
        set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_tfifo.v
160 
        set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_top.v
161 
        set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_transmitter.v
162 
        set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/raminfr.v
163 
        set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_wb_if.v
164 
        set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_cs_rf.v
165 
        set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_defines.v
166 
        set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_dp.v
167 
        set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_incn_r.v
168 
        set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_mem_if.v
169 
        set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_obct.v
170 
        set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_obct_top.v
171 
        set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_rd_fifo.v
172 
        set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_refresh.v
173 
        set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_rf.v
174 
        set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_timing.v
175 
        set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_top.v
176 
        set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_adr_sel.v
177 
        set_global_assignment -name VERILOG_FILE ../../rtl/altera_ram/altera_ram_top.v
178 
        set_global_assignment -name VERILOG_FILE ../../rtl/altera_ram/altera_ram.v
179 
        set_global_assignment -name VERILOG_FILE ../../rtl/flash_sram/flash_top.v
180 
        set_global_assignment -name VERILOG_FILE ../../rtl/gpio/rtl/verilog/gpio_top.v
181 
        set_global_assignment -name VERILOG_FILE ../../rtl/gpio/rtl/verilog/gpio_defines.v
182 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1k_soc_top.v
183 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1k_soc_defines.v
184 
        set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_top.v
185 
        set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_defines.v
186 
        set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_master_if.v
187 
        set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_msel.v
188 
        set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_pri_dec.v
189 
        set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_pri_enc.v
190 
        set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_rf.v
191 
        set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_slave_if.v
192 
        set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_arb.v
193 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/timescale.v
194 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_amultp2_32x32.v
195 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_cfgr.v
196 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_cpu.v
197 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_ctrl.v
198 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_dc_fsm.v
199 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_dc_ram.v
200 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_dc_tag.v
201 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_dc_top.v
202 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_defines.v
203 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_dmmu_tlb.v
204 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_dmmu_top.v
205 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_dpram_256x32.v
206 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_dpram_32x32.v
207 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_du.v
208 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_except.v
209 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_freeze.v
210 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_genpc.v
211 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_gmultp2_32x32.v
212 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_ic_fsm.v
213 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_ic_ram.v
214 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_ic_tag.v
215 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_ic_top.v
216 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_if.v
217 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_immu_tlb.v
218 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_immu_top.v
219 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_iwb_biu.v
220 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_lsu.v
221 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_mem2reg.v
222 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_mult_mac.v
223 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_operandmuxes.v
224 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_pic.v
225 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_pm.v
226 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_qmem_top.v
227 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_reg2mem.v
228 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_rf.v
229 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_rfram_generic.v
230 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_sb.v
231 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_sb_fifo.v
232 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_1024x32.v
233 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
234 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_1024x8.v
235 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_128x32.v
236 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_2048x32.v
237 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
238 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_2048x8.v
239 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_256x21.v
240 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_32x24.v
241 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_512x20.v
242 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_64x14.v
243 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_64x22.v
244 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_64x24.v
245 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_sprs.v
246 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_top.v
247 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_tpram_32x32.v
248 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_tt.v
249 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_wb_biu.v
250 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_wbmux.v
251 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
252 
        set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_alu.v
253 
        set_global_assignment -name QIP_FILE ../../rtl/altera_pll/altera_pll.qip
254 
        set_global_assignment -name VERILOG_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_top.v
255 
        set_global_assignment -name VECTOR_WAVEFORM_FILE or1k_soc_top.vwf
256 
        set_global_assignment -name VECTOR_WAVEFORM_FILE altera_ram.vwf
257 
        set_global_assignment -name QIP_FILE ../../rtl/altera_ddr_ctrl/altera_ddr.qip
258 
        set_global_assignment -name VHDL_FILE ../../rtl/altera_ddr_ctrl/auk_ddr_hp_controller.vhd
259 
        set_global_assignment -name MISC_FILE /opt/project/esig/or1k_soc/prj/altera/or1k_soc_top.dpf
260 
        set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE or1k_soc_top.vwf
261 
        set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE altera_ram.vwf
262 
        set_global_assignment -name VHDL_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/altera_virtual_jtag/rtl/vhdl/altera_virtual_jtag.vhd
263 
        set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v
264 
        set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
265 
        set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v
266 
        set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v
267 
        set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
268 
        set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v
269 
        set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v
270 
        set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
271 
        set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
272 
        set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v
273 
        set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../../altera9.0/quartus/libraries/megafunctions/sld_virtual_jtag.v -section_id or1k_soc_top
274 
        set_global_assignment -name ENABLE_SIGNALTAP OFF
275 
        set_global_assignment -name USE_SIGNALTAP_FILE sd_loader_test.stp
276 17 xianfeng 
        set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
277 12 xianfeng 
        set_global_assignment -name SEARCH_PATH ../../rtl/altera_ddr_ctrl/.
278 
        set_global_assignment -name SEARCH_PATH "../../rtl/altera_ddr_ctrl/ddr_high_performance_controller-library"
279 17 xianfeng 
        set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
280 
        set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
281 12 xianfeng 
        set_location_assignment PIN_B9 -to wb_clk_pad_i
282 
        set_location_assignment PIN_V9 -to ddr_pll_clk_pad_i
283 
        set_location_assignment PIN_N2 -to rst_n_pad_i
284 
        set_location_assignment PIN_E18 -to uart_srx_pad_i
285 
        set_location_assignment PIN_H17 -to uart_stx_pad_o
286 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dqs_io[1]
287 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dqs_io[0]
288 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[12]
289 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[9]
290 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[8]
291 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[11]
292 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[10]
293 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_we_n_o
294 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[0]
295 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[1]
296 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[2]
297 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[3]
298 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[4]
299 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[5]
300 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[6]
301 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[7]
302 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[9]
303 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[10]
304 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[11]
305 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[12]
306 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[13]
307 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[14]
308 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[15]
309 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_cs_n_o[0]
310 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_clk_n_io[0]
311 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_cke_o[0]
312 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_cas_n_o
313 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_clk_io[0]
314 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_ba_o[0]
315 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_ba_o[1]
316 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[0]
317 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[1]
318 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[2]
319 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[3]
320 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[4]
321 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[5]
322 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[6]
323 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[7]
324 
        set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
325 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_ras_n_o
326 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dm_o[0]
327 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dm_o[1]
328 
        set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[8]
329 
        set_location_assignment PIN_U16 -to ddr_mem_addr_o[12]
330 
        set_location_assignment PIN_V17 -to ddr_mem_addr_o[11]
331 
        set_location_assignment PIN_U17 -to ddr_mem_addr_o[10]
332 
        set_location_assignment PIN_V13 -to ddr_mem_addr_o[9]
333 
        set_location_assignment PIN_T13 -to ddr_mem_addr_o[8]
334 
        set_location_assignment PIN_T14 -to ddr_mem_addr_o[7]
335 
        set_location_assignment PIN_P6 -to ddr_mem_addr_o[6]
336 
        set_location_assignment PIN_P7 -to ddr_mem_addr_o[5]
337 
        set_location_assignment PIN_P8 -to ddr_mem_addr_o[4]
338 
        set_location_assignment PIN_U8 -to ddr_mem_addr_o[3]
339 
        set_location_assignment PIN_U7 -to ddr_mem_addr_o[2]
340 
        set_location_assignment PIN_U5 -to ddr_mem_addr_o[1]
341 
        set_location_assignment PIN_U1 -to ddr_mem_addr_o[0]
342 
        set_location_assignment PIN_V12 -to ddr_mem_ba_o[1]
343 
        set_location_assignment PIN_V11 -to ddr_mem_ba_o[0]
344 
        set_location_assignment PIN_T4 -to ddr_mem_cas_n_o
345 
        set_location_assignment PIN_R13 -to ddr_mem_cke_o[0]
346 
        set_location_assignment PIN_U2 -to ddr_mem_clk_io[0]
347 
        set_location_assignment PIN_V2 -to ddr_mem_clk_n_io[0]
348 
        set_location_assignment PIN_V1 -to ddr_mem_cs_n_o[0]
349 
        set_location_assignment PIN_V8 -to ddr_mem_dm_o[1]
350 
        set_location_assignment PIN_V3 -to ddr_mem_dm_o[0]
351 
        set_location_assignment PIN_U15 -to ddr_mem_we_n_o
352 
        set_location_assignment PIN_V16 -to ddr_mem_ras_n_o
353 
        set_location_assignment PIN_U3 -to ddr_mem_dqs_io[0]
354 
        set_location_assignment PIN_T8 -to ddr_mem_dqs_io[1]
355 
        set_location_assignment PIN_U4 -to ddr_mem_dq_io[0]
356 
        set_location_assignment PIN_V4 -to ddr_mem_dq_io[1]
357 
        set_location_assignment PIN_R8 -to ddr_mem_dq_io[2]
358 
        set_location_assignment PIN_V5 -to ddr_mem_dq_io[3]
359 
        set_location_assignment PIN_P9 -to ddr_mem_dq_io[4]
360 
        set_location_assignment PIN_U6 -to ddr_mem_dq_io[5]
361 
        set_location_assignment PIN_V6 -to ddr_mem_dq_io[6]
362 
        set_location_assignment PIN_V7 -to ddr_mem_dq_io[7]
363 
        set_location_assignment PIN_U13 -to ddr_mem_dq_io[8]
364 
        set_location_assignment PIN_U12 -to ddr_mem_dq_io[9]
365 
        set_location_assignment PIN_U11 -to ddr_mem_dq_io[10]
366 
        set_location_assignment PIN_V15 -to ddr_mem_dq_io[11]
367 
        set_location_assignment PIN_U14 -to ddr_mem_dq_io[12]
368 
        set_location_assignment PIN_R11 -to ddr_mem_dq_io[13]
369 
        set_location_assignment PIN_P10 -to ddr_mem_dq_io[14]
370 
        set_location_assignment PIN_V14 -to ddr_mem_dq_io[15]
371 
        set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_clk_io[0]
372 
        set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_clk_n_io[0]
373 
        set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_cs_n_o[0]
374 
        set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_cke_o[0]
375 
        set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[0]
376 
        set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[1]
377 
        set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[2]
378 
        set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[3]
379 
        set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[4]
380 
        set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[5]
381 
        set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[6]
382 
        set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[7]
383 
        set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[8]
384 
        set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[9]
385 
        set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[10]
386 
        set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[11]
387 
        set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[12]
388 
        set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_ba_o[0]
389 
        set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_ba_o[1]
390 
        set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_ras_n_o
391 
        set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_cas_n_o
392 
        set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_we_n_o
393 
        set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[0]
394 
        set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[1]
395 
        set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[2]
396 
        set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[3]
397 
        set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[4]
398 
        set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[5]
399 
        set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[6]
400 
        set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[7]
401 
        set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[8]
402 
        set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[9]
403 
        set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[10]
404 
        set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[11]
405 
        set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[12]
406 
        set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[13]
407 
        set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[14]
408 
        set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[15]
409 
        set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dqs_io[0]
410 
        set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dqs_io[1]
411 
        set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dm_o[0]
412 
        set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dm_o[1]
413 
        set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[0]
414 
        set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[1]
415 
        set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[2]
416 
        set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[3]
417 
        set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[4]
418 
        set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[5]
419 
        set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[6]
420 
        set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[7]
421 
        set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[8]
422 
        set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[9]
423 
        set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[10]
424 
        set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[11]
425 
        set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[12]
426 
        set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[13]
427 
        set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[14]
428 
        set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[15]
429 
        set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dqs_io[0]
430 
        set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dqs_io[1]
431 
        set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dm_o[0]
432 
        set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dm_o[1]
433 
        set_instance_assignment -name CKN_CK_PAIR ON -from ddr_mem_clk_n_io[0] -to ddr_mem_clk_io[0]
434 
        set_location_assignment PIN_P13 -to gpio_a_pad_io[0]
435 
        set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to gpio_a_pad_io[0]
436 
        set_location_assignment PIN_M2 -to sd_card_clk_pad_o
437 
        set_location_assignment PIN_N8 -to sd_card_cs_n_pad_o
438 
        set_location_assignment PIN_M3 -to sd_card_data_pad_i
439 
        set_location_assignment PIN_L6 -to sd_card_data_pad_o
440 
        set_location_assignment PIN_N18 -to eth_tx_clk_pad_i
441 
        set_location_assignment PIN_L17 -to eth_tx_en_pad_o
442 
        set_location_assignment PIN_M18 -to eth_txd_pad_o[0]
443 
        set_location_assignment PIN_L14 -to eth_txd_pad_o[1]
444 
        set_location_assignment PIN_L15 -to eth_txd_pad_o[2]
445 
        set_location_assignment PIN_P17 -to eth_txd_pad_o[3]
446 
        set_location_assignment PIN_F17 -to eth_rx_clk_pad_i
447 
        set_location_assignment PIN_G18 -to eth_rx_dv_pad_i
448 
        set_location_assignment PIN_L3 -to eth_crs_pad_i
449 
        set_location_assignment PIN_L4 -to eth_rx_er_pad_i
450 
        set_location_assignment PIN_G17 -to eth_col_pad_i
451 
        set_location_assignment PIN_P2 -to eth_rxd_pad_i[0]
452 
        set_location_assignment PIN_P1 -to eth_rxd_pad_i[1]
453 
        set_location_assignment PIN_T3 -to eth_rxd_pad_i[2]
454 
        set_location_assignment PIN_R3 -to eth_rxd_pad_i[3]
455 
        set_location_assignment PIN_P18 -to eth_mdc_pad_o
456 
        set_location_assignment PIN_N7 -to eth_mdio_pad_io
457 
        set_location_assignment PIN_H18 -to eth_reset_n_pad_o
458 
        set_location_assignment PIN_N9 -to led3_pad_o
459 
 
460 
        # Commit assignments
461 
        export_assignments
462 
 
463 
        # Close project
464 
        if {$need_to_close_project} {
465 
                project_close
466 
        }
467 
}

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