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xianfeng |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// OR1K test app definitions ////
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//// ////
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//// This file is part of the OR1K test application ////
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//// http://www.opencores.org/cores/or1k/xess/ ////
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//// ////
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//// Description ////
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//// DEfine target technology etc. Right now FIFOs are available ////
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//// only for Xilinx Virtex FPGAs. (TARGET_VIRTEX) ////
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//// ////
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//// To Do: ////
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//// - nothing really ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, damjan.lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: xsv_fpga_defines.v,v $
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// Revision 1.3 2010-01-08 01:41:07 Nathan
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// Removed unused, non-existant include from CPU behavioral model. Minor text edits.
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//
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// Revision 1.2 2008/07/11 08:16:01 Nathan
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// Ran through dos2unix
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//
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// Revision 1.1 2008/07/08 19:11:54 Nathan
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// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
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//
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// Revision 1.4 2004/04/05 08:44:35 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.2 2002/03/29 20:58:51 lampret
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// Changed hardcoded address for fake MC to use a define.
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//
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// Revision 1.1.1.1 2002/03/21 16:55:44 lampret
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// First import of the "new" XESS XSV environment.
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//
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//
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//
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//
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// Define to target to Xilinx Virtex
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//
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//`define TARGET_VIRTEX
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//
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// Interrupts
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//
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`define APP_INT_RES1 1:0
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`define APP_INT_UART 2
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`define APP_INT_RES2 3
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`define APP_INT_ETH 4
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`define APP_INT_PS2 5
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`define APP_INT_RES3 19:6
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//
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// Address map
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//
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`define APP_ADDR_DEC_W 3
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`define APP_ADDR_SDRAM `APP_ADDR_DEC_W'b001
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`define APP_ADDR_DEC2_W 8
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`define APP_ADDR_OCRAM `APP_ADDR_DEC2_W'h00
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`define APP_ADDR_DECP_W 8
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//`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h99
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`define APP_ADDR_VGA `APP_ADDR_DECP_W'h97
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`define APP_ADDR_ETH `APP_ADDR_DECP_W'h92
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`define APP_ADDR_AUDIO `APP_ADDR_DECP_W'h9d
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`define APP_ADDR_UART `APP_ADDR_DECP_W'h90
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`define APP_ADDR_PS2 `APP_ADDR_DECP_W'h94
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`define APP_ADDR_RES1 `APP_ADDR_DECP_W'h9e
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//`define APP_ADDR_RES2 `APP_ADDR_DECP_W'h9f
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//`define APP_ADDR_FAKEMC 4'h6
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// For simulation...
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// `define DBG_IF_MODEL 1
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