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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [bench/] [simulated_system/] [cpu_behavioral.v] - Blame information for rev 21

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// cpu_behavioral.v                                             ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC Debug Interface.               ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2004 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: cpu_behavioral.v,v $
// Revision 1.2  2010-01-08 01:41:08  Nathan
// Removed unused, non-existant include from CPU behavioral model.  Minor text edits.
//
// Revision 1.1  2008/07/08 19:11:55  Nathan
// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram.  Renamed sim-only testbench directory from verilog to simulated_system.
//
// Revision 1.1  2008/06/18 18:34:48  Nathan
// Initial working version.  Only Wishbone module implemented.  Simple testbench included, with CPU and Wishbone behavioral models from the old dbg_interface.
//
// Revision 1.1.1.1  2008/05/14 12:07:35  Nathan
// Original from OpenCores
//
// Revision 1.4  2004/03/28 20:27:40  igorm
// New release of the debug interface (3rd. release).
//
// Revision 1.3  2004/01/22 11:07:28  mohor
// test stall_test added.
//
// Revision 1.2  2004/01/17 18:01:31  mohor
// New version.
//
// Revision 1.1  2004/01/17 17:01:25  mohor
// Almost finished.
//
//
//
//
//
`include "timescale.v"
 
 
module cpu_behavioral
                   (
                    // CPU signals
                    cpu_rst_i,
                    cpu_clk_o,
                    cpu_addr_i,
                    cpu_data_o,
                    cpu_data_i,
                    cpu_bp_o,
                    cpu_stall_i,
                    cpu_stb_i,
                    cpu_we_i,
                    cpu_ack_o,
                    cpu_rst_o
                   );
 
 
// CPU signals
input         cpu_rst_i;
output        cpu_clk_o;
input  [31:0] cpu_addr_i;
output [31:0] cpu_data_o;
input  [31:0] cpu_data_i;
output        cpu_bp_o;
input         cpu_stall_i;
input         cpu_stb_i;
input         cpu_we_i;
output        cpu_ack_o;
output        cpu_rst_o;
 
reg           cpu_clk_o;
reg    [31:0] cpu_data_o;
reg           cpu_bp_o;
reg           cpu_ack_o;
reg           cpu_ack_q;
wire          cpu_ack;
initial
begin
  cpu_clk_o = 1'b0;
  forever #5 cpu_clk_o = ~cpu_clk_o;
end
 
 
initial
begin
  cpu_bp_o = 1'b0;
end
 
assign #200 cpu_ack = cpu_stall_i & cpu_stb_i;
 
 
 
always @ (posedge cpu_clk_o or posedge cpu_rst_i)
begin
  if (cpu_rst_i)
    begin
      cpu_ack_o <= #1 1'b0;
      cpu_ack_q <= #1 1'b0;
    end
  else
    begin
      cpu_ack_o <= #1 cpu_ack;
      cpu_ack_q <= #1 cpu_ack_o;
    end
end
 
always @ (posedge cpu_clk_o or posedge cpu_rst_i)
begin
  if (cpu_rst_i)
    cpu_data_o <= #1 32'h12345678;
  else if (cpu_ack_o && (!cpu_ack_q))
    cpu_data_o <= #1 cpu_data_o + 32'h11111111;
end
 
 
 
 
endmodule
 

Line No.	Rev	Author	Line
1	21	xianfeng	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// cpu_behavioral.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC Debug Interface. ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2004 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: cpu_behavioral.v,v $`
46			`// Revision 1.2 2010-01-08 01:41:08 Nathan`
47			`// Removed unused, non-existant include from CPU behavioral model. Minor text edits.`
48			`//`
49			`// Revision 1.1 2008/07/08 19:11:55 Nathan`
50			`// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.`
51			`//`
52			`// Revision 1.1 2008/06/18 18:34:48 Nathan`
53			`// Initial working version. Only Wishbone module implemented. Simple testbench included, with CPU and Wishbone behavioral models from the old dbg_interface.`
54			`//`
55			`// Revision 1.1.1.1 2008/05/14 12:07:35 Nathan`
56			`// Original from OpenCores`
57			`//`
58			`// Revision 1.4 2004/03/28 20:27:40 igorm`
59			`// New release of the debug interface (3rd. release).`
60			`//`
61			`// Revision 1.3 2004/01/22 11:07:28 mohor`
62			`// test stall_test added.`
63			`//`
64			`// Revision 1.2 2004/01/17 18:01:31 mohor`
65			`// New version.`
66			`//`
67			`// Revision 1.1 2004/01/17 17:01:25 mohor`
68			`// Almost finished.`
69			`//`
70			`//`
71			`//`
72			`//`
73			`//`
74			`include "timescale.v"
75
76
77			`module cpu_behavioral`
78			`(`
79			`// CPU signals`
80			`cpu_rst_i,`
81			`cpu_clk_o,`
82			`cpu_addr_i,`
83			`cpu_data_o,`
84			`cpu_data_i,`
85			`cpu_bp_o,`
86			`cpu_stall_i,`
87			`cpu_stb_i,`
88			`cpu_we_i,`
89			`cpu_ack_o,`
90			`cpu_rst_o`
91			`);`
92
93
94			`// CPU signals`
95			`input cpu_rst_i;`
96			`output cpu_clk_o;`
97			`input [31:0] cpu_addr_i;`
98			`output [31:0] cpu_data_o;`
99			`input [31:0] cpu_data_i;`
100			`output cpu_bp_o;`
101			`input cpu_stall_i;`
102			`input cpu_stb_i;`
103			`input cpu_we_i;`
104			`output cpu_ack_o;`
105			`output cpu_rst_o;`
106
107			`reg cpu_clk_o;`
108			`reg [31:0] cpu_data_o;`
109			`reg cpu_bp_o;`
110			`reg cpu_ack_o;`
111			`reg cpu_ack_q;`
112			`wire cpu_ack;`
113			`initial`
114			`begin`
115			`cpu_clk_o = 1'b0;`
116			`forever #5 cpu_clk_o = ~cpu_clk_o;`
117			`end`
118
119
120			`initial`
121			`begin`
122			`cpu_bp_o = 1'b0;`
123			`end`
124
125			`assign #200 cpu_ack = cpu_stall_i & cpu_stb_i;`
126
127
128
129			`always @ (posedge cpu_clk_o or posedge cpu_rst_i)`
130			`begin`
131			`if (cpu_rst_i)`
132			`begin`
133			`cpu_ack_o <= #1 1'b0;`
134			`cpu_ack_q <= #1 1'b0;`
135			`end`
136			`else`
137			`begin`
138			`cpu_ack_o <= #1 cpu_ack;`
139			`cpu_ack_q <= #1 cpu_ack_o;`
140			`end`
141			`end`
142
143			`always @ (posedge cpu_clk_o or posedge cpu_rst_i)`
144			`begin`
145			`if (cpu_rst_i)`
146			`cpu_data_o <= #1 32'h12345678;`
147			`else if (cpu_ack_o && (!cpu_ack_q))`
148			`cpu_data_o <= #1 cpu_data_o + 32'h11111111;`
149			`end`
150
151
152
153
154			`endmodule`
155

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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [bench/] [simulated_system/] [cpu_behavioral.v] - Blame information for rev 21