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//////////////////////////////////////////////////////////////////////
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//// ////
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//// timescale.v ////
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//// ////
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//// ////
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//// This file is part of the SoC Debug Interface. ////
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//// http://www.opencores.org/projects/DebugInterface/ ////
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//// ////
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//// Author(s): ////
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//// Igor Mohor (igorm@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 - 2004 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: timescale.v,v $
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// Revision 1.2 2010-01-08 01:41:08 Nathan
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// Removed unused, non-existant include from CPU behavioral model. Minor text edits.
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//
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// Revision 1.1 2008/07/08 19:11:56 Nathan
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// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.
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//
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// Revision 1.1 2008/06/18 18:34:48 Nathan
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// Initial working version. Only Wishbone module implemented. Simple testbench included, with CPU and Wishbone behavioral models from the old dbg_interface.
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//
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// Revision 1.1.1.1 2008/05/14 12:07:36 Nathan
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// Original from OpenCores
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//
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// Revision 1.4 2004/03/28 20:27:40 igorm
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// New release of the debug interface (3rd. release).
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//
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// Revision 1.3 2004/01/17 17:01:25 mohor
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// Almost finished.
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//
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// Revision 1.2 2003/12/23 14:26:01 mohor
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// New version of the debug interface. Not finished, yet.
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//
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//
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//
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//
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`timescale 1ns/10ps
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