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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  wb_model_defines.v                                          ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC Debug Interface.               ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2004 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: wb_model_defines.v,v $
// Revision 1.2  2010-01-08 01:41:08  Nathan
// Removed unused, non-existant include from CPU behavioral model.  Minor text edits.
//
// Revision 1.1  2008/07/08 19:11:57  Nathan
// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram.  Renamed sim-only testbench directory from verilog to simulated_system.
//
// Revision 1.1  2008/06/18 18:34:48  Nathan
// Initial working version.  Only Wishbone module implemented.  Simple testbench included, with CPU and Wishbone behavioral models from the old dbg_interface.
//
// Revision 1.1.1.1  2008/05/14 12:07:36  Nathan
// Original from OpenCores
//
// Revision 1.2  2004/03/28 20:27:40  igorm
// New release of the debug interface (3rd. release).
//
// Revision 1.1  2003/12/23 14:26:01  mohor
// New version of the debug interface. Not finished, yet.
//
//
//
 
// WISHBONE frequency in GHz
`define WB_FREQ 0.100
 
// memory frequency in GHz
`define MEM_FREQ 0.100
 
// setup and hold time definitions for WISHBONE - used in BFMs for signal generation
`define Tsetup 4
`define Thold  1
 
// how many clock cycles should model wait for design's response - integer 32 bit value
`define WAIT_FOR_RESPONSE 1023
 
// maximum number of transactions allowed in single call to block or cab transfer routines
`define MAX_BLK_SIZE  1024
 
// maximum retry terminations allowed for WISHBONE master to repeat an access
`define WB_TB_MAX_RTY 0
 
 
// some common types and defines
`define WB_ADDR_WIDTH 32
`define WB_DATA_WIDTH 32
`define WB_SEL_WIDTH `WB_DATA_WIDTH/8
`define WB_TAG_WIDTH 5
`define WB_ADDR_TYPE [(`WB_ADDR_WIDTH - 1):0]
`define WB_DATA_TYPE [(`WB_DATA_WIDTH - 1):0]
`define WB_SEL_TYPE  [(`WB_SEL_WIDTH  - 1):0]
`define WB_TAG_TYPE  [(`WB_TAG_WIDTH  - 1):0]
 
// read cycle stimulus - consists of:
//    - address field - which address read will be performed from
//    - sel field     - what byte select value should be
//    - tag field     - what tag values should be put on the bus
`define READ_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0]
`define READ_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH)
`define READ_ADDRESS  [(`WB_ADDR_WIDTH - 1):0]
`define READ_SEL      [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH - 1):`WB_ADDR_WIDTH]
`define READ_TAG_STIM [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_SEL_WIDTH)]
 
// read cycle return type consists of:
//    - read data field
//    - tag field received from WISHBONE
//    - wishbone slave response fields - ACK, ERR and RTY
//    - test bench error indicator (when testcase has not used wb master model properly)
//    - how much data was actually transfered
`define READ_RETURN_TYPE [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):0]
`define READ_DATA        [(32 + `WB_DATA_WIDTH + 4 - 1):32 + 4]
`define READ_TAG_RET     [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):(`WB_DATA_WIDTH + 32 + 4)]
`define READ_RETURN_LENGTH (32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1)
 
// write cycle stimulus type consists of
//    - address field
//    - data field
//    - sel field
//    - tag field
`define WRITE_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0]
`define WRITE_ADDRESS       [(`WB_ADDR_WIDTH - 1):0]
`define WRITE_DATA          [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH - 1):`WB_ADDR_WIDTH]
`define WRITE_SEL           [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH)]
`define WRITE_TAG_STIM      [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH)]
 
// length of WRITE_STIMULUS
`define WRITE_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH)
 
// write cycle return type consists of:
//    - test bench error indicator (when testcase has not used wb master model properly)
//    - wishbone slave response fields - ACK, ERR and RTY
//    - tag field received from WISHBONE
//    - how much data was actually transfered
`define WRITE_RETURN_TYPE [(32 + 4 + `WB_TAG_WIDTH - 1):0]
`define WRITE_TAG_RET     [(32 + 4 + `WB_TAG_WIDTH - 1):32 + 4]
 
// this four fields are common to both read and write routines return values
`define TB_ERROR_BIT [0]
`define CYC_ACK [1]
`define CYC_RTY [2]
`define CYC_ERR [3]
`define CYC_RESPONSE [3:1]
`define CYC_ACTUAL_TRANSFER [35:4]
 
// block transfer flags
`define WB_TRANSFER_FLAGS [41:0]
// consists of:
// - number of transfer cycles to perform
// - flag that enables retry termination handling - if disabled, block transfer routines will return on any termination other than acknowledge
// - flag indicating CAB transfer is to be performed - ignored by all single transfer routines
// - number of initial wait states to insert
// - number of subsequent wait states to insert
`define WB_TRANSFER_SIZE     [41:10]
`define WB_TRANSFER_AUTO_RTY [8]
`define WB_TRANSFER_CAB      [9]
`define INIT_WAITS           [3:0]
`define SUBSEQ_WAITS         [7:4]
 
// wb slave response
`define ACK_RESPONSE  3'b100
`define ERR_RESPONSE  3'b010
`define RTY_RESPONSE  3'b001
`define NO_RESPONSE   3'b000

Line No.	Rev	Author	Line
1	21	xianfeng	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// wb_model_defines.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC Debug Interface. ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// - Miha Dolenc (mihad@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2004 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: wb_model_defines.v,v $`
46			`// Revision 1.2 2010-01-08 01:41:08 Nathan`
47			`// Removed unused, non-existant include from CPU behavioral model. Minor text edits.`
48			`//`
49			`// Revision 1.1 2008/07/08 19:11:57 Nathan`
50			`// Added second testbench to simulate a complete system, including OR1200, wb_conbus, and onchipram. Renamed sim-only testbench directory from verilog to simulated_system.`
51			`//`
52			`// Revision 1.1 2008/06/18 18:34:48 Nathan`
53			`// Initial working version. Only Wishbone module implemented. Simple testbench included, with CPU and Wishbone behavioral models from the old dbg_interface.`
54			`//`
55			`// Revision 1.1.1.1 2008/05/14 12:07:36 Nathan`
56			`// Original from OpenCores`
57			`//`
58			`// Revision 1.2 2004/03/28 20:27:40 igorm`
59			`// New release of the debug interface (3rd. release).`
60			`//`
61			`// Revision 1.1 2003/12/23 14:26:01 mohor`
62			`// New version of the debug interface. Not finished, yet.`
63			`//`
64			`//`
65			`//`
66
67			`// WISHBONE frequency in GHz`
68			`define WB_FREQ 0.100
69
70			`// memory frequency in GHz`
71			`define MEM_FREQ 0.100
72
73			`// setup and hold time definitions for WISHBONE - used in BFMs for signal generation`
74			`define Tsetup 4
75			`define Thold 1
76
77			`// how many clock cycles should model wait for design's response - integer 32 bit value`
78			`define WAIT_FOR_RESPONSE 1023
79
80			`// maximum number of transactions allowed in single call to block or cab transfer routines`
81			`define MAX_BLK_SIZE 1024
82
83			`// maximum retry terminations allowed for WISHBONE master to repeat an access`
84			`define WB_TB_MAX_RTY 0
85
86
87			`// some common types and defines`
88			`define WB_ADDR_WIDTH 32
89			`define WB_DATA_WIDTH 32
90			`define WB_SEL_WIDTH `WB_DATA_WIDTH/8
91			`define WB_TAG_WIDTH 5
92			`define WB_ADDR_TYPE [(`WB_ADDR_WIDTH - 1):0]
93			`define WB_DATA_TYPE [(`WB_DATA_WIDTH - 1):0]
94			`define WB_SEL_TYPE [(`WB_SEL_WIDTH - 1):0]
95			`define WB_TAG_TYPE [(`WB_TAG_WIDTH - 1):0]
96
97			`// read cycle stimulus - consists of:`
98			`// - address field - which address read will be performed from`
99			`// - sel field - what byte select value should be`
100			`// - tag field - what tag values should be put on the bus`
101			`define READ_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0]
102			`define READ_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH)
103			`define READ_ADDRESS [(`WB_ADDR_WIDTH - 1):0]
104			`define READ_SEL [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH - 1):`WB_ADDR_WIDTH]
105			`define READ_TAG_STIM [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_SEL_WIDTH)]
106
107			`// read cycle return type consists of:`
108			`// - read data field`
109			`// - tag field received from WISHBONE`
110			`// - wishbone slave response fields - ACK, ERR and RTY`
111			`// - test bench error indicator (when testcase has not used wb master model properly)`
112			`// - how much data was actually transfered`
113			`define READ_RETURN_TYPE [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):0]
114			`define READ_DATA [(32 + `WB_DATA_WIDTH + 4 - 1):32 + 4]
115			`define READ_TAG_RET [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):(`WB_DATA_WIDTH + 32 + 4)]
116			`define READ_RETURN_LENGTH (32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1)
117
118			`// write cycle stimulus type consists of`
119			`// - address field`
120			`// - data field`
121			`// - sel field`
122			`// - tag field`
123			`define WRITE_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0]
124			`define WRITE_ADDRESS [(`WB_ADDR_WIDTH - 1):0]
125			`define WRITE_DATA [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH - 1):`WB_ADDR_WIDTH]
126			`define WRITE_SEL [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH)]
127			`define WRITE_TAG_STIM [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH)]
128
129			`// length of WRITE_STIMULUS`
130			`define WRITE_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH)
131
132			`// write cycle return type consists of:`
133			`// - test bench error indicator (when testcase has not used wb master model properly)`
134			`// - wishbone slave response fields - ACK, ERR and RTY`
135			`// - tag field received from WISHBONE`
136			`// - how much data was actually transfered`
137			`define WRITE_RETURN_TYPE [(32 + 4 + `WB_TAG_WIDTH - 1):0]
138			`define WRITE_TAG_RET [(32 + 4 + `WB_TAG_WIDTH - 1):32 + 4]
139
140			`// this four fields are common to both read and write routines return values`
141			`define TB_ERROR_BIT [0]
142			`define CYC_ACK [1]
143			`define CYC_RTY [2]
144			`define CYC_ERR [3]
145			`define CYC_RESPONSE [3:1]
146			`define CYC_ACTUAL_TRANSFER [35:4]
147
148			`// block transfer flags`
149			`define WB_TRANSFER_FLAGS [41:0]
150			`// consists of:`
151			`// - number of transfer cycles to perform`
152			`// - flag that enables retry termination handling - if disabled, block transfer routines will return on any termination other than acknowledge`
153			`// - flag indicating CAB transfer is to be performed - ignored by all single transfer routines`
154			`// - number of initial wait states to insert`
155			`// - number of subsequent wait states to insert`
156			`define WB_TRANSFER_SIZE [41:10]
157			`define WB_TRANSFER_AUTO_RTY [8]
158			`define WB_TRANSFER_CAB [9]
159			`define INIT_WAITS [3:0]
160			`define SUBSEQ_WAITS [7:4]
161
162			`// wb slave response`
163			`define ACK_RESPONSE 3'b100
164			`define ERR_RESPONSE 3'b010
165			`define RTY_RESPONSE 3'b001
166			`define NO_RESPONSE 3'b000

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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [bench/] [simulated_system/] [wb_model_defines.v] - Blame information for rev 21