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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [verilog/] [adbg_defines.v] - Blame information for rev 21

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1 21 xianfeng
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  adbg_defines.v                                              ////
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////                                                              ////
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////                                                              ////
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////  This file is part of the Advanced Debug Interface.          ////
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////                                                              ////
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////  Author(s):                                                  ////
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////       Nathan Yawn (nathan.yawn@opencores.org)                ////
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////                                                              ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2008 - 2010 Authors                            ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: adbg_defines.v,v $
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// Revision 1.4  2010-01-14 02:03:40  Nathan
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// Make hi-speed mode the default
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//
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// Revision 1.3  2010-01-10 22:53:48  Nathan
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// Added define for hi-speed mode
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//
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// Revision 1.2  2009/05/17 20:54:56  Nathan
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// Changed email address to opencores.org
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//
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// Revision 1.1  2008/07/22 20:28:30  Nathan
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// Changed names of all files and modules (prefixed an a, for advanced).  Cleanup, indenting.  No functional changes.
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//
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// Revision 1.5  2008/07/06 20:02:53  Nathan
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// Fixes for synthesis with Xilinx ISE (also synthesizable with 
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// Quartus II 7.0).  Ran through dos2unix.
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//
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// Revision 1.4  2008/06/30 20:09:20  Nathan
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// Removed code to select top-level module as active (it served no 
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// purpose).  Re-numbered modules, requiring changes to testbench and software driver.
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//
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// Length of the MODULE ID register
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`define DBG_TOP_MODULE_ID_LENGTH        2
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// How many modules can be supported by the module id length
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`define     DBG_TOP_MAX_MODULES           4
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// Chains
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`define DBG_TOP_WISHBONE_DEBUG_MODULE  2'h0
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`define DBG_TOP_CPU0_DEBUG_MODULE      2'h1
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`define DBG_TOP_CPU1_DEBUG_MODULE      2'h2
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// Length of data
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`define DBG_TOP_MODULE_DATA_LEN  53
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// If WISHBONE sub-module is supported uncomment the folowing line
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`define DBG_WISHBONE_SUPPORTED
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// If CPU_0 sub-module is supported uncomment the folowing line
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`define DBG_CPU0_SUPPORTED
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// If CPU_1 sub-module is supported uncomment the folowing line
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//`define DBG_CPU1_SUPPORTED
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// If this is defined, status bits will be skipped on burst
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// writes to improve download speeds.
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`define ADBG_USE_HISPEED

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