Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

/**********************************************************************************

*                                                                                 *

*  This verilog file is a part of the Boundary Scan Implementation and comes in   *

*  a pack with several other files. It is fully IEEE 1149.1 compliant.            *

*  For details check www.opencores.org (pdf files, bsdl file, etc.)               *

*                                                                                 *

*  Copyright (C) 2000 Igor Mohor (igorm@opencores.org) and OPENCORES.ORG          *

*                                                                                 *

*  This program is free software; you can redistribute it and/or modify           *

*  it under the terms of the GNU General Public License as published by           *

*  the Free Software Foundation; either version 2 of the License, or              *

*  (at your option) any later version.                                            *

*                                                                                 *

*  See the file COPYING for the full details of the license.                      *

*                                                                                 *

*  OPENCORES.ORG is looking for new open source IP cores and developers that      *

*  would like to help in our mission.                                             *

*                                                                                 *

**********************************************************************************/

/**********************************************************************************

*                                                                                 *

*         I/O Control Cell:                                                             *

*                                                                                 *

*         OutputControl: Output Control from on-chip logic                              *

*         FromPreviousBSCell: Value from previous boundary scan cell                    *

*         ToNextBSCell: Value for next boundary scan cell                               *

*         CaptureDR, ShiftDR, UpdateDR: TAP states                                      *

*         extest: Instruction Register Command                                          *

*         TCK: Test Clock                                                               *

*                                                                                 *

*         Output Enable can be generated by running CaptureDR-UpdateDR sequence or      *

*         shifting data for the exact number of time                                    *

*                                                                                 *

**********************************************************************************/

// This is not a top module 

module ControlCell( OutputControl, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, ToOutputEnable);

input  OutputControl;

input  FromPreviousBSCell;

input  CaptureDR;

input  ShiftDR;

input  UpdateDR;

input  extest;

input  TCK;

reg Latch;

output ToNextBSCell;

output ToOutputEnable;

reg    ToNextBSCell;

reg ShiftedControl;

wire SelectedInput = CaptureDR? OutputControl : FromPreviousBSCell;

always @ (posedge TCK)

begin

        if(CaptureDR | ShiftDR)

                Latch<=SelectedInput;

end

always @ (negedge TCK)

begin

        ToNextBSCell<=Latch;

end

always @ (negedge TCK)

begin

        if(UpdateDR)

                ShiftedControl<=ToNextBSCell;

end

assign ToOutputEnable = extest? ShiftedControl : OutputControl;

endmodule       // ControlCell