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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [adv_debug_sys/] [Hardware/] [xilinx_internal_jtag/] [rtl/] [verilog/] [xilinx_internal_jtag.v] - Blame information for rev 21

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1 21 xianfeng
///////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  xilinx_internal_jtag.v                                      ////
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////                                                              ////
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////                                                              ////
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////                                                              ////
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////  Author(s):                                                  ////
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////       Nathan Yawn (nathan.yawn@opencores.org)                ////
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////                                                              ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2008 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
38
//                                                                  //
39
// This file is a wrapper for the various Xilinx internal BSCAN     //
40
// TAP devices.  It is designed to take the place of a separate TAP //
41
// controller in Xilinx systems, to allow a user to access a CPU    //
42
// debug module (such as that of the OR1200) through the FPGA's     //
43
// dedicated JTAG / configuration port.                             //
44
//                                                                  //
45
//////////////////////////////////////////////////////////////////////
46
//
47
// CVS Revision History
48
//
49
// $Log: xilinx_internal_jtag.v,v $
50
// Revision 1.4  2009-12-28 01:15:28  Nathan
51
// Removed incorrect duplicate assignment of capture_dr_o in SPARTAN2 TAP, per bug report from Raul Fajardo.
52
//
53
// Revision 1.3  2009/06/16 02:54:23  Nathan
54
// Changed some signal names for better consistency between different hardware modules.
55
//
56
// Revision 1.2  2009/05/17 20:54:16  Nathan
57
// Changed email address to opencores.org
58
//
59
// Revision 1.1  2008/07/18 20:07:32  Nathan
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// Changed the directory structure to match existing projects.
61
//
62
// Revision 1.4  2008/07/11 08:26:10  Nathan
63
// Ran through dos2unix
64
//
65
// Revision 1.3  2008/07/11 08:25:52  Nathan
66
// Added logic to provide CAPTURE_DR signal when necessary, and to provide a TCK while UPDATE_DR is asserted.  Note that there is no TCK event between SHIFT_DR and UPDATE_DR, and no TCK event between UPDATE_DR and the next CAPTURE_DR; the Xilinx BSCAN devices do not provide it.  Tested successfully with the adv_dbg_if on Virtex-4.
67
//
68
// Revision 1.2  2008/06/09 19:34:14  Nathan
69
// Syntax and functional fixes made after compiling each type of BSCAN module using Xilinx tools.
70
//
71
// Revision 1.1  2008/05/22 19:54:07  Nathan
72
// Initial version
73
//
74
 
75
 
76
`include "xilinx_internal_jtag_options.v"
77
 
78
// Note that the SPARTAN BSCAN controllers have more than one channel.
79
// This implementation always uses channel 1, this is not configurable.
80
// If you want to use another channel, then it is probably because you
81
// want to attach multiple devices to the BSCAN device, which means
82
// you'll be making changes to this file anyway.
83
// Virtex BSCAN devices are instantiated separately for each channel.
84
// To select something other than the default (1), change the parameter
85
// "virtex_jtag_chain".
86
 
87
 
88
module xilinx_internal_jtag (
89
        tck_o,
90
        debug_tdo_i,
91
        tdi_o,
92
        test_logic_reset_o,
93
        run_test_idle_o,
94
        shift_dr_o,
95
        capture_dr_o,
96
        pause_dr_o,
97
        update_dr_o,
98
        debug_select_o
99
);
100
 
101
// May be 1, 2, 3, or 4
102
// Only used for Virtex 4/5 devices
103
parameter virtex_jtag_chain = 1;
104
 
105
input debug_tdo_i;
106
output tck_o;
107
output tdi_o;
108
output test_logic_reset_o;
109
output run_test_idle_o;
110
output shift_dr_o;
111
output capture_dr_o;
112
output pause_dr_o;
113
output update_dr_o;
114
output debug_select_o;
115
 
116
wire debug_tdo_i;
117
wire tck_o;
118
wire drck;
119
wire tdi_o;
120
wire test_logic_reset_o;
121
wire run_test_idle_o;
122
wire shift_dr_o;
123
wire pause_dr_o;
124
wire update_dr_o;
125
wire debug_select_o;
126
 
127
 
128
 
129
`ifdef SPARTAN2
130
 
131
// Note that this version is missing three outputs.
132
// It also does not have a real TCK...DRCK1 is only active when USER1 is selected
133
// AND the TAP is in SHIFT_DR or CAPTURE_DR states...except there's no
134
// capture_dr output. 
135
 
136
reg capture_dr_o;
137
wire update_bscan;
138
reg update_out;
139
 
140
BSCAN_SPARTAN2 BSCAN_SPARTAN2_inst (
141
.DRCK1(drck), // Data register output for USER1 functions
142
.DRCK2(), // Data register output for USER2 functions
143
.RESET(test_logic_reset_o), // Reset output from TAP controller
144
.SEL1(debug_select_o), // USER1 active output
145
.SEL2(), // USER2 active output
146
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
147
.TDI(tdi_o), // TDI output from TAP controller
148
.UPDATE(update_bscan), // UPDATE output from TAP controller
149
.TDO1(debug_tdo_i), // Data input for USER1 function
150
.TDO2( 1'b0 ) // Data input for USER2 function
151
);
152
 
153
assign pause_dr_o = 1'b0;
154
assign run_test_idle_o = 1'b0;
155
 
156
// We get one TCK during capture_dr state (low,high,SHIFT goes high on next DRCK high)
157
// On that negative edge, set capture_dr, and it will get registered on the rising
158
// edge.
159
always @ (negedge tck_o)
160
begin
161
        if(debug_select_o && !shift_dr_o)
162
                capture_dr_o <= 1'b1;
163
        else
164
                capture_dr_o <= 1'b0;
165
end
166
 
167
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
168
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
169
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
170
assign tck_o = (drck & debug_select_o & !update_bscan);
171
 
172
// This will hold the update_dr output so it can be registered on the rising edge
173
// of the clock created above.
174
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
175
begin
176
        if(update_bscan) update_out <= 1'b1;
177
        else if(capture_dr_o) update_out <= 1'b0;
178
        else if(!debug_select_o) update_out <= 1'b0;
179
end
180
 
181
assign update_dr_o = update_out;
182
 
183
`else
184
`ifdef SPARTAN3
185
// Note that this version is missing two outputs.
186
// It also does not have a real TCK...DRCK1 is only active when USER1 is selected.
187
 
188
wire capture_dr_o;
189
wire update_bscan;
190
reg update_out;
191
 
192
BSCAN_SPARTAN3 BSCAN_SPARTAN3_inst (
193
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
194
.DRCK1(drck), // Data register output for USER1 functions
195
.DRCK2(), // Data register output for USER2 functions
196
.RESET(test_logic_reset_o), // Reset output from TAP controller
197
.SEL1(debug_select_o), // USER1 active output
198
.SEL2(), // USER2 active output
199
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
200
.TDI(tdi_o), // TDI output from TAP controller
201
.UPDATE(update_bscan), // UPDATE output from TAP controller
202
.TDO1(debug_tdo_i), // Data input for USER1 function
203
.TDO2(1'b0) // Data input for USER2 function
204
);
205
 
206
assign pause_dr_o = 1'b0;
207
assign run_test_idle_o = 1'b0;
208
 
209
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
210
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
211
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
212
assign tck_o = (drck & debug_select_o & !update_bscan);
213
 
214
// This will hold the update_dr output so it can be registered on the rising edge
215
// of the clock created above.
216
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
217
begin
218
        if(update_bscan) update_out <= 1'b1;
219
        else if(capture_dr_o) update_out <= 1'b0;
220
        else if(!debug_select_o) update_out <= 1'b0;
221
end
222
 
223
assign update_dr_o = update_out;
224
 
225
`else
226
`ifdef SPARTAN3A
227
// Note that this version is missing two outputs.
228
// At least it has a real TCK.
229
 
230
wire capture_dr_o;
231
 
232
BSCAN_SPARTAN3A BSCAN_SPARTAN3A_inst (
233
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
234
.DRCK1(), // Data register output for USER1 functions
235
.DRCK2(), // Data register output for USER2 functions
236
.RESET(test_logic_reset_o), // Reset output from TAP controller
237
.SEL1(debug_select_o), // USER1 active output
238
.SEL2(), // USER2 active output
239
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
240
.TCK(tck_o), // TCK output from TAP controller
241
.TDI(tdi_o), // TDI output from TAP controller
242
.TMS(), // TMS output from TAP controller
243
.UPDATE(update_dr_o), // UPDATE output from TAP controller
244
.TDO1(debug_tdo_i), // Data input for USER1 function
245
.TDO2( 1'b0) // Data input for USER2 function
246
);
247
 
248
assign pause_dr_o = 1'b0;
249
assign run_test_idle_o = 1'b0;
250
 
251
`else
252
`ifdef VIRTEX
253
 
254
// Note that this version is missing three outputs.
255
// It also does not have a real TCK...DRCK1 is only active when USER1 is selected.
256
 
257
reg capture_dr_o;
258
wire update_bscan;
259
reg update_out;
260
 
261
BSCAN_VIRTEX BSCAN_VIRTEX_inst (
262
.DRCK1(drck), // Data register output for USER1 functions
263
.DRCK2(), // Data register output for USER2 functions
264
.RESET(test_logic_reset_o), // Reset output from TAP controller
265
.SEL1(debug_select_o), // USER1 active output
266
.SEL2(), // USER2 active output
267
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
268
.TDI(tdi_o), // TDI output from TAP controller
269
.UPDATE(update_bscan), // UPDATE output from TAP controller
270
.TDO1(debug_tdo_i), // Data input for USER1 function
271
.TDO2( 1'b0) // Data input for USER2 function
272
);
273
 
274
assign pause_dr_o = 1'b0;
275
assign run_test_idle_o = 1'b0;
276
 
277
// We get one TCK during capture_dr state (low,high,SHIFT goes high on next DRCK low)
278
// On that negative edge, set capture_dr, and it will get registered on the rising
279
// edge, then de-asserted on the same edge that SHIFT goes high.
280
always @ (negedge tck_o)
281
begin
282
        if(debug_select_o && !shift_dr_o)
283
                capture_dr_o <= 1'b1;
284
        else
285
                capture_dr_o <= 1'b0;
286
end
287
 
288
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
289
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
290
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
291
assign tck_o = (drck & debug_select_o & !update_bscan);
292
 
293
// This will hold the update_dr output so it can be registered on the rising edge
294
// of the clock created above.
295
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
296
begin
297
        if(update_bscan) update_out <= 1'b1;
298
        else if(capture_dr_o) update_out <= 1'b0;
299
        else if(!debug_select_o) update_out <= 1'b0;
300
end
301
 
302
assign update_dr_o = update_out;
303
 
304
`else
305
`ifdef VIRTEX2
306
 
307
// Note that this version is missing two outputs.
308
// It also does not have a real TCK...DRCK1 is only active when USER1 is selected.
309
 
310
wire capture_dr_o;
311
wire update_bscan;
312
reg update_out;
313
 
314
BSCAN_VIRTEX2 BSCAN_VIRTEX2_inst (
315
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
316
.DRCK1(drck), // Data register output for USER1 functions
317
.DRCK2(), // Data register output for USER2 functions
318
.RESET(test_logic_reset_o), // Reset output from TAP controller
319
.SEL1(debug_select_o), // USER1 active output
320
.SEL2(), // USER2 active output
321
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
322
.TDI(tdi_o), // TDI output from TAP controller
323
.UPDATE(update_bscan), // UPDATE output from TAP controller
324
.TDO1(debug_tdo_i), // Data input for USER1 function
325
.TDO2( 1'b0 ) // Data input for USER2 function
326
);
327
 
328
assign pause_dr_o = 1'b0;
329
assign run_test_idle_o = 1'b0;
330
 
331
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
332
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
333
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
334
assign tck_o = (drck & debug_select_o & !update_bscan);
335
 
336
// This will hold the update_dr output so it can be registered on the rising edge
337
// of the clock created above.
338
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
339
begin
340
        if(update_bscan) update_out <= 1'b1;
341
        else if(capture_dr_o) update_out <= 1'b0;
342
        else if(!debug_select_o) update_out <= 1'b0;
343
end
344
 
345
assign update_dr_o = update_out;
346
 
347
`else
348
`ifdef VIRTEX4
349
// Note that this version is missing two outputs.
350
// It also does not have a real TCK...DRCK is only active when USERn is selected.
351
 
352
wire capture_dr_o;
353
wire update_bscan;
354
reg update_out;
355
 
356
BSCAN_VIRTEX4 #(
357
.JTAG_CHAIN(virtex_jtag_chain)
358
) BSCAN_VIRTEX4_inst (
359
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
360
.DRCK(drck), // Data register output for USER function
361
.RESET(test_logic_reset_o), // Reset output from TAP controller
362
.SEL(debug_select_o), // USER active output
363
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
364
.TDI(tdi_o), // TDI output from TAP controller
365
.UPDATE(update_bscan), // UPDATE output from TAP controller
366
.TDO( debug_tdo_i ) // Data input for USER function
367
);
368
 
369
assign pause_dr_o = 1'b0;
370
assign run_test_idle_o = 1'b0;
371
 
372
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
373
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
374
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
375
assign tck_o = (drck & debug_select_o & !update_bscan);
376
 
377
// This will hold the update_dr output so it can be registered on the rising edge
378
// of the clock created above.
379
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
380
begin
381
        if(update_bscan) update_out <= 1'b1;
382
        else if(capture_dr_o) update_out <= 1'b0;
383
        else if(!debug_select_o) update_out <= 1'b0;
384
end
385
 
386
assign update_dr_o = update_out;
387
 
388
`else
389
`ifdef VIRTEX5
390
// Note that this version is missing two outputs.
391
// It also does not have a real TCK...DRCK is only active when USERn is selected.
392
 
393
wire capture_dr_o;
394
wire update_bscan;
395
reg update_out;
396
 
397
BSCAN_VIRTEX5 #(
398
.JTAG_CHAIN(virtex_jtag_chain)
399
) BSCAN_VIRTEX5_inst (
400
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
401
.DRCK(drck), // Data register output for USER function
402
.RESET(test_logic_reset), // Reset output from TAP controller
403
.SEL(debug_select_o), // USER active output
404
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
405
.TDI(tdi_o), // TDI output from TAP controller
406
.UPDATE(update_bscan), // UPDATE output from TAP controller
407
.TDO(debug_tdo_i) // Data input for USER function
408
);
409
 
410
assign pause_dr_o = 1'b0;
411
assign run_test_idle_o = 1'b0;
412
 
413
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
414
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
415
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
416
assign tck_o = (drck & debug_select_o & !update_bscan);
417
 
418
// This will hold the update_dr output so it can be registered on the rising edge
419
// of the clock created above.
420
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
421
begin
422
        if(update_bscan) update_out <= 1'b1;
423
        else if(capture_dr_o) update_out <= 1'b0;
424
        else if(!debug_select_o) update_out <= 1'b0;
425
end
426
 
427
assign update_dr_o = update_out;
428
 
429
 
430
`endif
431
`endif
432
`endif
433
`endif
434
`endif
435
`endif
436
`endif
437
 
438
endmodule

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