URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [adv_debug_sys/] [Hardware/] [xilinx_internal_jtag/] [rtl/] [verilog/] [xilinx_internal_jtag_options.v] - Blame information for rev 21

Details | Compare with Previous | View Log


 
 
// Xilinx has a different HDL entity for the internal JTAG in each of these.
// How thoughtful.
 
//`define SPARTAN2
//`define SPARTAN3  // This is also used for SPARTAN 3E devices
//`define SPARTAN3A
//`define VIRTEX
//`define VIRTEX2  // Also used for the VIRTEX 2P
`define VIRTEX4
//`define VIRTEX5

Line No.	Rev	Author	Line
1	21	xianfeng
2
3			`// Xilinx has a different HDL entity for the internal JTAG in each of these.`
4			`// How thoughtful.`
5
6			//`define SPARTAN2
7			//`define SPARTAN3 // This is also used for SPARTAN 3E devices
8			//`define SPARTAN3A
9			//`define VIRTEX
10			//`define VIRTEX2 // Also used for the VIRTEX 2P
11			`define VIRTEX4
12			//`define VIRTEX5

Browse

Tools

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [adv_debug_sys/] [Hardware/] [xilinx_internal_jtag/] [rtl/] [verilog/] [xilinx_internal_jtag_options.v] - Blame information for rev 21