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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [altera_ddr_ctrl/] [alt_mem_phy_defines.v] - Blame information for rev 12

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//#mw_delete ("")
/* Legal Notice: (C)2006 Altera Corporation. All rights reserved.  Your
   use of Altera Corporation's design tools, logic functions and other
   software and tools, and its AMPP partner logic functions, and any
   output files any of the foregoing (including device programming or
   simulation files), and any associated documentation or information are
   expressly subject to the terms and conditions of the Altera Program
   License Subscription Agreement or other applicable license agreement,
   including, without limitation, that your use is for the sole purpose
   of programming logic devices manufactured by Altera and sold by Altera
   or its authorized distributors.  Please refer to the applicable
   agreement for further details. */
 
 
/*-----------------------------------------------------------------------------
  Title           : Defines
 
  File:  $RCSfile : alt_mem_phy_defines.v,v $
 
  Last Modified   : $Date: 2009/04/01 $
 
  Revision        : $Revision: #1 $
 
  Abstract        : Defines file for the ALTMEMPHY.  This provides one file in
                    which all constant definitions can be contained, thus
                    ensuring continuity of naming and correct port widths
                    between blocks.
-----------------------------------------------------------------------------*/
//#end
 
// Set timescale to prevent warnings in simulation.
`timescale 1 ps / 1 ps
 
// These defines are constant values used in the PHY RTL :
 
// Check to see whether alt_mem_phy_defines is already defined.  If it is,
// then this define file has already been loaded, and so it is not necessary
// to set the defines.  Otherwise set the defines.
 
`ifdef ALT_MEM_PHY_DEFINES
`else
 
`define ALT_MEM_PHY_DEFINES
 
// Address and command defines :
`define ADC_NUM_PIN_GROUPS  8
 
`define ADC_ADDR_PERIOD_SEL  0
`define ADC_BA_PERIOD_SEL    1
`define ADC_CAS_N_PERIOD_SEL 2
`define ADC_CKE_PERIOD_SEL   3
`define ADC_ODT_PERIOD_SEL   4
`define ADC_RAS_N_PERIOD_SEL 5
`define ADC_WE_N_PERIOD_SEL  6
`define ADC_CS_N_PERIOD_SEL  7
 
// Clk and reset defines :
 
// PLL reconfiguration constants :
 
`define CLK_PLL_STEP_FORWARD 9'b000000011
`define CLK_PLL_STEP_BACK    9'b000000001
`define CLK_PLL_STEP_CANCEL  9'b000000000
 
`define CLK_PLL_RECONFIG_SELECT_PHASE_STEP 3'h2
`define CLK_PLL_INITIALISED   1'b1
`define CLK_PLL_UNINITIALISED 1'b0
 
 
`define CLK_PLL_RECONFIG_FSM_WIDTH               3
`define CLK_PLL_RECONFIG_IDLE                 3'h0
`define CLK_PLL_CLEAR_OLD_PHASE               3'h1
`define CLK_PLL_CLEAR_OLD_PHASE_WAIT_ON_BUSY  3'h2
`define CLK_PLL_SET_NEW_DIR                   3'h3
`define CLK_PLL_SET_NEW_DIR_WAIT_ON_BUSY      3'h4
`define CLK_PLL_REQUEST_UPDATE                3'h5
`define CLK_PLL_REQUEST_UPDATE_WAIT_ON_BUSY   3'h6
`define CLK_PLL_ILLEGAL_STATE                 3'h7
 
 
 
// Postamble defines
`define POA_OVERRIDE_VAL 2'b11
`define POA_OVERRIDE_VAL_FULL_RATE 1'b1
 
 
// Mimic path state machine defines
`define        MIMIC_FSM_WIDTH 3
`define        MIMIC_IDLE      3'b000
`define        MIMIC_SAMPLE    3'b001
`define        MIMIC_SEND      3'b010
`define        MIMIC_SEND1     3'b011
`define        MIMIC_SEND2     3'b100
 
 
// SIII DDR2/3 DQS Config atom defines :
 
`define     DQSCONFIG_DQS_OUTPUT_PHASE_SETTING_WIDTH      4
`define     DQSCONFIG_DQS_BUSOUT_DELAY_SETTING_WIDTH      4
`define     DQSCONFIG_DQS_INPUT_PHASE_SETTING_WIDTH       3
`define     DQSCONFIG_DQS_EN_CTRL_PHASE_SETTING_WIDTH     4
`define     DQSCONFIG_DQS_EN_DELAY_SETTING_WIDTH          3
`define     DQSCONFIG_DQS_OCT_DELAY_SETTING1_WIDTH        4
`define     DQSCONFIG_DQS_OCT_DELAY_SETTING2_WIDTH        3
 
`define     DQSCONFIG_RESYNC_IP_PHASE_SETTING_WIDTH       4
`define     DQSCONFIG_DQ_OP_PHASE_SETTING_WIDTH           4
 
// SIII DDR2/3 IO Config atom defines :
`define     IOCONFIG_DQ_PAD_TO_IP_REG_DELAY_SETTING_WIDTH 4
`define     IOCONFIG_DQ_OUTPUT_DELAY_SETTING1_WIDTH       4
`define     IOCONFIG_DQ_OUTPUT_DELAY_SETTING2_WIDTH       3
 
`define     OCT_SERIES_TERM_CONTROL_WIDTH                 14
`define     OCT_PARALLEL_TERM_CONTROL_WIDTH               14
 
`define     SIII_ATOM_DELAY_DQ_T9                         0
`define     SIII_ATOM_DELAY_DQ_T10                        0
`define     SIII_ATOM_DELAY_DQOE_T9                       0
`define     SIII_ATOM_DELAY_DQOE_T10                      0
`define     SIII_ATOM_DELAY_OCT_T9                        0
`define     SIII_ATOM_DELAY_OCT_T10                       0
 
`define     SIII_ATOM_DELAY_DQ_T1                         0
 
`define     SIII_ATOM_DELAY_DQS_T9                        0
`define     SIII_ATOM_DELAY_DQS_T10                       0
 
`define     SIII_ATOM_DELAY_DQSOE_T9                      0
`define     SIII_ATOM_DELAY_DQSOE_T10                     0
 
`define     SIII_ATOM_DELAY_DQSOCT_T9                     0
`define     SIII_ATOM_DELAY_DQSOCT_T10                    0
 
`define     SIII_ATOM_DELAY_DQS_T7                        0
`define     SIII_ATOM_DELAY_DQSN_T7                       0
 
`define     SIII_ATOM_DELAY_DQS_T11                       0
 
`define     SIII_ATOM_DELAY_DM_T9                         0
`define     SIII_ATOM_DELAY_DM_T10                        0
 
 
`endif

Line No.	Rev	Author	Line
1	12	xianfeng	`//#mw_delete ("")`
2			`/* Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your`
3			`use of Altera Corporation's design tools, logic functions and other`
4			`software and tools, and its AMPP partner logic functions, and any`
5			`output files any of the foregoing (including device programming or`
6			`simulation files), and any associated documentation or information are`
7			`expressly subject to the terms and conditions of the Altera Program`
8			`License Subscription Agreement or other applicable license agreement,`
9			`including, without limitation, that your use is for the sole purpose`
10			`of programming logic devices manufactured by Altera and sold by Altera`
11			`or its authorized distributors. Please refer to the applicable`
12			`agreement for further details. */`
13
14
15			`/*-----------------------------------------------------------------------------`
16			`Title : Defines`
17
18			`File: $RCSfile : alt_mem_phy_defines.v,v $`
19
20			`Last Modified : $Date: 2009/04/01 $`
21
22			`Revision : $Revision: #1 $`
23
24			`Abstract : Defines file for the ALTMEMPHY. This provides one file in`
25			`which all constant definitions can be contained, thus`
26			`ensuring continuity of naming and correct port widths`
27			`between blocks.`
28			`-----------------------------------------------------------------------------*/`
29			`//#end`
30
31			`// Set timescale to prevent warnings in simulation.`
32			`timescale 1 ps / 1 ps
33
34			`// These defines are constant values used in the PHY RTL :`
35
36			`// Check to see whether alt_mem_phy_defines is already defined. If it is,`
37			`// then this define file has already been loaded, and so it is not necessary`
38			`// to set the defines. Otherwise set the defines.`
39
40			`ifdef ALT_MEM_PHY_DEFINES
41			`else
42
43			`define ALT_MEM_PHY_DEFINES
44
45			`// Address and command defines :`
46			`define ADC_NUM_PIN_GROUPS 8
47
48			`define ADC_ADDR_PERIOD_SEL 0
49			`define ADC_BA_PERIOD_SEL 1
50			`define ADC_CAS_N_PERIOD_SEL 2
51			`define ADC_CKE_PERIOD_SEL 3
52			`define ADC_ODT_PERIOD_SEL 4
53			`define ADC_RAS_N_PERIOD_SEL 5
54			`define ADC_WE_N_PERIOD_SEL 6
55			`define ADC_CS_N_PERIOD_SEL 7
56
57			`// Clk and reset defines :`
58
59			`// PLL reconfiguration constants :`
60
61			`define CLK_PLL_STEP_FORWARD 9'b000000011
62			`define CLK_PLL_STEP_BACK 9'b000000001
63			`define CLK_PLL_STEP_CANCEL 9'b000000000
64
65			`define CLK_PLL_RECONFIG_SELECT_PHASE_STEP 3'h2
66			`define CLK_PLL_INITIALISED 1'b1
67			`define CLK_PLL_UNINITIALISED 1'b0
68
69
70			`define CLK_PLL_RECONFIG_FSM_WIDTH 3
71			`define CLK_PLL_RECONFIG_IDLE 3'h0
72			`define CLK_PLL_CLEAR_OLD_PHASE 3'h1
73			`define CLK_PLL_CLEAR_OLD_PHASE_WAIT_ON_BUSY 3'h2
74			`define CLK_PLL_SET_NEW_DIR 3'h3
75			`define CLK_PLL_SET_NEW_DIR_WAIT_ON_BUSY 3'h4
76			`define CLK_PLL_REQUEST_UPDATE 3'h5
77			`define CLK_PLL_REQUEST_UPDATE_WAIT_ON_BUSY 3'h6
78			`define CLK_PLL_ILLEGAL_STATE 3'h7
79
80
81
82			`// Postamble defines`
83			`define POA_OVERRIDE_VAL 2'b11
84			`define POA_OVERRIDE_VAL_FULL_RATE 1'b1
85
86
87			`// Mimic path state machine defines`
88			`define MIMIC_FSM_WIDTH 3
89			`define MIMIC_IDLE 3'b000
90			`define MIMIC_SAMPLE 3'b001
91			`define MIMIC_SEND 3'b010
92			`define MIMIC_SEND1 3'b011
93			`define MIMIC_SEND2 3'b100
94
95
96			`// SIII DDR2/3 DQS Config atom defines :`
97
98			`define DQSCONFIG_DQS_OUTPUT_PHASE_SETTING_WIDTH 4
99			`define DQSCONFIG_DQS_BUSOUT_DELAY_SETTING_WIDTH 4
100			`define DQSCONFIG_DQS_INPUT_PHASE_SETTING_WIDTH 3
101			`define DQSCONFIG_DQS_EN_CTRL_PHASE_SETTING_WIDTH 4
102			`define DQSCONFIG_DQS_EN_DELAY_SETTING_WIDTH 3
103			`define DQSCONFIG_DQS_OCT_DELAY_SETTING1_WIDTH 4
104			`define DQSCONFIG_DQS_OCT_DELAY_SETTING2_WIDTH 3
105
106			`define DQSCONFIG_RESYNC_IP_PHASE_SETTING_WIDTH 4
107			`define DQSCONFIG_DQ_OP_PHASE_SETTING_WIDTH 4
108
109			`// SIII DDR2/3 IO Config atom defines :`
110			`define IOCONFIG_DQ_PAD_TO_IP_REG_DELAY_SETTING_WIDTH 4
111			`define IOCONFIG_DQ_OUTPUT_DELAY_SETTING1_WIDTH 4
112			`define IOCONFIG_DQ_OUTPUT_DELAY_SETTING2_WIDTH 3
113
114			`define OCT_SERIES_TERM_CONTROL_WIDTH 14
115			`define OCT_PARALLEL_TERM_CONTROL_WIDTH 14
116
117			`define SIII_ATOM_DELAY_DQ_T9 0
118			`define SIII_ATOM_DELAY_DQ_T10 0
119			`define SIII_ATOM_DELAY_DQOE_T9 0
120			`define SIII_ATOM_DELAY_DQOE_T10 0
121			`define SIII_ATOM_DELAY_OCT_T9 0
122			`define SIII_ATOM_DELAY_OCT_T10 0
123
124			`define SIII_ATOM_DELAY_DQ_T1 0
125
126			`define SIII_ATOM_DELAY_DQS_T9 0
127			`define SIII_ATOM_DELAY_DQS_T10 0
128
129			`define SIII_ATOM_DELAY_DQSOE_T9 0
130			`define SIII_ATOM_DELAY_DQSOE_T10 0
131
132			`define SIII_ATOM_DELAY_DQSOCT_T9 0
133			`define SIII_ATOM_DELAY_DQSOCT_T10 0
134
135			`define SIII_ATOM_DELAY_DQS_T7 0
136			`define SIII_ATOM_DELAY_DQSN_T7 0
137
138			`define SIII_ATOM_DELAY_DQS_T11 0
139
140			`define SIII_ATOM_DELAY_DM_T9 0
141			`define SIII_ATOM_DELAY_DM_T10 0
142
143
144			`endif

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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [altera_ddr_ctrl/] [alt_mem_phy_defines.v] - Blame information for rev 12