| 1 |
12 |
xianfeng |
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN">
|
| 2 |
|
|
<HTML>
|
| 3 |
|
|
<HEAD>
|
| 4 |
|
|
<STYLE type="text/css">
|
| 5 |
|
|
A.h:hover { color: "#FF0000"; }
|
| 6 |
|
|
A.menu:link { text-decoration: none}
|
| 7 |
|
|
A.menu:visited{ text-decoration: none}
|
| 8 |
|
|
A.menu:hover {color: #EE9B06;}
|
| 9 |
|
|
A.submenu:link { text-decoration: none;}
|
| 10 |
|
|
A.submenu:visited { text-decoration: none}
|
| 11 |
|
|
A.submenu:hover {color: #EE9B06;}
|
| 12 |
|
|
div.category { border-bottom: 5px, solid, black; }
|
| 13 |
|
|
br.submenu { line-height: 1em;}
|
| 14 |
|
|
br.submenu { line-height: 7px;}
|
| 15 |
|
|
BODY, H1, H2, H3, H4, TD, TH, UL, OL, LI, P, DD, DT, DL, INPUT, SELECT, SPAN { font-family : SansSerif, Verdana, Helvetica, Arial, San-sarif; }
|
| 16 |
|
|
BODY { background-color : #e0e0e0; }
|
| 17 |
|
|
TD, UL, OL, LI, P, DD, DT, DL, SPAN { font-size: 11pt; color : black; }
|
| 18 |
|
|
BLOCKQUOTE { font-size: 10pt; color : #000099; }
|
| 19 |
|
|
TH { font-size : 11pt; font-weight : bold; font-style : normal; color : black; }
|
| 20 |
|
|
H1 { font-size : 18pt; color : black; }
|
| 21 |
|
|
H2 { font-size : 14pt; color : black; }
|
| 22 |
|
|
H3 { font-size : 12pt; color : black; }
|
| 23 |
|
|
H4 { font-size : 11pt; font-weight : bold; color : black; }
|
| 24 |
|
|
|
| 25 |
|
|
</style></HEAD><BODY align="left" style='background-color: #ffffff;'><DIV align="left"><TABLE width="95%" border=0 cellpadding=2><TR><TD><TABLE cellpadding=2 border=0 ><TR><WIZARD></WIZARD><TD><H1>Generation Report - DDR SDRAM High Performance Controller v9.0</H1></TD></TR></TABLE></TD></TR><TR><TD><TABLE cellpadding=2 border=1 width="60%"><TR><TD><B>Entity Name</B></TD><TD>altera_ddr_controller_phy</TD></TR><TR><TD><B>Variation Name</B></TD><TD>altera_ddr</TD></TR><TR><TD><B>Variation HDL</B></TD><TD>Verilog HDL</TD></TR><TR><TD><B>Output Directory</B></TD><TD>/opt/workspace/xzeng/esig/trunk/or1k_soc/rtl/altera_ddr_ctrl</TD></TR></TABLE></TD></TR><TR><TD><h2>File Summary</h2>The MegaWizard interface is creating the following files in the output directory:</TD></TR><TR><TD><TABLE cellspacing=2 cellpadding=2 border=1 width="100%"><TR align="left"><TH align="left" align="top" width="25%"><B>File</B></TH><TH align="left"><B>Description</B></TH></TR><TR><TD>altera_ddr.v</TD><TD>A MegaCore<small><sup>®</sup></small> function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.</TD></TR><TR><TD>altera_ddr_bb.v</TD><TD>Verilog HDL black-box file for the MegaCore function variation. Use this file when using a third-party EDA tool to synthesize your design.</TD></TR><TR><TD>altera_ddr.bsf</TD><TD>Quartus<small><sup>®</sup></small> II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor.</TD></TR><TR><TD>altera_ddr_auk_ddr_hp_controller_wrapper.vo</TD><TD>Verilog HDL IP functional simulation model</TD></TR><TR><TD>altera_ddr.qip</TD><TD>Contains Quartus II project information for your MegaCore function variation.</TD></TR><TR><TD>altera_ddr.html</TD><TD>The MegaCore function report file.</TD></TR><TR><TD>auk_ddr_hp_controller.ocp</TD><TD>An OpenCore Plus file, for time limited or tethered hardware evaluation.</TD></TR><TR><TD>auk_ddr_hp_controller.vhd</TD><TD>Encrypted source code for the controller.</TD></TR><TR><TD>altera_ddr_example_driver.v</TD><TD>Example self-checking test generator that matches your variation.</TD></TR><TR><TD>altera_ddr_example_top.v</TD><TD>Example top level design file that you should set as your Quartus II project top level. Instantiates the example driver and the controller.</TD></TR><TR><TD>altera_ddr_example_top.sdc</TD><TD>Example Synopsys Design Constraints file for paths in the example top level.</TD></TR><TR><TD>altera_ddr_advisor.ipa</TD><TD>IP Advisor file that matches your variation. Used by the IP Advisor feature in the Quartus II software.</TD></TR><TR><TD>altera_ddr_ex_lfsr8.v</TD><TD>Example linear feedback shift register that is used to generate the pseudo-random test data for the example driver.</TD></TR><TR><TD>testbench | altera_ddr_example_top_tb.v</TD><TD>Example testbench that instantiates the example top level design file and the example memory model.</TD></TR><TR><TD>testbench | altera_ddr_mem_model.v</TD><TD>A simple example memory model that matches your variation.</TD></TR><TR><TD>testbench | altera_ddr_full_mem_model.v</TD><TD>Memory model that allocates memory for all available addresses.</TD></TR><TR><TD>altera_ddr_pin_assignments.tcl</TD><TD>TCL script</TD></TR></TABLE></TD></TR><TR><TD><h2>MegaCore Function Variation File Ports</h2><TABLE border=1 cellpadding=2 cellspacing=0 width="75%"><TR align="left"><TH align="left"><B>Name</B></TH><TH align="left"><B>Direction</B></TH><TH align="left"><B>Width</B></TH></TR><TR><TD>local_address</TD><TD>INPUT</TD><TD>23</TD></TR><TR><TD>local_write_req</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>local_read_req</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>local_burstbegin</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>local_ready</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>local_rdata</TD><TD>OUTPUT</TD><TD>32</TD></TR><TR><TD>local_rdata_valid</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>local_wdata</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>local_be</TD><TD>INPUT</TD><TD>4</TD></TR><TR><TD>local_size</TD><TD>INPUT</TD><TD>2</TD></TR><TR><TD>reset_request_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_clk</TD><TD>BIDIR</TD><TD>1</TD></TR><TR><TD>mem_clk_n</TD><TD>BIDIR</TD><TD>1</TD></TR><TR><TD>mem_cs_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_cke</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_addr</TD><TD>OUTPUT</TD><TD>13</TD></TR><TR><TD>mem_ba</TD><TD>OUTPUT</TD><TD>2</TD></TR><TR><TD>mem_ras_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_cas_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_we_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_dq</TD><TD>BIDIR</TD><TD>16</TD></TR><TR><TD>mem_dqs</TD><TD>BIDIR</TD><TD>2</TD></TR><TR><TD>mem_dm</TD><TD>OUTPUT</TD><TD>2</TD></TR><TR><TD>local_refresh_ack</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>local_wdata_req</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>local_init_done</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>reset_phy_clk_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>global_reset_n</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>pll_ref_clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>phy_clk</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>aux_full_rate_clk</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>aux_half_rate_clk</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>soft_reset_n</TD><TD>INPUT</TD><TD>1</TD></TR></TABLE></TD></TR></TD></TR></TABLE></DIV></BODY></HTML>
|
