OpenCores
URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [altera_ddr_ctrl/] [altera_ddr.v] - Blame information for rev 12

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 12 xianfeng 
// megafunction wizard: %DDR High Performance Controller v9.0%
2 
// GENERATION: XML
3 
 
4 
// ============================================================
5 
// Megafunction Name(s):
6 
//                      altera_ddr_controller_phy
7 
// ============================================================
8 
// Generated by DDR High Performance Controller 9.0 [Altera, IP Toolbench 1.3.0 Build 235]
9 
// ************************************************************
10 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
11 
// ************************************************************
12 
// Copyright (C) 1991-2009 Altera Corporation
13 
// Any megafunction design, and related net list (encrypted or decrypted),
14 
// support information, device programming or simulation file, and any other
15 
// associated documentation or information provided by Altera or a partner
16 
// under Altera's Megafunction Partnership Program may be used only to
17 
// program PLD devices (but not masked PLD devices) from Altera.  Any other
18 
// use of such megafunction design, net list, support information, device
19 
// programming or simulation file, or any other related documentation or
20 
// information is prohibited for any other purpose, including, but not
21 
// limited to modification, reverse engineering, de-compiling, or use with
22 
// any other silicon devices, unless such use is explicitly licensed under
23 
// a separate agreement with Altera or a megafunction partner.  Title to
24 
// the intellectual property, including patents, copyrights, trademarks,
25 
// trade secrets, or maskworks, embodied in any such megafunction design,
26 
// net list, support information, device programming or simulation file, or
27 
// any other related documentation or information provided by Altera or a
28 
// megafunction partner, remains with Altera, the megafunction partner, or
29 
// their respective licensors.  No other licenses, including any licenses
30 
// needed under any third party's intellectual property, are provided herein.
31 
 
32 
 
33 
module altera_ddr (
34 
        local_address,
35 
        local_write_req,
36 
        local_read_req,
37 
        local_burstbegin,
38 
        local_wdata,
39 
        local_be,
40 
        local_size,
41 
        global_reset_n,
42 
        pll_ref_clk,
43 
        soft_reset_n,
44 
        local_ready,
45 
        local_rdata,
46 
        local_rdata_valid,
47 
        reset_request_n,
48 
        mem_cs_n,
49 
        mem_cke,
50 
        mem_addr,
51 
        mem_ba,
52 
        mem_ras_n,
53 
        mem_cas_n,
54 
        mem_we_n,
55 
        mem_dm,
56 
        local_refresh_ack,
57 
        local_wdata_req,
58 
        local_init_done,
59 
        reset_phy_clk_n,
60 
        phy_clk,
61 
        aux_full_rate_clk,
62 
        aux_half_rate_clk,
63 
        mem_clk,
64 
        mem_clk_n,
65 
        mem_dq,
66 
        mem_dqs);
67 
 
68 
 
69 
        input   [22:0]   local_address;
70 
        input           local_write_req;
71 
        input           local_read_req;
72 
        input           local_burstbegin;
73 
        input   [31:0]   local_wdata;
74 
        input   [3:0]    local_be;
75 
        input   [1:0]    local_size;
76 
        input           global_reset_n;
77 
        input           pll_ref_clk;
78 
        input           soft_reset_n;
79 
        output          local_ready;
80 
        output  [31:0]   local_rdata;
81 
        output          local_rdata_valid;
82 
        output          reset_request_n;
83 
        output  [0:0]     mem_cs_n;
84 
        output  [0:0]     mem_cke;
85 
        output  [12:0]   mem_addr;
86 
        output  [1:0]    mem_ba;
87 
        output          mem_ras_n;
88 
        output          mem_cas_n;
89 
        output          mem_we_n;
90 
        output  [1:0]    mem_dm;
91 
        output          local_refresh_ack;
92 
        output          local_wdata_req;
93 
        output          local_init_done;
94 
        output          reset_phy_clk_n;
95 
        output          phy_clk;
96 
        output          aux_full_rate_clk;
97 
        output          aux_half_rate_clk;
98 
        inout   [0:0]     mem_clk;
99 
        inout   [0:0]     mem_clk_n;
100 
        inout   [15:0]   mem_dq;
101 
        inout   [1:0]    mem_dqs;
102 
 
103 
        wire signal_wire0 = 1'b0;
104 
        wire [13:0] signal_wire1 = 14'b0;
105 
        wire [13:0] signal_wire2 = 14'b0;
106 
        wire [5:0] signal_wire3 = 6'b0;
107 
        wire [5:0] signal_wire4 = 6'b0;
108 
        wire signal_wire5 = 1'b0;
109 
        wire signal_wire6 = 1'b0;
110 
        wire signal_wire7 = 1'b0;
111 
        wire [3:0] signal_wire8 = 4'b0;
112 
        wire [2:0] signal_wire9 = 3'b0;
113 
        wire signal_wire10 = 1'b0;
114 
        wire [8:0] signal_wire11 = 9'b0;
115 
        wire [3:0] signal_wire12 = 4'b0;
116 
        wire signal_wire13 = 1'b0;
117 
        wire signal_wire14 = 1'b0;
118 
        wire signal_wire15 = 1'b0;
119 
        wire signal_wire16 = 1'b0;
120 
        wire signal_wire17 = 1'b0;
121 
        wire signal_wire18 = 1'b0;
122 
 
123 
        altera_ddr_controller_phy       altera_ddr_controller_phy_inst(
124 
                .local_address(local_address),
125 
                .local_write_req(local_write_req),
126 
                .local_read_req(local_read_req),
127 
                .local_burstbegin(local_burstbegin),
128 
                .local_wdata(local_wdata),
129 
                .local_be(local_be),
130 
                .local_size(local_size),
131 
                .local_refresh_req(signal_wire0),
132 
                .oct_ctl_rs_value(signal_wire1),
133 
                .oct_ctl_rt_value(signal_wire2),
134 
                .dqs_delay_ctrl_import(signal_wire3),
135 
                .dqs_offset_delay_ctrl(signal_wire4),
136 
                .pll_reconfig_write_param(signal_wire5),
137 
                .pll_reconfig_read_param(signal_wire6),
138 
                .pll_reconfig(signal_wire7),
139 
                .pll_reconfig_counter_type(signal_wire8),
140 
                .pll_reconfig_counter_param(signal_wire9),
141 
                .pll_reconfig_soft_reset_en_n(signal_wire10),
142 
                .pll_reconfig_data_in(signal_wire11),
143 
                .pll_phasecounterselect(signal_wire12),
144 
                .pll_phaseupdown(signal_wire13),
145 
                .pll_phasestep(signal_wire14),
146 
                .pll_reconfig_enable(signal_wire15),
147 
                .global_reset_n(global_reset_n),
148 
                .local_autopch_req(signal_wire16),
149 
                .local_powerdn_req(signal_wire17),
150 
                .local_self_rfsh_req(signal_wire18),
151 
                .pll_ref_clk(pll_ref_clk),
152 
                .soft_reset_n(soft_reset_n),
153 
                .local_ready(local_ready),
154 
                .local_rdata(local_rdata),
155 
                .local_rdata_valid(local_rdata_valid),
156 
                .reset_request_n(reset_request_n),
157 
                .mem_odt(),
158 
                .mem_cs_n(mem_cs_n),
159 
                .mem_cke(mem_cke),
160 
                .mem_addr(mem_addr),
161 
                .mem_ba(mem_ba),
162 
                .mem_ras_n(mem_ras_n),
163 
                .mem_cas_n(mem_cas_n),
164 
                .mem_we_n(mem_we_n),
165 
                .mem_dm(mem_dm),
166 
                .local_rdata_error(),
167 
                .local_refresh_ack(local_refresh_ack),
168 
                .local_wdata_req(local_wdata_req),
169 
                .local_init_done(local_init_done),
170 
                .reset_phy_clk_n(reset_phy_clk_n),
171 
                .mem_reset_n(),
172 
                .dll_reference_clk(),
173 
                .dqs_delay_ctrl_export(),
174 
                .pll_reconfig_busy(),
175 
                .pll_reconfig_clk(),
176 
                .pll_reconfig_reset(),
177 
                .pll_reconfig_data_out(),
178 
                .pll_phase_done(),
179 
                .aux_scan_clk_reset_n(),
180 
                .aux_scan_clk(),
181 
                .local_powerdn_ack(),
182 
                .local_self_rfsh_ack(),
183 
                .phy_clk(phy_clk),
184 
                .aux_full_rate_clk(aux_full_rate_clk),
185 
                .aux_half_rate_clk(aux_half_rate_clk),
186 
                .mem_clk(mem_clk),
187 
                .mem_clk_n(mem_clk_n),
188 
                .mem_dq(mem_dq),
189 
                .mem_dqs(mem_dqs),
190 
                .mem_dqsn());
191 
endmodule
192 
 
193 
// =========================================================
194 
// DDR High Performance Controller Wizard Data
195 
// ===============================
196 
// DO NOT EDIT FOLLOWING DATA
197 
// @Altera, IP Toolbench@
198 
// Warning: If you modify this section, DDR High Performance Controller Wizard may not be able to reproduce your chosen configuration.
199 
//
200 
// Retrieval info: <?xml version="1.0"?>
201 
// Retrieval info: <MEGACORE title="DDR SDRAM High Performance Controller"  version="9.0"  build="235"  iptb_version="1.3.0 Build 235"  format_version="120" >
202 
// Retrieval info:  <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.DDRControllerMVCModel"  active_core="altera_ddr_controller_phy" >
203 
// Retrieval info:   <STATIC_SECTION>
204 
// Retrieval info:    <PRIVATES>
205 
// Retrieval info:     <NAMESPACE name = "parameterization">
206 
// Retrieval info:      <PRIVATE name = "pipeline_commands" value="false"  type="STRING"  enable="1" />
207 
// Retrieval info:      <PRIVATE name = "debug_en" value="false"  type="STRING"  enable="1" />
208 
// Retrieval info:      <PRIVATE name = "export_debug_port" value="false"  type="STRING"  enable="1" />
209 
// Retrieval info:      <PRIVATE name = "use_generated_memory_model" value="true"  type="STRING"  enable="1" />
210 
// Retrieval info:      <PRIVATE name = "dedicated_memory_clk_phase_label" value="Dedicated memory clock phase:"  type="STRING"  enable="1" />
211 
// Retrieval info:      <PRIVATE name = "mem_if_clk_mhz" value="150.0"  type="STRING"  enable="1" />
212 
// Retrieval info:      <PRIVATE name = "quartus_project_exists" value="true"  type="STRING"  enable="1" />
213 
// Retrieval info:      <PRIVATE name = "local_if_drate" value="Full"  type="STRING"  enable="1" />
214 
// Retrieval info:      <PRIVATE name = "enable_v72_rsu" value="false"  type="STRING"  enable="1" />
215 
// Retrieval info:      <PRIVATE name = "local_if_clk_mhz_label" value="(150.0 MHz)"  type="STRING"  enable="1" />
216 
// Retrieval info:      <PRIVATE name = "new_variant" value="false"  type="STRING"  enable="1" />
217 
// Retrieval info:      <PRIVATE name = "mem_if_memtype" value="DDR SDRAM"  type="STRING"  enable="1" />
218 
// Retrieval info:      <PRIVATE name = "pll_ref_clk_mhz" value="50.0"  type="STRING"  enable="1" />
219 
// Retrieval info:      <PRIVATE name = "mem_if_clk_ps_label" value="(6667 ps)"  type="STRING"  enable="1" />
220 
// Retrieval info:      <PRIVATE name = "family" value="Cyclone III"  type="STRING"  enable="1" />
221 
// Retrieval info:      <PRIVATE name = "project_family" value="Cyclone III"  type="STRING"  enable="1" />
222 
// Retrieval info:      <PRIVATE name = "speed_grade" value="6"  type="STRING"  enable="1" />
223 
// Retrieval info:      <PRIVATE name = "dedicated_memory_clk_phase" value="0"  type="STRING"  enable="1" />
224 
// Retrieval info:      <PRIVATE name = "pll_ref_clk_ps_label" value="(20000 ps)"  type="STRING"  enable="1" />
225 
// Retrieval info:      <PRIVATE name = "avalon_burst_length" value="1"  type="STRING"  enable="1" />
226 
// Retrieval info:      <PRIVATE name = "WIDTH_RATIO" value="4"  type="STRING"  enable="1" />
227 
// Retrieval info:      <PRIVATE name = "mem_if_pchaddr_bit" value="10"  type="STRING"  enable="1" />
228 
// Retrieval info:      <PRIVATE name = "mem_if_clk_pair_count" value="1"  type="STRING"  enable="1" />
229 
// Retrieval info:      <PRIVATE name = "vendor" value="Other"  type="STRING"  enable="1" />
230 
// Retrieval info:      <PRIVATE name = "chip_or_dimm" value="Discrete Device"  type="STRING"  enable="1" />
231 
// Retrieval info:      <PRIVATE name = "mem_fmax" value="200.0"  type="STRING"  enable="1" />
232 
// Retrieval info:      <PRIVATE name = "mem_if_cs_per_dimm" value="1"  type="STRING"  enable="1" />
233 
// Retrieval info:      <PRIVATE name = "pre_latency_label" value="Fix read latency at:"  type="STRING"  enable="1" />
234 
// Retrieval info:      <PRIVATE name = "dedicated_memory_clk_en" value="false"  type="STRING"  enable="1" />
235 
// Retrieval info:      <PRIVATE name = "mirror_addressing" value="0"  type="STRING"  enable="1" />
236 
// Retrieval info:      <PRIVATE name = "mem_if_bankaddr_width" value="2"  type="STRING"  enable="1" />
237 
// Retrieval info:      <PRIVATE name = "mem_if_preset_rlat" value="0"  type="STRING"  enable="1" />
238 
// Retrieval info:      <PRIVATE name = "post_latency_label" value="cycles (0 cycles=minimum latency, non-deterministic)"  type="STRING"  enable="1" />
239 
// Retrieval info:      <PRIVATE name = "mem_dyn_deskew_en" value="false"  type="STRING"  enable="1" />
240 
// Retrieval info:      <PRIVATE name = "mem_if_cs_width" value="1"  type="STRING"  enable="1" />
241 
// Retrieval info:      <PRIVATE name = "mem_if_rowaddr_width" value="13"  type="STRING"  enable="1" />
242 
// Retrieval info:      <PRIVATE name = "local_if_dwidth_label" value="32"  type="STRING"  enable="1" />
243 
// Retrieval info:      <PRIVATE name = "mem_if_dm_pins_en" value="Yes"  type="STRING"  enable="1" />
244 
// Retrieval info:      <PRIVATE name = "mem_if_preset" value="PSC A2S56D40CTP-G5"  type="STRING"  enable="1" />
245 
// Retrieval info:      <PRIVATE name = "fast_simulation_en" value="FAST"  type="STRING"  enable="1" />
246 
// Retrieval info:      <PRIVATE name = "mem_if_coladdr_width" value="9"  type="STRING"  enable="1" />
247 
// Retrieval info:      <PRIVATE name = "mem_if_dq_per_dqs" value="8"  type="STRING"  enable="1" />
248 
// Retrieval info:      <PRIVATE name = "mem_if_dwidth" value="16"  type="STRING"  enable="1" />
249 
// Retrieval info:      <PRIVATE name = "mem_tiha_ps" value="600"  type="STRING"  enable="1" />
250 
// Retrieval info:      <PRIVATE name = "mem_tdsh_ck" value="0.2"  type="STRING"  enable="1" />
251 
// Retrieval info:      <PRIVATE name = "mem_if_trfc_ns" value="70.0"  type="STRING"  enable="1" />
252 
// Retrieval info:      <PRIVATE name = "mem_tqh_ck" value="0.36"  type="STRING"  enable="1" />
253 
// Retrieval info:      <PRIVATE name = "mem_tisa_ps" value="600"  type="STRING"  enable="1" />
254 
// Retrieval info:      <PRIVATE name = "mem_tdss_ck" value="0.2"  type="STRING"  enable="1" />
255 
// Retrieval info:      <PRIVATE name = "mem_if_tinit_us" value="200.0"  type="STRING"  enable="1" />
256 
// Retrieval info:      <PRIVATE name = "mem_if_trcd_ns" value="15.0"  type="STRING"  enable="1" />
257 
// Retrieval info:      <PRIVATE name = "mem_if_twtr_ck" value="2"  type="STRING"  enable="1" />
258 
// Retrieval info:      <PRIVATE name = "mem_tdqss_ck" value="0.28"  type="STRING"  enable="1" />
259 
// Retrieval info:      <PRIVATE name = "mem_tqhs_ps" value="500"  type="STRING"  enable="1" />
260 
// Retrieval info:      <PRIVATE name = "mem_tdsa_ps" value="400"  type="STRING"  enable="1" />
261 
// Retrieval info:      <PRIVATE name = "mem_tac_ps" value="700"  type="STRING"  enable="1" />
262 
// Retrieval info:      <PRIVATE name = "mem_tdha_ps" value="400"  type="STRING"  enable="1" />
263 
// Retrieval info:      <PRIVATE name = "mem_if_tras_ns" value="40.0"  type="STRING"  enable="1" />
264 
// Retrieval info:      <PRIVATE name = "mem_if_twr_ns" value="15.0"  type="STRING"  enable="1" />
265 
// Retrieval info:      <PRIVATE name = "mem_tdqsck_ps" value="550"  type="STRING"  enable="1" />
266 
// Retrieval info:      <PRIVATE name = "mem_if_trp_ns" value="15.0"  type="STRING"  enable="1" />
267 
// Retrieval info:      <PRIVATE name = "mem_tdqsq_ps" value="400"  type="STRING"  enable="1" />
268 
// Retrieval info:      <PRIVATE name = "mem_if_tmrd_ns" value="10.0"  type="STRING"  enable="1" />
269 
// Retrieval info:      <PRIVATE name = "mem_if_trefi_us" value="7.0"  type="STRING"  enable="1" />
270 
// Retrieval info:      <PRIVATE name = "mem_tcl" value="3.0"  type="STRING"  enable="1" />
271 
// Retrieval info:      <PRIVATE name = "mem_tcl_40_fmax" value="533.0"  type="STRING"  enable="1" />
272 
// Retrieval info:      <PRIVATE name = "mem_odt" value="Disabled"  type="STRING"  enable="1" />
273 
// Retrieval info:      <PRIVATE name = "mem_dll_en" value="Yes"  type="STRING"  enable="1" />
274 
// Retrieval info:      <PRIVATE name = "ac_phase" value="90"  type="STRING"  enable="1" />
275 
// Retrieval info:      <PRIVATE name = "mem_drv_str" value="Normal"  type="STRING"  enable="1" />
276 
// Retrieval info:      <PRIVATE name = "mem_if_oct_en" value="false"  type="STRING"  enable="1" />
277 
// Retrieval info:      <PRIVATE name = "input_period" value="0"  type="STRING"  enable="1" />
278 
// Retrieval info:      <PRIVATE name = "mem_tcl_60_fmax" value="533.0"  type="STRING"  enable="1" />
279 
// Retrieval info:      <PRIVATE name = "board_skew_ps" value="20"  type="STRING"  enable="1" />
280 
// Retrieval info:      <PRIVATE name = "mem_if_dqsn_en" value="false"  type="STRING"  enable="1" />
281 
// Retrieval info:      <PRIVATE name = "dll_external" value="false"  type="STRING"  enable="1" />
282 
// Retrieval info:      <PRIVATE name = "mem_tcl_15_fmax" value="533.0"  type="STRING"  enable="1" />
283 
// Retrieval info:      <PRIVATE name = "mem_tcl_30_fmax" value="200.0"  type="STRING"  enable="1" />
284 
// Retrieval info:      <PRIVATE name = "mem_bl" value="4"  type="STRING"  enable="1" />
285 
// Retrieval info:      <PRIVATE name = "ac_clk_select" value="90"  type="STRING"  enable="1" />
286 
// Retrieval info:      <PRIVATE name = "mem_tcl_50_fmax" value="533.0"  type="STRING"  enable="1" />
287 
// Retrieval info:      <PRIVATE name = "mem_tcl_25_fmax" value="200.0"  type="STRING"  enable="1" />
288 
// Retrieval info:      <PRIVATE name = "mem_tcl_20_fmax" value="133.333"  type="STRING"  enable="1" />
289 
// Retrieval info:      <PRIVATE name = "pll_reconfig_ports_en" value="false"  type="STRING"  enable="1" />
290 
// Retrieval info:      <PRIVATE name = "mem_btype" value="Sequential"  type="STRING"  enable="1" />
291 
// Retrieval info:      <PRIVATE name = "ctl_ecc_en" value="false"  type="STRING"  enable="1" />
292 
// Retrieval info:      <PRIVATE name = "user_refresh_en" value="false"  type="STRING"  enable="1" />
293 
// Retrieval info:      <PRIVATE name = "local_if_type_avalon" value="true"  type="STRING"  enable="1" />
294 
// Retrieval info:      <PRIVATE name = "ctl_self_refresh_en" value="false"  type="STRING"  enable="1" />
295 
// Retrieval info:      <PRIVATE name = "clk_source_sharing_en" value="false"  type="STRING"  enable="1" />
296 
// Retrieval info:      <PRIVATE name = "phy_if_type_afi" value="true"  type="STRING"  enable="1" />
297 
// Retrieval info:      <PRIVATE name = "ctl_autopch_en" value="false"  type="STRING"  enable="1" />
298 
// Retrieval info:      <PRIVATE name = "shared_sys_clk_source" value="XX"  type="STRING"  enable="1" />
299 
// Retrieval info:      <PRIVATE name = "ref_clk_source" value="XX"  type="STRING"  enable="1" />
300 
// Retrieval info:      <PRIVATE name = "ctl_powerdn_en" value="false"  type="STRING"  enable="1" />
301 
// Retrieval info:      <PRIVATE name = "tool_context" value="STANDALONE"  type="STRING"  enable="1" />
302 
// Retrieval info:      <PRIVATE name = "mem_srtr" value="Normal"  type="STRING"  enable="1" />
303 
// Retrieval info:      <PRIVATE name = "mem_mpr_loc" value="Predefined Pattern"  type="STRING"  enable="1" />
304 
// Retrieval info:      <PRIVATE name = "dss_tinit_rst_us" value="200.0"  type="STRING"  enable="1" />
305 
// Retrieval info:      <PRIVATE name = "mem_tcl_90_fmax" value="400.0"  type="STRING"  enable="1" />
306 
// Retrieval info:      <PRIVATE name = "mem_rtt_wr" value="Dynamic ODT off"  type="STRING"  enable="1" />
307 
// Retrieval info:      <PRIVATE name = "mem_tcl_100_fmax" value="400.0"  type="STRING"  enable="1" />
308 
// Retrieval info:      <PRIVATE name = "mem_pasr" value="Full Array"  type="STRING"  enable="1" />
309 
// Retrieval info:      <PRIVATE name = "mem_asrm" value="Manual SR Reference (SRT)"  type="STRING"  enable="1" />
310 
// Retrieval info:      <PRIVATE name = "mem_mpr_oper" value="Predefined Pattern"  type="STRING"  enable="1" />
311 
// Retrieval info:      <PRIVATE name = "mem_tcl_80_fmax" value="400.0"  type="STRING"  enable="1" />
312 
// Retrieval info:      <PRIVATE name = "mem_drv_impedance" value="RZQ/7"  type="STRING"  enable="1" />
313 
// Retrieval info:      <PRIVATE name = "mem_rtt_nom" value="ODT Disabled"  type="STRING"  enable="1" />
314 
// Retrieval info:      <PRIVATE name = "mem_tcl_70_fmax" value="400.0"  type="STRING"  enable="1" />
315 
// Retrieval info:      <PRIVATE name = "mem_wtcl" value="5.0"  type="STRING"  enable="1" />
316 
// Retrieval info:      <PRIVATE name = "mem_dll_pch" value="Fast Exit"  type="STRING"  enable="1" />
317 
// Retrieval info:      <PRIVATE name = "mem_atcl" value="Disabled"  type="STRING"  enable="1" />
318 
// Retrieval info:     </NAMESPACE>
319 
// Retrieval info:     <NAMESPACE name = "simgen">
320 
// Retrieval info:      <PRIVATE name = "use_alt_top" value="1"  type="STRING"  enable="1" />
321 
// Retrieval info:      <PRIVATE name = "alt_top" value="altera_ddr_auk_ddr_hp_controller_wrapper"  type="STRING"  enable="1" />
322 
// Retrieval info:      <PRIVATE name = "nativelink_excludes" value="altera_ddr_phy_alt_mem_phy_seq.vhd,altera_ddr_phy_alt_mem_phy_seq_wrapper.vhd,altera_ddr_phy_alt_mem_phy_seq_wrapper.v"  type="STRING"  enable="1" />
323 
// Retrieval info:      <PRIVATE name = "family" value="Cyclone III"  type="STRING"  enable="1" />
324 
// Retrieval info:      <PRIVATE name = "filename" value="altera_ddr_auk_ddr_hp_controller_wrapper.vo"  type="STRING"  enable="1" />
325 
// Retrieval info:     </NAMESPACE>
326 
// Retrieval info:     <NAMESPACE name = "simgen2">
327 
// Retrieval info:      <PRIVATE name = "family" value="Cyclone III"  type="STRING"  enable="1" />
328 
// Retrieval info:      <PRIVATE name = "command" value="--simgen_arbitrary_blackbox=+altera_ddr_alt_mem_phy_seq_wrapper;+altera_ddr_alt_mem_phy_reconfig;+altera_ddr_alt_mem_phy_pll;+altera_ddr_phy_alt_mem_phy_delay --ini=simgen_tri_bus_opt=on"  type="STRING"  enable="1" />
329 
// Retrieval info:      <PRIVATE name = "parameter" value="SIMGEN_INITIALIZATION_FILE=/opt/workspace/xzeng/esig/trunk/or1k_soc/rtl/altera_ddr_ctrl/altera_ddr_simgen_init.txt"  type="STRING"  enable="1" />
330 
// Retrieval info:     </NAMESPACE>
331 
// Retrieval info:     <NAMESPACE name = "simgen_enable">
332 
// Retrieval info:      <PRIVATE name = "language" value="Verilog HDL"  type="STRING"  enable="1" />
333 
// Retrieval info:      <PRIVATE name = "enabled" value="1"  type="STRING"  enable="1" />
334 
// Retrieval info:     </NAMESPACE>
335 
// Retrieval info:     <NAMESPACE name = "qip">
336 
// Retrieval info:      <PRIVATE name = "gx_libs" value="1"  type="STRING"  enable="1" />
337 
// Retrieval info:     </NAMESPACE>
338 
// Retrieval info:     <NAMESPACE name = "greybox">
339 
// Retrieval info:      <PRIVATE name = "filename" value="altera_ddr_syn.v"  type="STRING"  enable="1" />
340 
// Retrieval info:     </NAMESPACE>
341 
// Retrieval info:     <NAMESPACE name = "serializer"/>
342 
// Retrieval info:     <NAMESPACE name = "quartus_settings">
343 
// Retrieval info:      <PRIVATE name = "DEVICE" value="EP3C25F324C6"  type="STRING"  enable="1" />
344 
// Retrieval info:      <PRIVATE name = "FAMILY" value="Cyclone III"  type="STRING"  enable="1" />
345 
// Retrieval info:      <PRIVATE name = "WEB_BROWSER" value="/usr/bin/firefox"  type="STRING"  enable="1" />
346 
// Retrieval info:      <PRIVATE name = "LICENSE_FILE" value="/opt/altera9.0/license.dat"  type="STRING"  enable="1" />
347 
// Retrieval info:     </NAMESPACE>
348 
// Retrieval info:    </PRIVATES>
349 
// Retrieval info:    <FILES/>
350 
// Retrieval info:    <PORTS/>
351 
// Retrieval info:    <LIBRARIES/>
352 
// Retrieval info:   </STATIC_SECTION>
353 
// Retrieval info:  </NETLIST_SECTION>
354 
// Retrieval info: </MEGACORE>
355 
// =========================================================
356 
// RELATED_FILES: altera_ddr_auk_ddr_hp_controller_wrapper.v, auk_ddr_hp_controller.vhd, altera_ddr_phy_alt_mem_phy_seq.vhd,altera_ddr_phy_alt_mem_phy_seq_wrapper.vhd,altera_ddr_phy_alt_mem_phy_seq_wrapper.v;
357 
// IPFS_FILES: altera_ddr_auk_ddr_hp_controller_wrapper.vo;
358 
// =========================================================

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.