Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

DDR_INST

altera_ddr

Follow the recommendations to configure your core.

MegaCore variation

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INFO

Information

The following recommendations provide a flow for your DDR SDRAM memory interface design.

The following recommendations provide a walkthrough for designing a DDR SDRAM memory interface with the FPGA-External Memory design flow.

The walkthrough provides some recommended settings in order to simplify the design, including termination scheme and drive strength settings.

This walkthrough can also be found in AN:435 Design Guidelines for Implementing DDR-DDR2 SDRAM Interfaces in Stratix III Devices.

http://www.altera.com/literature/an/an435.pdf

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        Follow the steps outlined in this walkthrough to design a DDR SDRAM memory interface.

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PROJECT_PLANNING

Resource Planning

Follow the recommendations to plan your signals and device selection.

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PIN_PLAN

Pin Planning

The following recommendations provide steps for designing your DDR SDRAM memory interface.

Altera recommends the following pin placements:

* Data

- Pin on Memory Device: DQ

- Pin on FPGA: DQ

* Data Mask

- Pin on Memory Device: DM

- Pin on FPGA: DQ (1)

* Data Strobe

- Pin on Memory Device: DQS

- Pin on FPGA: DQS

* Memory Clock

- Pin on Memory Device: CK/CK#

- Pin on FPGA: DQ/DQS/DQSn (2)

* Address

- Pin on Memory Device: A, BA

- Pin on FPGA: Any user I/O

* Command

- Pin on Memory Device: CS#, RAS#, CAS#, WE#, CKE

- Pin on FPGA: Any user I/O

Notes:

(1) The DM pins must be in the write DQ group.

(2) Any unused DQ or DQS pins with DIFFOUT capability for mem_clk[n] and mem_clk_n[n].

Furthermore, please ensure that Address/Command pins are placed on the same side as the memory clocks.  Also, if on-chip termination (OCT) is used, ensure that the Rup/Rdn pins are assigned correctly.

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The DDR SDRAM High Performance Controller Megacore function does not generate pin assignments for non-memory signals such as clock sources or pin location assignments for the design. Launch Pin Planner to make these assignments to the design.

Ensure the clocks are placed on the correct pins and on the same side as Address/Command pins. If on-chip termination (OCT) is used, make sure Rup/Rdn are assigned correctly.

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BOARD_TRACE_MODEL

Board Trace Model Assignment

To ensure that IO timing performance is correctly modeled in QuartusII, it is necessary to complete the Board Trace Model definition for each signal.

Ensure that the overall board trace models are a reasonable approximation for each I/O standard on each PCB.

Board trace models include two transmission line segments (near and far). These line segments are ideal for SDRAM interfaces. You can use the near transmission line to represent the PCB and the far transmission line to represent the DIMM.

The board trace model should only include PCB or off chip information.

When implemented, ODT at the memory should be included as external discreet termination and the capacitive loading of the memory should be calculated for each net and also added.

*Ideally, the distributed capacitance and inductance of your PCB traces should be ascertained from your PCB development tool. However, in general a 50-ohm trace is approximately 3 pF and 8 nH per inch.

Trace delay information can be entered on a per net basis if desired, but in general a net group basis should be sufficient. Multiple nets can be selected at the same time and then have their respective board trace models all entered simultaneously.

Altera suggests the following net groups:

    * mem_clk

    * mem_addr (mem_a and mem_ba)

    * mem_ctrl (mem_cas#, mem_cke, mem_cs_n, mem_odt, mem_ras_n, mem_we_n)

    * mem_dq_group0 (mem_dq[7..0], mem_dm[0])

    * mem_dq_group1 (mem_dq[15..8], mem_dm[1])

    * mem_dq_group...

    * mem_dqs0 and mem_dqsn0

Notes:

    The DQS pin can be combined with the respective DQ group as a single-ended signal, otherwise each differential DQS pin pair should be entered separately.

    DIMM board trace models and SDRAM component capacitive loading information should be obtained from your memory vendor directly and must be included into your Quartus II board trace model parameters.

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                Please refer to AN:435 Design Guidelines for Implementing DDR-DDR2 SDRAM Interfaces in Stratix III Devices

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RTL_SIM

Perform RTL/Functional Simulation (Optional)

During the instantiation of the DDR SDRAM High Performance Controller, there is an option to generate a simulation model of the IP so you can perform functional simulation on your design.

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        Follow these recommendations to obtain and setup simulation models, and run functional simulation with NativeLink.

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SETUP_SIM

Setup Simulation Options in Quartus II software

Setup Simulation Options in Quartus II software

Obtain and copy the memory model to a suitable location. For example, obtain the ddr.v and ddr_parameters.vh memory model files from the Micron website and save them in the testbench directory.

Open the memory model file in a text editor and add the following define statements to the top of the file:

 'define sg25

 'define x8

The two define statements prepare the DDR SDRAM memory interface model.

The first statement specifies the memory device speed grade as -25. The second statement specifies the memory device width per DQS. Open the testbench in a text editor, instantiate the downloaded memory model, and connect its signals to the rest of the design.

You must delete the START and END MEGAWIZARD comments to ensure the MegaWizard Plug-In Manager does not overwrite the changes when the controller megafunction is regenerated.

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        Setup the simulation model

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RUN_SIM

Run Simulation with Nativelink

Run functional simulation with Nativelink

Set the absolute path to your third-party simulator executable.

On the Assignments menu, click on EDA Tool Settings to open the Settings dialog box. In the Category list (left-hand side of the panel) click the "+" icon to expand EDA Tool Settings and click Simulation.

In the Simulation panel, select ModelSim-Altera from the Tool list. In the NativeLink settings box, turn on Compile test bench. Enter the name of your testbench top-level module, simulation period, etc.

After you have elaborated the design, point to Run EDA Simulation Tool from the Tools menu and click EDA RTL Simulation. This step creates the \simulation directory in your project directory, as well as a script that compiles all necessary files and runs the simulation.

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        Setup NativeLink, and run the simulation

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ADD

Add Constraints

The following recommendations guide you in adding the correct constraints.

Add Constraints

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ADD_TIMING

Add Timing Constraints

Add the timing constraint file to the project.

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        Follow these recommendations to select the timing analyzer and add timing constraints.

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TIMING_ANALYZER_OPTION

Select Timing Analyzer Option

Select the timing analyzer option

Select TimeQuest as the timing analyzer.

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        Open the Settings dialog box and verify that TimeQuest is selected as the timing analyzer.

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CONSTRAINT_SCRIPT

Add Timing Constraints Script

Add the timing constraint file to the project.

Instantiating the DDR SDRAM High Performance Controller generates constraint files for the design. The timing constraint file, altera_ddr_phy_ddr_timing.sdc, constrains the clock and input/output delay on the DDR SDRAM High Performance Controller.

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        To add the timing constraints, go to the Assignments menu and click the Settings option. In the Settings dialog box, under Timing Analysis Settings, select TimeQuest Timing Analyzer. Select the SDC file and click Add.

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                altera_ddr_phy_ddr_timing.sdc

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ADD_PIN_DQ

Add Pin and DQ Group Assignments

Run the tcl script to add pin assignments and DQ group assignments

The pin assignment script, altera_ddr_pin_assignments.tcl, sets up the I/O standards for the DDR SDRAM memory interface.  It also launches the DQ group assignment script, altera_ddr_phy_assign_dq_groups.tcl, which relates the DQ and DQS pin groups together for the Fitter to place them correctly in the Quartus II software.

Please note that this script does not create a clock for the design. You need to create a clock for the design and provide pin assignments for the signals of both the example driver and testbench that were generated with the MegaCore variation.

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        Run the altera_ddr_pin_assignments.tcl to add the pin, I/O standards, and DQ group assignments to the example design.  <p>You can either click on the button below to let the IP Advisor run the script, or open the Tcl Scripts dialog box to run the script manually.

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