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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [altera_ddr_ctrl/] [altera_ddr_ex_lfsr8.v] - Blame information for rev 12

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//
module altera_ddr_ex_lfsr8 (
clk, reset_n, enable, pause, load, data, ldata);
 
   parameter seed  = 32;
   input clk;
   input reset_n;
   input enable;
   input pause;
   input load;
   output[8 - 1:0] data;
   wire[8 - 1:0] data;
   input[8 - 1:0] ldata;
 
   reg[8 - 1:0] lfsr_data;
 
   assign data = lfsr_data ;
 
   always @(posedge clk or negedge reset_n)
   begin
      if (!reset_n)
      begin
         // Reset - asynchronously reset to seed value
         lfsr_data <= seed[7:0] ;
      end
      else
      begin
         if (!enable)
         begin
            lfsr_data <= seed[7:0];
         end
         else
         begin
            if (load)
            begin
               lfsr_data <= ldata ;
            end
            else
            begin
               // Registered mode - synchronous propagation of signals
               if (!pause)
               begin
                  lfsr_data[0] <= lfsr_data[7] ;
                  lfsr_data[1] <= lfsr_data[0] ;
                  lfsr_data[2] <= lfsr_data[1] ^ lfsr_data[7] ;
                  lfsr_data[3] <= lfsr_data[2] ^ lfsr_data[7] ;
                  lfsr_data[4] <= lfsr_data[3] ^ lfsr_data[7] ;
                  lfsr_data[5] <= lfsr_data[4] ;
                  lfsr_data[6] <= lfsr_data[5] ;
                  lfsr_data[7] <= lfsr_data[6] ;
               end
            end
         end
      end
   end
endmodule

Line No.	Rev	Author	Line
1	12	xianfeng	`//`
2			`module altera_ddr_ex_lfsr8 (`
3			`clk, reset_n, enable, pause, load, data, ldata);`
4
5			`parameter seed = 32;`
6			`input clk;`
7			`input reset_n;`
8			`input enable;`
9			`input pause;`
10			`input load;`
11			`output[8 - 1:0] data;`
12			`wire[8 - 1:0] data;`
13			`input[8 - 1:0] ldata;`
14
15			`reg[8 - 1:0] lfsr_data;`
16
17			`assign data = lfsr_data ;`
18
19			`always @(posedge clk or negedge reset_n)`
20			`begin`
21			`if (!reset_n)`
22			`begin`
23			`// Reset - asynchronously reset to seed value`
24			`lfsr_data <= seed[7:0] ;`
25			`end`
26			`else`
27			`begin`
28			`if (!enable)`
29			`begin`
30			`lfsr_data <= seed[7:0];`
31			`end`
32			`else`
33			`begin`
34			`if (load)`
35			`begin`
36			`lfsr_data <= ldata ;`
37			`end`
38			`else`
39			`begin`
40			`// Registered mode - synchronous propagation of signals`
41			`if (!pause)`
42			`begin`
43			`lfsr_data[0] <= lfsr_data[7] ;`
44			`lfsr_data[1] <= lfsr_data[0] ;`
45			`lfsr_data[2] <= lfsr_data[1] ^ lfsr_data[7] ;`
46			`lfsr_data[3] <= lfsr_data[2] ^ lfsr_data[7] ;`
47			`lfsr_data[4] <= lfsr_data[3] ^ lfsr_data[7] ;`
48			`lfsr_data[5] <= lfsr_data[4] ;`
49			`lfsr_data[6] <= lfsr_data[5] ;`
50			`lfsr_data[7] <= lfsr_data[6] ;`
51			`end`
52			`end`
53			`end`
54			`end`
55			`end`
56			`endmodule`

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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [altera_ddr_ctrl/] [altera_ddr_ex_lfsr8.v] - Blame information for rev 12