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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [altera_ddr_ctrl/] [altera_ddr_example_driver.v] - Blame information for rev 12

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1 12 xianfeng 
//Legal Notice: (C)2009 Altera Corporation. All rights reserved.  Your
2 
//use of Altera Corporation's design tools, logic functions and other
3 
//software and tools, and its AMPP partner logic functions, and any
4 
//output files any of the foregoing (including device programming or
5 
//simulation files), and any associated documentation or information are
6 
//expressly subject to the terms and conditions of the Altera Program
7 
//License Subscription Agreement or other applicable license agreement,
8 
//including, without limitation, that your use is for the sole purpose
9 
//of programming logic devices manufactured by Altera and sold by Altera
10 
//or its authorized distributors.  Please refer to the applicable
11 
//agreement for further details.
12 
 
13 
// synthesis translate_off
14 
`timescale 1ns / 1ps
15 
// synthesis translate_on
16 
 
17 
// turn off superfluous verilog processor warnings
18 
// altera message_level Level1
19 
// altera message_off 10034 10035 10036 10037 10230 10240 10030
20 
 
21 
module altera_ddr_example_driver (
22 
                                   // inputs:
23 
                                    clk,
24 
                                    local_rdata,
25 
                                    local_rdata_valid,
26 
                                    local_ready,
27 
                                    reset_n,
28 
 
29 
                                   // outputs:
30 
                                    local_bank_addr,
31 
                                    local_be,
32 
                                    local_burstbegin,
33 
                                    local_col_addr,
34 
                                    local_cs_addr,
35 
                                    local_read_req,
36 
                                    local_row_addr,
37 
                                    local_size,
38 
                                    local_wdata,
39 
                                    local_write_req,
40 
                                    pnf_per_byte,
41 
                                    pnf_persist,
42 
                                    test_complete,
43 
                                    test_status
44 
                                 )
45 
  /* synthesis ALTERA_ATTRIBUTE = "MESSAGE_DISABLE=14130;MESSAGE_DISABLE=14110" */ ;
46 
 
47 
  output  [  1: 0] local_bank_addr;
48 
  output  [  3: 0] local_be;
49 
  output           local_burstbegin;
50 
  output  [  8: 0] local_col_addr;
51 
  output           local_cs_addr;
52 
  output           local_read_req;
53 
  output  [ 12: 0] local_row_addr;
54 
  output  [  1: 0] local_size;
55 
  output  [ 31: 0] local_wdata;
56 
  output           local_write_req;
57 
  output  [  3: 0] pnf_per_byte;
58 
  output           pnf_persist;
59 
  output           test_complete;
60 
  output  [  7: 0] test_status;
61 
  input            clk;
62 
  input   [ 31: 0] local_rdata;
63 
  input            local_rdata_valid;
64 
  input            local_ready;
65 
  input            reset_n;
66 
 
67 
  wire    [ 19: 0] COUNTER_VALUE;
68 
  wire    [  1: 0] LOCAL_BURST_LEN_s;
69 
  wire    [  1: 0] MAX_BANK;
70 
  wire             MAX_CHIPSEL;
71 
  wire    [  8: 0] MAX_COL;
72 
  wire    [ 12: 0] MAX_ROW;
73 
  wire    [ 12: 0] MAX_ROW_PIN;
74 
  wire             MIN_CHIPSEL;
75 
  wire    [  3: 0] addr_value;
76 
  wire             avalon_burst_mode;
77 
  reg     [  1: 0] bank_addr;
78 
  reg     [  3: 0] be;
79 
  reg     [  2: 0] burst_beat_count;
80 
  reg              burst_begin;
81 
  reg     [  8: 0] col_addr;
82 
  wire    [  3: 0] compare;
83 
  reg     [  3: 0] compare_reg;
84 
  reg     [  3: 0] compare_valid;
85 
  reg     [  3: 0] compare_valid_reg;
86 
  reg              cs_addr;
87 
  wire    [ 31: 0] dgen_data;
88 
  reg              dgen_enable;
89 
  reg     [ 31: 0] dgen_ldata;
90 
  reg              dgen_load;
91 
  wire             dgen_pause;
92 
  wire             enable_be;
93 
  reg              full_burst_on;
94 
  reg              last_rdata_valid;
95 
  reg              last_wdata_req;
96 
  wire    [  1: 0] local_bank_addr;
97 
  wire    [  3: 0] local_be;
98 
  wire             local_burstbegin;
99 
  wire    [  8: 0] local_col_addr;
100 
  wire             local_cs_addr;
101 
  wire             local_read_req;
102 
  wire    [ 12: 0] local_row_addr;
103 
  wire    [  1: 0] local_size;
104 
  wire    [ 31: 0] local_wdata;
105 
  wire             local_write_req;
106 
  wire    [  8: 0] max_col_value;
107 
  wire             p_burst_begin;
108 
  wire             p_read_req;
109 
  reg              p_state_on;
110 
  wire             pause_be;
111 
  wire    [  3: 0] pnf_per_byte;
112 
  reg              pnf_persist;
113 
  reg              pnf_persist1;
114 
  wire             pnf_persist_compare;
115 
  wire             powerdn_on;
116 
  reg              rdata_valid_flag;
117 
  reg              rdata_valid_flag_reg;
118 
  reg              rdata_valid_flag_reg_2;
119 
  wire             reached_max_address;
120 
  reg              read_req;
121 
  reg     [  7: 0] reads_remaining;
122 
  reg              reset_address;
123 
  reg              reset_be;
124 
  reg              reset_data;
125 
  wire             restart_LFSR_n;
126 
  reg     [ 12: 0] row_addr;
127 
  wire             selfrfsh_on;
128 
  wire    [  1: 0] size;
129 
  reg     [  4: 0] state;
130 
  reg              test_addr_pin;
131 
  reg              test_addr_pin_mode;
132 
  wire             test_addr_pin_on;
133 
  reg              test_complete;
134 
  reg              test_dm_pin;
135 
  reg              test_dm_pin_mode;
136 
  wire             test_dm_pin_on;
137 
  reg              test_incomplete_writes;
138 
  reg              test_incomplete_writes_mode;
139 
  wire             test_incomplete_writes_on;
140 
  reg              test_seq_addr;
141 
  reg              test_seq_addr_mode;
142 
  wire             test_seq_addr_on;
143 
  wire    [  7: 0] test_status;
144 
  reg              wait_first_write_data;
145 
  wire    [ 31: 0] wdata;
146 
  wire             wdata_req;
147 
  reg              write_req;
148 
  reg     [  7: 0] writes_remaining;
149 
  //
150 
 
151 
  //Turn on this mode to test sequential address
152 
  assign test_seq_addr_on = 1'b1;
153 
 
154 
  //Turn on this mode to test all address pins by a One-hot pattern address generator
155 
  assign test_addr_pin_on = 1'b1;
156 
 
157 
  //Turn on this mode to make use of dm pins
158 
  assign test_dm_pin_on = 1'b1;
159 
 
160 
  //Turn on this mode to exercise write process in Full rate, size 1 or DDR3 Half rate, size 1
161 
  assign test_incomplete_writes_on = 1'b1;
162 
 
163 
  //restart_LFSR_n is an active low signal, set it to 1'b0 to restart LFSR data generator after a complete test
164 
  assign restart_LFSR_n = 1'b1;
165 
 
166 
  //Change COUNTER_VALUE to control the period of power down and self refresh mode
167 
  assign COUNTER_VALUE = 150;
168 
 
169 
  //Change MAX_ROW to test more or lesser row address in test_seq_addr_mode, maximum value is 2^(row bits) -1, while minimum value is 0
170 
  assign MAX_ROW = 3;
171 
 
172 
  //Change MAX_COL to test more or lesser column address in test_seq_addr_mode, maximum value is 2^(column bits) - (LOCAL_BURST_LEN_s * dwidth_ratio (aka half-rate (4) or full-rate (2))), while minimum value is 0 for Half rate and (LOCAL_BURST_LEN_s * dwidth_ratio) for Full rate
173 
  assign MAX_COL = 16;
174 
 
175 
  //Decrease MAX_BANK to test lesser bank address, minimum value is 0
176 
  assign MAX_BANK = 3;
177 
 
178 
  //Decrease MAX_CHIPSEL to test lesser memory chip, minimum value is MIN_CHIPSEL
179 
  assign MAX_CHIPSEL = 0;
180 
 
181 
  //
182 
 
183 
  assign MIN_CHIPSEL = 0;
184 
  assign MAX_ROW_PIN = {13{1'b1}};
185 
  assign max_col_value = ((addr_value == 2) == 0)? MAX_COL :
186 
    (MAX_COL + 2);
187 
 
188 
  assign powerdn_on = 1'b0;
189 
  assign selfrfsh_on = 1'b0;
190 
  assign local_burstbegin = burst_begin | p_burst_begin;
191 
  assign avalon_burst_mode = 1;
192 
  //
193 
  //One hot decoder for test_status signal
194 
  assign test_status[0] = test_seq_addr_mode;
195 
  assign test_status[1] = test_incomplete_writes_mode;
196 
  assign test_status[2] = test_dm_pin_mode;
197 
  assign test_status[3] = test_addr_pin_mode;
198 
  assign test_status[4] = 0;
199 
  assign test_status[5] = 0;
200 
  assign test_status[6] = 0;
201 
  assign test_status[7] = test_complete;
202 
  assign p_read_req = 0;
203 
  assign p_burst_begin = 0;
204 
  assign local_cs_addr = cs_addr;
205 
  assign local_row_addr = row_addr;
206 
  assign local_bank_addr = bank_addr;
207 
  assign local_col_addr = col_addr;
208 
  assign local_write_req = write_req;
209 
  assign local_wdata = wdata;
210 
  assign local_read_req = read_req | p_read_req;
211 
  assign wdata = (reset_data == 0)? dgen_data :
212 
    32'd0;
213 
 
214 
  //The LOCAL_BURST_LEN_s is a signal used insted of the parameter LOCAL_BURST_LEN
215 
  assign LOCAL_BURST_LEN_s = 2;
216 
  //LOCAL INTERFACE (AVALON)
217 
  assign wdata_req = write_req & local_ready;
218 
 
219 
  // Generate new data (enable lfsr) when writing or reading valid data
220 
  assign dgen_pause = ~ ((wdata_req & ~reset_data) | (local_rdata_valid));
221 
 
222 
  assign enable_be = (wdata_req & test_dm_pin_mode & ~reset_data) | (test_dm_pin_mode & local_rdata_valid);
223 
  assign pnf_per_byte = compare_valid_reg;
224 
  assign pause_be = (reset_data & test_dm_pin_mode) | ~test_dm_pin_mode;
225 
  assign local_be = be;
226 
  assign local_size = size;
227 
  assign size = (full_burst_on == 0)? 1'd1 :
228 
    LOCAL_BURST_LEN_s[1 : 0];
229 
 
230 
  assign reached_max_address = (row_addr == MAX_ROW_PIN) || ((col_addr == (max_col_value)) & (row_addr == MAX_ROW) & (bank_addr == MAX_BANK) & (cs_addr == MAX_CHIPSEL));
231 
  assign addr_value = ((test_incomplete_writes_mode & write_req & ~full_burst_on) == 0)? 4 :
232 
    2;
233 
 
234 
  assign pnf_persist_compare = (rdata_valid_flag_reg_2 == 0)? 1'd1 :
235 
    pnf_persist1;
236 
 
237 
  altera_ddr_ex_lfsr8 LFSRGEN_0_lfsr_inst
238 
    (
239 
      .clk (clk),
240 
      .data (dgen_data[7 : 0]),
241 
      .enable (dgen_enable),
242 
      .ldata (dgen_ldata[7 : 0]),
243 
      .load (dgen_load),
244 
      .pause (dgen_pause),
245 
      .reset_n (reset_n)
246 
    );
247 
 
248 
  defparam LFSRGEN_0_lfsr_inst.seed = 1;
249 
 
250 
  // 8 bit comparator per local byte lane
251 
  assign compare[0] = (dgen_data[7 : 0] & {8 {be[0]}}) === local_rdata[7 : 0];
252 
 
253 
  altera_ddr_ex_lfsr8 LFSRGEN_1_lfsr_inst
254 
    (
255 
      .clk (clk),
256 
      .data (dgen_data[15 : 8]),
257 
      .enable (dgen_enable),
258 
      .ldata (dgen_ldata[15 : 8]),
259 
      .load (dgen_load),
260 
      .pause (dgen_pause),
261 
      .reset_n (reset_n)
262 
    );
263 
 
264 
  defparam LFSRGEN_1_lfsr_inst.seed = 11;
265 
 
266 
  // 8 bit comparator per local byte lane
267 
  assign compare[1] = (dgen_data[15 : 8] & {8 {be[1]}}) === local_rdata[15 : 8];
268 
 
269 
  altera_ddr_ex_lfsr8 LFSRGEN_2_lfsr_inst
270 
    (
271 
      .clk (clk),
272 
      .data (dgen_data[23 : 16]),
273 
      .enable (dgen_enable),
274 
      .ldata (dgen_ldata[23 : 16]),
275 
      .load (dgen_load),
276 
      .pause (dgen_pause),
277 
      .reset_n (reset_n)
278 
    );
279 
 
280 
  defparam LFSRGEN_2_lfsr_inst.seed = 21;
281 
 
282 
  // 8 bit comparator per local byte lane
283 
  assign compare[2] = (dgen_data[23 : 16] & {8 {be[2]}}) === local_rdata[23 : 16];
284 
 
285 
  altera_ddr_ex_lfsr8 LFSRGEN_3_lfsr_inst
286 
    (
287 
      .clk (clk),
288 
      .data (dgen_data[31 : 24]),
289 
      .enable (dgen_enable),
290 
      .ldata (dgen_ldata[31 : 24]),
291 
      .load (dgen_load),
292 
      .pause (dgen_pause),
293 
      .reset_n (reset_n)
294 
    );
295 
 
296 
  defparam LFSRGEN_3_lfsr_inst.seed = 31;
297 
 
298 
  // 8 bit comparator per local byte lane
299 
  assign compare[3] = (dgen_data[31 : 24] & {8 {be[3]}}) === local_rdata[31 : 24];
300 
 
301 
  //
302 
  //-----------------------------------------------------------------
303 
  //Main clocked process
304 
  //-----------------------------------------------------------------
305 
  //Read / Write control state machine & address counter
306 
  //-----------------------------------------------------------------
307 
  always @(posedge clk or negedge reset_n)
308 
    begin
309 
      if (reset_n == 0)
310 
        begin
311 
          //Reset - asynchronously force all register outputs LOW
312 
          state <= 0;
313 
 
314 
          write_req <= 1'b0;
315 
          read_req <= 1'b0;
316 
          burst_begin <= 1'b0;
317 
          burst_beat_count <= 0;
318 
          dgen_load <= 1'b0;
319 
          wait_first_write_data <= 1'b0;
320 
          test_complete <= 1'b0;
321 
          reset_data <= 1'b0;
322 
          reset_be <= 1'b0;
323 
          writes_remaining <= 0;
324 
          reads_remaining <= 0;
325 
          test_addr_pin <= 1'b0;
326 
          test_dm_pin <= 1'b0;
327 
          test_seq_addr <= 1'b0;
328 
          test_incomplete_writes <= 1'b0;
329 
          test_addr_pin_mode <= 1'b0;
330 
          test_dm_pin_mode <= 1'b0;
331 
          test_seq_addr_mode <= 1'b0;
332 
          test_incomplete_writes_mode <= 1'b0;
333 
          full_burst_on <= 1'b1;
334 
          p_state_on <= 1'b0;
335 
          dgen_enable <= 1'b1;
336 
        end
337 
      else
338 
        begin
339 
          if (write_req & local_ready)
340 
            begin
341 
              if (wdata_req)
342 
                  writes_remaining <= writes_remaining + (size - 1);
343 
              else
344 
                writes_remaining <= writes_remaining + size;
345 
            end
346 
          else if ((wdata_req) & (writes_remaining > 0))
347 
              //size
348 
              writes_remaining <= writes_remaining - 1'b1;
349 
 
350 
          else
351 
            writes_remaining <= writes_remaining;
352 
          if ((read_req | p_read_req) & local_ready)
353 
            begin
354 
              if (local_rdata_valid)
355 
                  reads_remaining <= reads_remaining + (size - 1);
356 
              else
357 
                reads_remaining <= reads_remaining + size;
358 
            end
359 
          else if ((local_rdata_valid) & (reads_remaining > 0))
360 
              reads_remaining <= reads_remaining - 1'b1;
361 
          else
362 
            reads_remaining <= reads_remaining;
363 
          case (state)
364 
 
365 
              5'd0: begin
366 
                  test_addr_pin <= test_addr_pin_on;
367 
                  test_dm_pin <= test_dm_pin_on;
368 
                  test_seq_addr <= test_seq_addr_on;
369 
                  test_incomplete_writes <= test_incomplete_writes_on;
370 
                  test_complete <= 1'b0;
371 
                  state <= 1;
372 
              end // 5'd0
373 
 
374 
              5'd1: begin
375 
                  //Reset just in case!
376 
                  reset_address <= 1'b0;
377 
 
378 
                  reset_be <= 1'b0;
379 
                  write_req <= 1'b1;
380 
                  writes_remaining <= 1'b0;
381 
                  reads_remaining <= 1'b0;
382 
                  wait_first_write_data <= 1'b1;
383 
                  dgen_enable <= 1'b1;
384 
                  if (test_seq_addr == 1'b1)
385 
                    begin
386 
                      test_seq_addr_mode <= 1;
387 
                      if (avalon_burst_mode == 0)
388 
                          state <= 5;
389 
                      else if (avalon_burst_mode == 1)
390 
                        begin
391 
                          state <= 13;
392 
                          burst_begin <= 1'b1;
393 
                        end
394 
                    end
395 
                  else if (test_incomplete_writes == 1'b1)
396 
                    begin
397 
                      full_burst_on <= 1'b0;
398 
                      test_incomplete_writes_mode <= 1;
399 
                      state <= 5;
400 
                      if (avalon_burst_mode == 1)
401 
                          burst_begin <= 1'b1;
402 
                    end
403 
                  else if (test_dm_pin == 1'b1)
404 
                    begin
405 
                      reset_data <= 1'b1;
406 
                      test_dm_pin_mode <= 1;
407 
                      if (avalon_burst_mode == 0)
408 
                          state <= 2;
409 
                      else
410 
                        begin
411 
                          burst_begin <= 1'b1;
412 
                          state <= 10;
413 
                        end
414 
                    end
415 
                  else if (test_addr_pin == 1'b1)
416 
                    begin
417 
                      test_addr_pin_mode <= 1;
418 
                      if (avalon_burst_mode == 0)
419 
                          state <= 5;
420 
                      else if (avalon_burst_mode == 1)
421 
                        begin
422 
                          state <= 13;
423 
                          burst_begin <= 1'b1;
424 
                        end
425 
                    end
426 
                  else
427 
                    state <= 9;
428 
              end // 5'd1
429 
 
430 
              5'd10: begin
431 
                  wait_first_write_data <= 1'b0;
432 
                  burst_begin <= 1'b0;
433 
                  if (write_req & local_ready)
434 
                    begin
435 
                      burst_beat_count <= burst_beat_count + 1'b1;
436 
                      state <= 11;
437 
                    end
438 
              end // 5'd10
439 
 
440 
              5'd11: begin
441 
                  if (write_req & local_ready)
442 
                      if (burst_beat_count == size - 1'b1)
443 
                        begin
444 
                          burst_beat_count <= 0;
445 
                          burst_begin <= 1'b1;
446 
                          if (reached_max_address)
447 
                              state <= 12;
448 
                          else
449 
                            state <= 10;
450 
                        end
451 
                      else
452 
                        burst_beat_count <= burst_beat_count + 1'b1;
453 
              end // 5'd11
454 
 
455 
              5'd12: begin
456 
                  burst_begin <= 1'b0;
457 
                  if (write_req & local_ready)
458 
                      state <= 3;
459 
              end // 5'd12
460 
 
461 
              5'd13: begin
462 
                  wait_first_write_data <= 1'b0;
463 
                  burst_begin <= 1'b0;
464 
                  reset_be <= 1'b0;
465 
                  if (write_req & local_ready)
466 
                    begin
467 
                      burst_beat_count <= burst_beat_count + 1'b1;
468 
                      state <= 14;
469 
                    end
470 
              end // 5'd13
471 
 
472 
              5'd14: begin
473 
                  if (write_req & local_ready)
474 
                      if (burst_beat_count == size - 1'b1)
475 
                        begin
476 
                          burst_beat_count <= 0;
477 
                          burst_begin <= 1'b1;
478 
                          if (reached_max_address)
479 
                              state <= 15;
480 
                          else
481 
                            state <= 13;
482 
                        end
483 
                      else
484 
                        burst_beat_count <= burst_beat_count + 1'b1;
485 
              end // 5'd14
486 
 
487 
              5'd15: begin
488 
                  if (write_req & local_ready)
489 
                    begin
490 
                      reset_address <= 1'b1;
491 
                      burst_begin <= 1'b0;
492 
                      state <= 6;
493 
                    end
494 
              end // 5'd15
495 
 
496 
              5'd16: begin
497 
                  dgen_load <= 1'b0;
498 
                  reset_be <= 1'b0;
499 
                  if (local_ready & read_req)
500 
                      if (reached_max_address)
501 
                        begin
502 
                          read_req <= 1'b0;
503 
                          burst_begin <= 1'b0;
504 
                          state <= 8;
505 
                        end
506 
              end // 5'd16
507 
 
508 
              5'd2: begin
509 
                  wait_first_write_data <= 1'b0;
510 
                  if (write_req & local_ready)
511 
                      if (reached_max_address)
512 
                        begin
513 
                          write_req <= 1'b0;
514 
                          state <= 3;
515 
                        end
516 
              end // 5'd2
517 
 
518 
              5'd3: begin
519 
                  if (avalon_burst_mode == 0)
520 
                    begin
521 
                      if (!wdata_req)
522 
                          if (writes_remaining == 0)
523 
                            begin
524 
                              reset_be <= 1'b1;
525 
                              reset_address <= 1'b1;
526 
                              dgen_load <= 1'b1;
527 
                              state <= 4;
528 
                            end
529 
                    end
530 
                  else if (write_req & local_ready)
531 
                    begin
532 
                      reset_be <= 1'b1;
533 
                      write_req <= 1'b0;
534 
                      reset_address <= 1'b1;
535 
                      dgen_load <= 1'b1;
536 
                      state <= 4;
537 
                    end
538 
              end // 5'd3
539 
 
540 
              5'd4: begin
541 
                  reset_address <= 1'b0;
542 
                  dgen_load <= 1'b0;
543 
                  reset_be <= 1'b0;
544 
                  reset_data <= 1'b0;
545 
                  write_req <= 1'b1;
546 
                  if (avalon_burst_mode == 0)
547 
                      state <= 5;
548 
                  else
549 
                    begin
550 
                      burst_begin <= 1'b1;
551 
                      state <= 13;
552 
                    end
553 
              end // 5'd4
554 
 
555 
              5'd5: begin
556 
                  wait_first_write_data <= 1'b0;
557 
                  if (write_req & local_ready)
558 
                    begin
559 
                      burst_begin <= 1'b1;
560 
                      if (reached_max_address)
561 
                        begin
562 
                          reset_address <= 1'b1;
563 
                          write_req <= 1'b0;
564 
                          state <= 6;
565 
                          if (test_incomplete_writes_mode)
566 
                            begin
567 
                              burst_begin <= 1'b0;
568 
                              full_burst_on <= 1'b1;
569 
                            end
570 
                        end
571 
                    end
572 
              end // 5'd5
573 
 
574 
              5'd6: begin
575 
                  reset_address <= 1'b0;
576 
                  if (avalon_burst_mode == 0)
577 
                    begin
578 
                      if (writes_remaining == 0)
579 
                        begin
580 
                          dgen_load <= 1'b1;
581 
                          reset_be <= 1'b1;
582 
                          read_req <= 1'b1;
583 
                          state <= 7;
584 
                        end
585 
                    end
586 
                  else if (test_incomplete_writes_mode)
587 
                    begin
588 
                      dgen_load <= 1'b1;
589 
                      read_req <= 1'b1;
590 
                      burst_begin <= 1'b1;
591 
                      state <= 16;
592 
                    end
593 
                  else if (write_req & local_ready)
594 
                    begin
595 
                      write_req <= 1'b0;
596 
                      dgen_load <= 1'b1;
597 
                      reset_be <= 1'b1;
598 
                      read_req <= 1'b1;
599 
                      burst_begin <= 1'b1;
600 
                      state <= 16;
601 
                    end
602 
              end // 5'd6
603 
 
604 
              5'd7: begin
605 
                  dgen_load <= 1'b0;
606 
                  reset_be <= 1'b0;
607 
                  if (local_ready & read_req)
608 
                      if (reached_max_address)
609 
                        begin
610 
                          read_req <= 1'b0;
611 
                          state <= 8;
612 
                        end
613 
              end // 5'd7
614 
 
615 
              5'd8: begin
616 
                  if (reads_remaining == 1'b0)
617 
                    begin
618 
                      reset_address <= 1'b1;
619 
                      if (test_seq_addr)
620 
                        begin
621 
                          test_seq_addr <= 1'b0;
622 
                          test_seq_addr_mode <= 1'b0;
623 
                          state <= 1;
624 
                        end
625 
                      else if (test_incomplete_writes)
626 
                        begin
627 
                          test_incomplete_writes <= 1'b0;
628 
                          test_incomplete_writes_mode <= 1'b0;
629 
                          state <= 1;
630 
                        end
631 
                      else if (test_dm_pin)
632 
                        begin
633 
                          test_dm_pin <= 1'b0;
634 
                          test_dm_pin_mode <= 1'b0;
635 
                          state <= 1;
636 
                        end
637 
                      else if (test_addr_pin)
638 
                        begin
639 
                          test_addr_pin_mode <= 1'b0;
640 
                          dgen_load <= 1'b1;
641 
                          state <= 9;
642 
                        end
643 
                      else
644 
                        state <= 9;
645 
                    end
646 
              end // 5'd8
647 
 
648 
              5'd9: begin
649 
                  reset_address <= 1'b0;
650 
                  reset_be <= 1'b0;
651 
                  dgen_load <= 1'b0;
652 
                  if (powerdn_on == 1'b0 & selfrfsh_on == 1'b0)
653 
                    begin
654 
                      test_complete <= 1'b1;
655 
                      p_state_on <= 1'b0;
656 
                      dgen_enable <= restart_LFSR_n;
657 
                      state <= 0;
658 
                    end
659 
                  else if (reached_max_address & reads_remaining == 0)
660 
                    begin
661 
                      p_state_on <= 1'b1;
662 
                      reset_address <= 1'b1;
663 
                      reset_be <= 1'b1;
664 
                      dgen_load <= 1'b1;
665 
                    end
666 
              end // 5'd9
667 
 
668 
          endcase // state
669 
        end
670 
    end
671 
 
672 
 
673 
  //
674 
  //-----------------------------------------------------------------
675 
  //Logics that detect the first read data
676 
  //-----------------------------------------------------------------
677 
  always @(posedge clk or negedge reset_n)
678 
    begin
679 
      if (reset_n == 0)
680 
          rdata_valid_flag <= 1'b0;
681 
      else if (local_rdata_valid)
682 
          rdata_valid_flag <= 1'b1;
683 
    end
684 
 
685 
 
686 
  //
687 
  //-----------------------------------------------------------------
688 
  //Address Generator Process
689 
  //-----------------------------------------------------------------
690 
  always @(posedge clk or negedge reset_n)
691 
    begin
692 
      if (reset_n == 0)
693 
        begin
694 
          cs_addr <= 0;
695 
          bank_addr <= 0;
696 
          row_addr <= 0;
697 
          col_addr <= 0;
698 
        end
699 
      else if (reset_address)
700 
        begin
701 
          cs_addr <= MIN_CHIPSEL;
702 
          row_addr <= 0;
703 
          bank_addr <= 0;
704 
          col_addr <= 0;
705 
        end
706 
      else if (((local_ready & write_req & (test_dm_pin_mode | test_addr_pin_mode)) & (state == 2 | state == 5 | state == 10 | state == 13)) | ((local_ready & read_req & (test_dm_pin_mode | test_addr_pin_mode)) & (state == 7 | state == 16)) || ((local_ready & p_read_req) & (state == 9)))
707 
        begin
708 
          col_addr[8 : 2] <= {col_addr[7 : 2],col_addr[8]};
709 
          row_addr[12 : 0] <= {row_addr[11 : 0],row_addr[12]};
710 
          if (row_addr == 13'd0)
711 
            begin
712 
              col_addr <= 9'd4;
713 
              row_addr <= 13'd1;
714 
            end
715 
          else if (row_addr == {1'b1,{12{1'b0}}})
716 
            begin
717 
              col_addr <= {{6{1'b1}},{3{1'b0}}};
718 
              row_addr <= {{12{1'b1}},1'b0};
719 
            end
720 
          else if (row_addr == {1'b0,{12{1'b1}}})
721 
            begin
722 
              col_addr <= {{7{1'b1}},{2{1'b0}}};
723 
              row_addr <= {13{1'b1}};
724 
            end
725 
          if (bank_addr == MAX_BANK)
726 
              bank_addr <= 0;
727 
          else
728 
            bank_addr <= bank_addr + 1'b1;
729 
          if (cs_addr == MAX_CHIPSEL)
730 
              cs_addr <= MIN_CHIPSEL;
731 
          else
732 
            cs_addr <= cs_addr + 1'b1;
733 
        end
734 
      else if ((local_ready & write_req & (test_seq_addr_mode | test_incomplete_writes_mode) &  (state == 2 | state == 5 | state == 10 | state == 13)) | ((local_ready & read_req & (test_seq_addr_mode | test_incomplete_writes_mode)) & (state == 7 | state == 16)))
735 
          if (col_addr >= max_col_value)
736 
            begin
737 
              col_addr <= 0;
738 
              if (row_addr == MAX_ROW)
739 
                begin
740 
                  row_addr <= 0;
741 
                  if (bank_addr == MAX_BANK)
742 
                    begin
743 
                      bank_addr <= 0;
744 
                      if (cs_addr == MAX_CHIPSEL)
745 
                          //reached_max_count <= TRUE
746 
                          //(others => '0')
747 
                          cs_addr <= MIN_CHIPSEL;
748 
 
749 
                      else
750 
                        cs_addr <= cs_addr + 1'b1;
751 
                    end
752 
                  else
753 
                    bank_addr <= bank_addr + 1'b1;
754 
                end
755 
              else
756 
                row_addr <= row_addr + 1'b1;
757 
            end
758 
          else
759 
            col_addr <= col_addr + addr_value;
760 
    end
761 
 
762 
 
763 
  //
764 
  //-----------------------------------------------------------------
765 
  //Byte Enable Generator Process
766 
  //-----------------------------------------------------------------
767 
  always @(posedge clk or negedge reset_n)
768 
    begin
769 
      if (reset_n == 0)
770 
          be <= {4{1'b1}};
771 
      else if (reset_be)
772 
          be <= 4'd1;
773 
      else if (enable_be)
774 
          be[3 : 0] <= {be[2 : 0],be[3]};
775 
      else if (pause_be)
776 
          be <= {4{1'b1}};
777 
      else
778 
        be <= be;
779 
    end
780 
 
781 
 
782 
  //------------------------------------------------------------
783 
  //LFSR re-load data storage
784 
  //Comparator masking and test pass signal generation
785 
  //------------------------------------------------------------
786 
  always @(posedge clk or negedge reset_n)
787 
    begin
788 
      if (reset_n == 0)
789 
        begin
790 
          dgen_ldata <= 0;
791 
          last_wdata_req <= 1'b0;
792 
          //all ones
793 
          compare_valid <= {4 {1'b1}};
794 
 
795 
          //all ones
796 
          compare_valid_reg <= {4 {1'b1}};
797 
 
798 
          pnf_persist <= 1'b0;
799 
          pnf_persist1 <= 1'b0;
800 
          //all ones
801 
          compare_reg <= {4 {1'b1}};
802 
 
803 
          last_rdata_valid <= 1'b0;
804 
          rdata_valid_flag_reg <= 1'b0;
805 
          rdata_valid_flag_reg_2 <= 1'b0;
806 
        end
807 
      else
808 
        begin
809 
          last_wdata_req <= wdata_req;
810 
          last_rdata_valid <= local_rdata_valid;
811 
          rdata_valid_flag_reg <= rdata_valid_flag;
812 
          rdata_valid_flag_reg_2 <= rdata_valid_flag_reg;
813 
          compare_reg <= compare;
814 
          if (wait_first_write_data)
815 
              dgen_ldata <= dgen_data;
816 
          //Enable the comparator result when read data is valid
817 
          if (last_rdata_valid)
818 
              compare_valid <= compare_reg;
819 
          //Create the overall persistent passnotfail output
820 
          if (&compare_valid & rdata_valid_flag_reg & pnf_persist_compare)
821 
              pnf_persist1 <= 1'b1;
822 
          else
823 
            pnf_persist1 <= 1'b0;
824 
          //Extra register stage to help Tco / Fmax on comparator output pins
825 
          compare_valid_reg <= compare_valid;
826 
 
827 
          pnf_persist <= pnf_persist1;
828 
        end
829 
    end
830 
 
831 
 
832 
 
833 
endmodule
834 
 

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