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</style></HEAD><BODY align="left" style='background-color: #ffffff;'><DIV align="left"><TABLE width="95%" border=0 cellpadding=2><TR><TD><TABLE cellpadding=2 border=0 ><TR><WIZARD></WIZARD><TD><H1>Generation Report - ALTMEMPHY v9.0</H1></TD></TR></TABLE></TD></TR><TR><TD><TABLE cellpadding=2 border=1 width="60%"><TR><TD><B>Entity Name</B></TD><TD>altera_ddr_phy_alt_mem_phy</TD></TR><TR><TD><B>Variation Name</B></TD><TD>altera_ddr_phy</TD></TR><TR><TD><B>Variation HDL</B></TD><TD>Verilog HDL</TD></TR><TR><TD><B>Output Directory</B></TD><TD>/opt/workspace/xzeng/esig/trunk/or1k_soc/rtl/altera_ddr_ctrl</TD></TR></TABLE></TD></TR><TR><TD><h2>File Summary</h2>The MegaWizard interface is creating the following files in the output directory:</TD></TR><TR><TD><TABLE cellspacing=2 cellpadding=2 border=1 width="100%"><TR align="left"><TH align="left" align="top" width="25%"><B>File</B></TH><TH align="left"><B>Description</B></TH></TR><TR><TD>altera_ddr_phy.v</TD><TD>A MegaCore<small><sup>®</sup></small> function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.</TD></TR><TR><TD>altera_ddr_phy_bb.v</TD><TD>Verilog HDL black-box file for the MegaCore function variation. Use this file when using a third-party EDA tool to synthesize your design.</TD></TR><TR><TD>altera_ddr_phy.bsf</TD><TD>Quartus<small><sup>®</sup></small> II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor.</TD></TR><TR><TD>altera_ddr_phy_alt_mem_phy_seq_wrapper.vo</TD><TD>Verilog HDL IP functional simulation model</TD></TR><TR><TD>altera_ddr_syn.v</TD><TD>A timing and resource estimation netlist for use in some third-party synthesis tools.</TD></TR><TR><TD>altera_ddr_phy.qip</TD><TD>Contains Quartus II project information for your MegaCore function variation.</TD></TR><TR><TD>altera_ddr_phy.html</TD><TD>The MegaCore function report file.</TD></TR><TR><TD>altera_ddr_phy_alt_mem_phy_seq_wrapper.v</TD><TD>A wrapper file that calls the sequencer file, this file is for compilation.</TD></TR><TR><TD>altera_ddr_phy_alt_mem_phy_seq.vhd</TD><TD>Contains the sequencer used during calibration.</TD></TR><TR><TD>altera_ddr_phy_alt_mem_phy.v</TD><TD>Contains all modules of the ALTMEMPHY variation except for the sequencer.</TD></TR><TR><TD>altera_ddr_phy_alt_mem_phy_pll.v</TD><TD>The PLL megafunction file for your ALTMEMPHY variation.</TD></TR><TR><TD>altera_ddr_phy_pin_assignments.tcl</TD><TD>Contains I/O standard, drive strength, output enable grouping, and termination assignments for your ALTMEMPHY variation. If your top-level design pin names do not match the default pin names or a prefixed version, edit the assignments in this file.</TD></TR><TR><TD>altera_ddr_phy_ddr_pins.tcl</TD><TD>Contains procedures used in the altera_ddr_phy_report_timing.tcl file.</TD></TR><TR><TD>altera_ddr_phy_report_timing.tcl</TD><TD>Script that reports timing for your ALTMEMPHY variation during compilation.</TD></TR><TR><TD>altera_ddr_phy_ddr_timing.sdc</TD><TD>Contains timing constraints for your ALTMEMPHY variation.</TD></TR><TR><TD>altera_ddr_phy_alt_mem_phy_pll.qip</TD><TD>Quartus II IP file for the ALTPLL variation, containing the files associated with the ALTPLL megafunction.</TD></TR><TR><TD>alt_mem_phy_defines.v</TD><TD>Contains constants used in the interface.</TD></TR><TR><TD>altera_ddr_phy.ppf</TD><TD>Pin planner file for your ALTMEMPHY variation.</TD></TR></TABLE></TD></TR><TR><TD><h2>MegaCore Function Variation File Ports</h2><TABLE border=1 cellpadding=2 cellspacing=0 width="75%"><TR align="left"><TH align="left"><B>Name</B></TH><TH align="left"><B>Direction</B></TH><TH align="left"><B>Width</B></TH></TR><TR><TD>pll_ref_clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>global_reset_n</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>soft_reset_n</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>reset_request_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ctl_clk</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ctl_reset_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ctl_dqs_burst</TD><TD>INPUT</TD><TD>2</TD></TR><TR><TD>ctl_wdata_valid</TD><TD>INPUT</TD><TD>2</TD></TR><TR><TD>ctl_wdata</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>ctl_dm</TD><TD>INPUT</TD><TD>4</TD></TR><TR><TD>ctl_wlat</TD><TD>OUTPUT</TD><TD>5</TD></TR><TR><TD>ctl_addr</TD><TD>INPUT</TD><TD>13</TD></TR><TR><TD>ctl_ba</TD><TD>INPUT</TD><TD>2</TD></TR><TR><TD>ctl_cas_n</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_cke</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_cs_n</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_odt</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_ras_n</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_we_n</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_rst_n</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_mem_clk_disable</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_doing_rd</TD><TD>INPUT</TD><TD>2</TD></TR><TR><TD>ctl_rdata</TD><TD>OUTPUT</TD><TD>32</TD></TR><TR><TD>ctl_rdata_valid</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ctl_rlat</TD><TD>OUTPUT</TD><TD>5</TD></TR><TR><TD>ctl_cal_req</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_cal_byte_lane_sel_n</TD><TD>INPUT</TD><TD>2</TD></TR><TR><TD>ctl_cal_success</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ctl_cal_fail</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_addr</TD><TD>OUTPUT</TD><TD>13</TD></TR><TR><TD>mem_ba</TD><TD>OUTPUT</TD><TD>2</TD></TR><TR><TD>mem_cas_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_cke</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_cs_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_dm</TD><TD>OUTPUT</TD><TD>2</TD></TR><TR><TD>mem_odt</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_ras_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_we_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_reset_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_clk</TD><TD>BIDIR</TD><TD>1</TD></TR><TR><TD>mem_clk_n</TD><TD>BIDIR</TD><TD>1</TD></TR><TR><TD>mem_dq</TD><TD>BIDIR</TD><TD>16</TD></TR><TR><TD>mem_dqs</TD><TD>BIDIR</TD><TD>2</TD></TR><TR><TD>mem_dqs_n</TD><TD>BIDIR</TD><TD>2</TD></TR><TR><TD>dbg_clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dbg_reset_n</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dbg_addr</TD><TD>INPUT</TD><TD>13</TD></TR><TR><TD>dbg_wr</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dbg_rd</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dbg_cs</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dbg_wr_data</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>dbg_rd_data</TD><TD>OUTPUT</TD><TD>32</TD></TR><TR><TD>dbg_waitrequest</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>aux_half_rate_clk</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>aux_full_rate_clk</TD><TD>OUTPUT</TD><TD>1</TD></TR></TABLE></TD></TR></TD></TR></TABLE></DIV></BODY></HTML>
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