1 |
12 |
xianfeng |
// megafunction wizard: %altmemphy v9.0%
|
2 |
|
|
// GENERATION: XML
|
3 |
|
|
|
4 |
|
|
// ============================================================
|
5 |
|
|
// Megafunction Name(s):
|
6 |
|
|
// altera_ddr_phy_alt_mem_phy
|
7 |
|
|
// ============================================================
|
8 |
|
|
// Generated by altmemphy 9.0 [Altera, IP Toolbench 1.3.0 Build 235]
|
9 |
|
|
// ************************************************************
|
10 |
|
|
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
11 |
|
|
// ************************************************************
|
12 |
|
|
// Copyright (C) 1991-2009 Altera Corporation
|
13 |
|
|
// Any megafunction design, and related net list (encrypted or decrypted),
|
14 |
|
|
// support information, device programming or simulation file, and any other
|
15 |
|
|
// associated documentation or information provided by Altera or a partner
|
16 |
|
|
// under Altera's Megafunction Partnership Program may be used only to
|
17 |
|
|
// program PLD devices (but not masked PLD devices) from Altera. Any other
|
18 |
|
|
// use of such megafunction design, net list, support information, device
|
19 |
|
|
// programming or simulation file, or any other related documentation or
|
20 |
|
|
// information is prohibited for any other purpose, including, but not
|
21 |
|
|
// limited to modification, reverse engineering, de-compiling, or use with
|
22 |
|
|
// any other silicon devices, unless such use is explicitly licensed under
|
23 |
|
|
// a separate agreement with Altera or a megafunction partner. Title to
|
24 |
|
|
// the intellectual property, including patents, copyrights, trademarks,
|
25 |
|
|
// trade secrets, or maskworks, embodied in any such megafunction design,
|
26 |
|
|
// net list, support information, device programming or simulation file, or
|
27 |
|
|
// any other related documentation or information provided by Altera or a
|
28 |
|
|
// megafunction partner, remains with Altera, the megafunction partner, or
|
29 |
|
|
// their respective licensors. No other licenses, including any licenses
|
30 |
|
|
// needed under any third party's intellectual property, are provided herein.
|
31 |
|
|
|
32 |
|
|
|
33 |
|
|
module altera_ddr_phy (
|
34 |
|
|
pll_ref_clk,
|
35 |
|
|
global_reset_n,
|
36 |
|
|
soft_reset_n,
|
37 |
|
|
ctl_dqs_burst,
|
38 |
|
|
ctl_wdata_valid,
|
39 |
|
|
ctl_wdata,
|
40 |
|
|
ctl_dm,
|
41 |
|
|
ctl_addr,
|
42 |
|
|
ctl_ba,
|
43 |
|
|
ctl_cas_n,
|
44 |
|
|
ctl_cke,
|
45 |
|
|
ctl_cs_n,
|
46 |
|
|
ctl_odt,
|
47 |
|
|
ctl_ras_n,
|
48 |
|
|
ctl_we_n,
|
49 |
|
|
ctl_rst_n,
|
50 |
|
|
ctl_mem_clk_disable,
|
51 |
|
|
ctl_doing_rd,
|
52 |
|
|
ctl_cal_req,
|
53 |
|
|
ctl_cal_byte_lane_sel_n,
|
54 |
|
|
dbg_clk,
|
55 |
|
|
dbg_reset_n,
|
56 |
|
|
dbg_addr,
|
57 |
|
|
dbg_wr,
|
58 |
|
|
dbg_rd,
|
59 |
|
|
dbg_cs,
|
60 |
|
|
dbg_wr_data,
|
61 |
|
|
reset_request_n,
|
62 |
|
|
ctl_clk,
|
63 |
|
|
ctl_reset_n,
|
64 |
|
|
ctl_wlat,
|
65 |
|
|
ctl_rdata,
|
66 |
|
|
ctl_rdata_valid,
|
67 |
|
|
ctl_rlat,
|
68 |
|
|
ctl_cal_success,
|
69 |
|
|
ctl_cal_fail,
|
70 |
|
|
mem_addr,
|
71 |
|
|
mem_ba,
|
72 |
|
|
mem_cas_n,
|
73 |
|
|
mem_cke,
|
74 |
|
|
mem_cs_n,
|
75 |
|
|
mem_dm,
|
76 |
|
|
mem_odt,
|
77 |
|
|
mem_ras_n,
|
78 |
|
|
mem_we_n,
|
79 |
|
|
mem_reset_n,
|
80 |
|
|
dbg_rd_data,
|
81 |
|
|
dbg_waitrequest,
|
82 |
|
|
aux_half_rate_clk,
|
83 |
|
|
aux_full_rate_clk,
|
84 |
|
|
mem_clk,
|
85 |
|
|
mem_clk_n,
|
86 |
|
|
mem_dq,
|
87 |
|
|
mem_dqs,
|
88 |
|
|
mem_dqs_n);
|
89 |
|
|
|
90 |
|
|
|
91 |
|
|
input pll_ref_clk;
|
92 |
|
|
input global_reset_n;
|
93 |
|
|
input soft_reset_n;
|
94 |
|
|
input [1:0] ctl_dqs_burst;
|
95 |
|
|
input [1:0] ctl_wdata_valid;
|
96 |
|
|
input [31:0] ctl_wdata;
|
97 |
|
|
input [3:0] ctl_dm;
|
98 |
|
|
input [12:0] ctl_addr;
|
99 |
|
|
input [1:0] ctl_ba;
|
100 |
|
|
input [0:0] ctl_cas_n;
|
101 |
|
|
input [0:0] ctl_cke;
|
102 |
|
|
input [0:0] ctl_cs_n;
|
103 |
|
|
input [0:0] ctl_odt;
|
104 |
|
|
input [0:0] ctl_ras_n;
|
105 |
|
|
input [0:0] ctl_we_n;
|
106 |
|
|
input [0:0] ctl_rst_n;
|
107 |
|
|
input [0:0] ctl_mem_clk_disable;
|
108 |
|
|
input [1:0] ctl_doing_rd;
|
109 |
|
|
input ctl_cal_req;
|
110 |
|
|
input [1:0] ctl_cal_byte_lane_sel_n;
|
111 |
|
|
input dbg_clk;
|
112 |
|
|
input dbg_reset_n;
|
113 |
|
|
input [12:0] dbg_addr;
|
114 |
|
|
input dbg_wr;
|
115 |
|
|
input dbg_rd;
|
116 |
|
|
input dbg_cs;
|
117 |
|
|
input [31:0] dbg_wr_data;
|
118 |
|
|
output reset_request_n;
|
119 |
|
|
output ctl_clk;
|
120 |
|
|
output ctl_reset_n;
|
121 |
|
|
output [4:0] ctl_wlat;
|
122 |
|
|
output [31:0] ctl_rdata;
|
123 |
|
|
output [0:0] ctl_rdata_valid;
|
124 |
|
|
output [4:0] ctl_rlat;
|
125 |
|
|
output ctl_cal_success;
|
126 |
|
|
output ctl_cal_fail;
|
127 |
|
|
output [12:0] mem_addr;
|
128 |
|
|
output [1:0] mem_ba;
|
129 |
|
|
output mem_cas_n;
|
130 |
|
|
output [0:0] mem_cke;
|
131 |
|
|
output [0:0] mem_cs_n;
|
132 |
|
|
output [1:0] mem_dm;
|
133 |
|
|
output [0:0] mem_odt;
|
134 |
|
|
output mem_ras_n;
|
135 |
|
|
output mem_we_n;
|
136 |
|
|
output mem_reset_n;
|
137 |
|
|
output [31:0] dbg_rd_data;
|
138 |
|
|
output dbg_waitrequest;
|
139 |
|
|
output aux_half_rate_clk;
|
140 |
|
|
output aux_full_rate_clk;
|
141 |
|
|
inout [0:0] mem_clk;
|
142 |
|
|
inout [0:0] mem_clk_n;
|
143 |
|
|
inout [15:0] mem_dq;
|
144 |
|
|
inout [1:0] mem_dqs;
|
145 |
|
|
inout [1:0] mem_dqs_n;
|
146 |
|
|
|
147 |
|
|
|
148 |
|
|
altera_ddr_phy_alt_mem_phy altera_ddr_phy_alt_mem_phy_inst(
|
149 |
|
|
.pll_ref_clk(pll_ref_clk),
|
150 |
|
|
.global_reset_n(global_reset_n),
|
151 |
|
|
.soft_reset_n(soft_reset_n),
|
152 |
|
|
.ctl_dqs_burst(ctl_dqs_burst),
|
153 |
|
|
.ctl_wdata_valid(ctl_wdata_valid),
|
154 |
|
|
.ctl_wdata(ctl_wdata),
|
155 |
|
|
.ctl_dm(ctl_dm),
|
156 |
|
|
.ctl_addr(ctl_addr),
|
157 |
|
|
.ctl_ba(ctl_ba),
|
158 |
|
|
.ctl_cas_n(ctl_cas_n),
|
159 |
|
|
.ctl_cke(ctl_cke),
|
160 |
|
|
.ctl_cs_n(ctl_cs_n),
|
161 |
|
|
.ctl_odt(ctl_odt),
|
162 |
|
|
.ctl_ras_n(ctl_ras_n),
|
163 |
|
|
.ctl_we_n(ctl_we_n),
|
164 |
|
|
.ctl_rst_n(ctl_rst_n),
|
165 |
|
|
.ctl_mem_clk_disable(ctl_mem_clk_disable),
|
166 |
|
|
.ctl_doing_rd(ctl_doing_rd),
|
167 |
|
|
.ctl_cal_req(ctl_cal_req),
|
168 |
|
|
.ctl_cal_byte_lane_sel_n(ctl_cal_byte_lane_sel_n),
|
169 |
|
|
.dbg_clk(dbg_clk),
|
170 |
|
|
.dbg_reset_n(dbg_reset_n),
|
171 |
|
|
.dbg_addr(dbg_addr),
|
172 |
|
|
.dbg_wr(dbg_wr),
|
173 |
|
|
.dbg_rd(dbg_rd),
|
174 |
|
|
.dbg_cs(dbg_cs),
|
175 |
|
|
.dbg_wr_data(dbg_wr_data),
|
176 |
|
|
.reset_request_n(reset_request_n),
|
177 |
|
|
.ctl_clk(ctl_clk),
|
178 |
|
|
.ctl_reset_n(ctl_reset_n),
|
179 |
|
|
.ctl_wlat(ctl_wlat),
|
180 |
|
|
.ctl_rdata(ctl_rdata),
|
181 |
|
|
.ctl_rdata_valid(ctl_rdata_valid),
|
182 |
|
|
.ctl_rlat(ctl_rlat),
|
183 |
|
|
.ctl_cal_success(ctl_cal_success),
|
184 |
|
|
.ctl_cal_fail(ctl_cal_fail),
|
185 |
|
|
.mem_addr(mem_addr),
|
186 |
|
|
.mem_ba(mem_ba),
|
187 |
|
|
.mem_cas_n(mem_cas_n),
|
188 |
|
|
.mem_cke(mem_cke),
|
189 |
|
|
.mem_cs_n(mem_cs_n),
|
190 |
|
|
.mem_dm(mem_dm),
|
191 |
|
|
.mem_odt(mem_odt),
|
192 |
|
|
.mem_ras_n(mem_ras_n),
|
193 |
|
|
.mem_we_n(mem_we_n),
|
194 |
|
|
.mem_reset_n(mem_reset_n),
|
195 |
|
|
.dbg_rd_data(dbg_rd_data),
|
196 |
|
|
.dbg_waitrequest(dbg_waitrequest),
|
197 |
|
|
.aux_half_rate_clk(aux_half_rate_clk),
|
198 |
|
|
.aux_full_rate_clk(aux_full_rate_clk),
|
199 |
|
|
.mem_clk(mem_clk),
|
200 |
|
|
.mem_clk_n(mem_clk_n),
|
201 |
|
|
.mem_dq(mem_dq),
|
202 |
|
|
.mem_dqs(mem_dqs),
|
203 |
|
|
.mem_dqs_n(mem_dqs_n));
|
204 |
|
|
|
205 |
|
|
defparam
|
206 |
|
|
altera_ddr_phy_alt_mem_phy_inst.FAMILY = "Cyclone III",
|
207 |
|
|
altera_ddr_phy_alt_mem_phy_inst.MEM_IF_MEMTYPE = "DDR",
|
208 |
|
|
altera_ddr_phy_alt_mem_phy_inst.DLL_DELAY_BUFFER_MODE = "LOW",
|
209 |
|
|
altera_ddr_phy_alt_mem_phy_inst.DLL_DELAY_CHAIN_LENGTH = 12,
|
210 |
|
|
altera_ddr_phy_alt_mem_phy_inst.DQS_DELAY_CTL_WIDTH = 6,
|
211 |
|
|
altera_ddr_phy_alt_mem_phy_inst.DQS_OUT_MODE = "DELAY_CHAIN2",
|
212 |
|
|
altera_ddr_phy_alt_mem_phy_inst.DQS_PHASE = 6000,
|
213 |
|
|
altera_ddr_phy_alt_mem_phy_inst.DQS_PHASE_SETTING = 2,
|
214 |
|
|
altera_ddr_phy_alt_mem_phy_inst.DWIDTH_RATIO = 2,
|
215 |
|
|
altera_ddr_phy_alt_mem_phy_inst.MEM_IF_DWIDTH = 16,
|
216 |
|
|
altera_ddr_phy_alt_mem_phy_inst.MEM_IF_ADDR_WIDTH = 13,
|
217 |
|
|
altera_ddr_phy_alt_mem_phy_inst.MEM_IF_BANKADDR_WIDTH = 2,
|
218 |
|
|
altera_ddr_phy_alt_mem_phy_inst.MEM_IF_CS_WIDTH = 1,
|
219 |
|
|
altera_ddr_phy_alt_mem_phy_inst.MEM_IF_DM_WIDTH = 2,
|
220 |
|
|
altera_ddr_phy_alt_mem_phy_inst.MEM_IF_DM_PINS_EN = 1,
|
221 |
|
|
altera_ddr_phy_alt_mem_phy_inst.MEM_IF_DQ_PER_DQS = 8,
|
222 |
|
|
altera_ddr_phy_alt_mem_phy_inst.MEM_IF_DQS_WIDTH = 2,
|
223 |
|
|
altera_ddr_phy_alt_mem_phy_inst.MEM_IF_OCT_EN = 0,
|
224 |
|
|
altera_ddr_phy_alt_mem_phy_inst.MEM_IF_CLK_PAIR_COUNT = 1,
|
225 |
|
|
altera_ddr_phy_alt_mem_phy_inst.MEM_IF_CLK_PS = 6667,
|
226 |
|
|
altera_ddr_phy_alt_mem_phy_inst.MEM_IF_CLK_PS_STR = "6667 ps",
|
227 |
|
|
altera_ddr_phy_alt_mem_phy_inst.MEM_IF_MR_0 = 50,
|
228 |
|
|
altera_ddr_phy_alt_mem_phy_inst.MEM_IF_MR_1 = 0,
|
229 |
|
|
altera_ddr_phy_alt_mem_phy_inst.MEM_IF_MR_2 = 0,
|
230 |
|
|
altera_ddr_phy_alt_mem_phy_inst.MEM_IF_MR_3 = 0,
|
231 |
|
|
altera_ddr_phy_alt_mem_phy_inst.PLL_STEPS_PER_CYCLE = 64,
|
232 |
|
|
altera_ddr_phy_alt_mem_phy_inst.SCAN_CLK_DIVIDE_BY = 2,
|
233 |
|
|
altera_ddr_phy_alt_mem_phy_inst.MEM_IF_DQSN_EN = 0,
|
234 |
|
|
altera_ddr_phy_alt_mem_phy_inst.DLL_EXPORT_IMPORT = "EXPORT",
|
235 |
|
|
altera_ddr_phy_alt_mem_phy_inst.MEM_IF_ADDR_CMD_PHASE = 90,
|
236 |
|
|
altera_ddr_phy_alt_mem_phy_inst.RANK_HAS_ADDR_SWAP = 0;
|
237 |
|
|
endmodule
|
238 |
|
|
|
239 |
|
|
// =========================================================
|
240 |
|
|
// altmemphy Wizard Data
|
241 |
|
|
// ===============================
|
242 |
|
|
// DO NOT EDIT FOLLOWING DATA
|
243 |
|
|
// @Altera, IP Toolbench@
|
244 |
|
|
// Warning: If you modify this section, altmemphy Wizard may not be able to reproduce your chosen configuration.
|
245 |
|
|
//
|
246 |
|
|
// Retrieval info: <?xml version="1.0"?>
|
247 |
|
|
// Retrieval info: <MEGACORE title="ALTMEMPHY" version="9.0" build="198" iptb_version="1.3.0 Build 235" format_version="120" >
|
248 |
|
|
// Retrieval info: <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.DDRPHYMVCModel" active_core="altera_ddr_phy_alt_mem_phy" >
|
249 |
|
|
// Retrieval info: <STATIC_SECTION>
|
250 |
|
|
// Retrieval info: <PRIVATES>
|
251 |
|
|
// Retrieval info: <NAMESPACE name = "parameterization">
|
252 |
|
|
// Retrieval info: <PRIVATE name = "pipeline_commands" value="false" type="STRING" enable="1" />
|
253 |
|
|
// Retrieval info: <PRIVATE name = "debug_en" value="false" type="STRING" enable="1" />
|
254 |
|
|
// Retrieval info: <PRIVATE name = "export_debug_port" value="false" type="STRING" enable="1" />
|
255 |
|
|
// Retrieval info: <PRIVATE name = "use_generated_memory_model" value="true" type="STRING" enable="1" />
|
256 |
|
|
// Retrieval info: <PRIVATE name = "dedicated_memory_clk_phase_label" value="Dedicated memory clock phase:" type="STRING" enable="1" />
|
257 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_clk_mhz" value="150.0" type="STRING" enable="1" />
|
258 |
|
|
// Retrieval info: <PRIVATE name = "quartus_project_exists" value="true" type="STRING" enable="1" />
|
259 |
|
|
// Retrieval info: <PRIVATE name = "local_if_drate" value="Full" type="STRING" enable="1" />
|
260 |
|
|
// Retrieval info: <PRIVATE name = "enable_v72_rsu" value="false" type="STRING" enable="1" />
|
261 |
|
|
// Retrieval info: <PRIVATE name = "local_if_clk_mhz_label" value="(150.0 MHz)" type="STRING" enable="1" />
|
262 |
|
|
// Retrieval info: <PRIVATE name = "new_variant" value="false" type="STRING" enable="1" />
|
263 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_memtype" value="DDR SDRAM" type="STRING" enable="1" />
|
264 |
|
|
// Retrieval info: <PRIVATE name = "pll_ref_clk_mhz" value="50.0" type="STRING" enable="1" />
|
265 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_clk_ps_label" value="(6667 ps)" type="STRING" enable="1" />
|
266 |
|
|
// Retrieval info: <PRIVATE name = "family" value="Cyclone III" type="STRING" enable="1" />
|
267 |
|
|
// Retrieval info: <PRIVATE name = "project_family" value="Cyclone III" type="STRING" enable="1" />
|
268 |
|
|
// Retrieval info: <PRIVATE name = "speed_grade" value="6" type="STRING" enable="1" />
|
269 |
|
|
// Retrieval info: <PRIVATE name = "dedicated_memory_clk_phase" value="0" type="STRING" enable="1" />
|
270 |
|
|
// Retrieval info: <PRIVATE name = "pll_ref_clk_ps_label" value="(20000 ps)" type="STRING" enable="1" />
|
271 |
|
|
// Retrieval info: <PRIVATE name = "avalon_burst_length" value="1" type="STRING" enable="1" />
|
272 |
|
|
// Retrieval info: <PRIVATE name = "WIDTH_RATIO" value="4" type="STRING" enable="1" />
|
273 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_pchaddr_bit" value="10" type="STRING" enable="1" />
|
274 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_clk_pair_count" value="1" type="STRING" enable="1" />
|
275 |
|
|
// Retrieval info: <PRIVATE name = "vendor" value="Other" type="STRING" enable="1" />
|
276 |
|
|
// Retrieval info: <PRIVATE name = "chip_or_dimm" value="Discrete Device" type="STRING" enable="1" />
|
277 |
|
|
// Retrieval info: <PRIVATE name = "mem_fmax" value="200.0" type="STRING" enable="1" />
|
278 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_cs_per_dimm" value="1" type="STRING" enable="1" />
|
279 |
|
|
// Retrieval info: <PRIVATE name = "pre_latency_label" value="Fix read latency at:" type="STRING" enable="1" />
|
280 |
|
|
// Retrieval info: <PRIVATE name = "dedicated_memory_clk_en" value="false" type="STRING" enable="1" />
|
281 |
|
|
// Retrieval info: <PRIVATE name = "mirror_addressing" value="0" type="STRING" enable="1" />
|
282 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_bankaddr_width" value="2" type="STRING" enable="1" />
|
283 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_preset_rlat" value="0" type="STRING" enable="1" />
|
284 |
|
|
// Retrieval info: <PRIVATE name = "post_latency_label" value="cycles (0 cycles=minimum latency, non-deterministic)" type="STRING" enable="1" />
|
285 |
|
|
// Retrieval info: <PRIVATE name = "mem_dyn_deskew_en" value="false" type="STRING" enable="1" />
|
286 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_cs_width" value="1" type="STRING" enable="1" />
|
287 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_rowaddr_width" value="13" type="STRING" enable="1" />
|
288 |
|
|
// Retrieval info: <PRIVATE name = "local_if_dwidth_label" value="32" type="STRING" enable="1" />
|
289 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_dm_pins_en" value="Yes" type="STRING" enable="1" />
|
290 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_preset" value="PSC A2S56D40CTP-G5" type="STRING" enable="1" />
|
291 |
|
|
// Retrieval info: <PRIVATE name = "fast_simulation_en" value="FAST" type="STRING" enable="1" />
|
292 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_coladdr_width" value="9" type="STRING" enable="1" />
|
293 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_dq_per_dqs" value="8" type="STRING" enable="1" />
|
294 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_dwidth" value="16" type="STRING" enable="1" />
|
295 |
|
|
// Retrieval info: <PRIVATE name = "mem_tiha_ps" value="600" type="STRING" enable="1" />
|
296 |
|
|
// Retrieval info: <PRIVATE name = "mem_tdsh_ck" value="0.2" type="STRING" enable="1" />
|
297 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_trfc_ns" value="70.0" type="STRING" enable="1" />
|
298 |
|
|
// Retrieval info: <PRIVATE name = "mem_tqh_ck" value="0.36" type="STRING" enable="1" />
|
299 |
|
|
// Retrieval info: <PRIVATE name = "mem_tisa_ps" value="600" type="STRING" enable="1" />
|
300 |
|
|
// Retrieval info: <PRIVATE name = "mem_tdss_ck" value="0.2" type="STRING" enable="1" />
|
301 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_tinit_us" value="200.0" type="STRING" enable="1" />
|
302 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_trcd_ns" value="15.0" type="STRING" enable="1" />
|
303 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_twtr_ck" value="2" type="STRING" enable="1" />
|
304 |
|
|
// Retrieval info: <PRIVATE name = "mem_tdqss_ck" value="0.28" type="STRING" enable="1" />
|
305 |
|
|
// Retrieval info: <PRIVATE name = "mem_tqhs_ps" value="500" type="STRING" enable="1" />
|
306 |
|
|
// Retrieval info: <PRIVATE name = "mem_tdsa_ps" value="400" type="STRING" enable="1" />
|
307 |
|
|
// Retrieval info: <PRIVATE name = "mem_tac_ps" value="700" type="STRING" enable="1" />
|
308 |
|
|
// Retrieval info: <PRIVATE name = "mem_tdha_ps" value="400" type="STRING" enable="1" />
|
309 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_tras_ns" value="40.0" type="STRING" enable="1" />
|
310 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_twr_ns" value="15.0" type="STRING" enable="1" />
|
311 |
|
|
// Retrieval info: <PRIVATE name = "mem_tdqsck_ps" value="550" type="STRING" enable="1" />
|
312 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_trp_ns" value="15.0" type="STRING" enable="1" />
|
313 |
|
|
// Retrieval info: <PRIVATE name = "mem_tdqsq_ps" value="400" type="STRING" enable="1" />
|
314 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_tmrd_ns" value="10.0" type="STRING" enable="1" />
|
315 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_trefi_us" value="7.0" type="STRING" enable="1" />
|
316 |
|
|
// Retrieval info: <PRIVATE name = "mem_tcl" value="3.0" type="STRING" enable="1" />
|
317 |
|
|
// Retrieval info: <PRIVATE name = "mem_tcl_40_fmax" value="533.0" type="STRING" enable="1" />
|
318 |
|
|
// Retrieval info: <PRIVATE name = "mem_odt" value="Disabled" type="STRING" enable="1" />
|
319 |
|
|
// Retrieval info: <PRIVATE name = "mem_dll_en" value="Yes" type="STRING" enable="1" />
|
320 |
|
|
// Retrieval info: <PRIVATE name = "ac_phase" value="90" type="STRING" enable="1" />
|
321 |
|
|
// Retrieval info: <PRIVATE name = "mem_drv_str" value="Normal" type="STRING" enable="1" />
|
322 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_oct_en" value="false" type="STRING" enable="1" />
|
323 |
|
|
// Retrieval info: <PRIVATE name = "input_period" value="0" type="STRING" enable="1" />
|
324 |
|
|
// Retrieval info: <PRIVATE name = "mem_tcl_60_fmax" value="533.0" type="STRING" enable="1" />
|
325 |
|
|
// Retrieval info: <PRIVATE name = "board_skew_ps" value="20" type="STRING" enable="1" />
|
326 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_dqsn_en" value="false" type="STRING" enable="1" />
|
327 |
|
|
// Retrieval info: <PRIVATE name = "dll_external" value="false" type="STRING" enable="1" />
|
328 |
|
|
// Retrieval info: <PRIVATE name = "mem_tcl_15_fmax" value="533.0" type="STRING" enable="1" />
|
329 |
|
|
// Retrieval info: <PRIVATE name = "mem_tcl_30_fmax" value="200.0" type="STRING" enable="1" />
|
330 |
|
|
// Retrieval info: <PRIVATE name = "mem_bl" value="4" type="STRING" enable="1" />
|
331 |
|
|
// Retrieval info: <PRIVATE name = "ac_clk_select" value="90" type="STRING" enable="1" />
|
332 |
|
|
// Retrieval info: <PRIVATE name = "mem_tcl_50_fmax" value="533.0" type="STRING" enable="1" />
|
333 |
|
|
// Retrieval info: <PRIVATE name = "mem_tcl_25_fmax" value="200.0" type="STRING" enable="1" />
|
334 |
|
|
// Retrieval info: <PRIVATE name = "mem_tcl_20_fmax" value="133.333" type="STRING" enable="1" />
|
335 |
|
|
// Retrieval info: <PRIVATE name = "pll_reconfig_ports_en" value="false" type="STRING" enable="1" />
|
336 |
|
|
// Retrieval info: <PRIVATE name = "mem_btype" value="Sequential" type="STRING" enable="1" />
|
337 |
|
|
// Retrieval info: <PRIVATE name = "ctl_ecc_en" value="false" type="STRING" enable="1" />
|
338 |
|
|
// Retrieval info: <PRIVATE name = "user_refresh_en" value="false" type="STRING" enable="1" />
|
339 |
|
|
// Retrieval info: <PRIVATE name = "local_if_type_avalon" value="true" type="STRING" enable="1" />
|
340 |
|
|
// Retrieval info: <PRIVATE name = "ctl_self_refresh_en" value="false" type="STRING" enable="1" />
|
341 |
|
|
// Retrieval info: <PRIVATE name = "clk_source_sharing_en" value="false" type="STRING" enable="1" />
|
342 |
|
|
// Retrieval info: <PRIVATE name = "phy_if_type_afi" value="true" type="STRING" enable="1" />
|
343 |
|
|
// Retrieval info: <PRIVATE name = "ctl_autopch_en" value="false" type="STRING" enable="1" />
|
344 |
|
|
// Retrieval info: <PRIVATE name = "shared_sys_clk_source" value="XX" type="STRING" enable="1" />
|
345 |
|
|
// Retrieval info: <PRIVATE name = "ref_clk_source" value="XX" type="STRING" enable="1" />
|
346 |
|
|
// Retrieval info: <PRIVATE name = "ctl_powerdn_en" value="false" type="STRING" enable="1" />
|
347 |
|
|
// Retrieval info: <PRIVATE name = "tool_context" value="STANDALONE" type="STRING" enable="1" />
|
348 |
|
|
// Retrieval info: <PRIVATE name = "mem_srtr" value="Normal" type="STRING" enable="1" />
|
349 |
|
|
// Retrieval info: <PRIVATE name = "mem_mpr_loc" value="Predefined Pattern" type="STRING" enable="1" />
|
350 |
|
|
// Retrieval info: <PRIVATE name = "dss_tinit_rst_us" value="200.0" type="STRING" enable="1" />
|
351 |
|
|
// Retrieval info: <PRIVATE name = "mem_tcl_90_fmax" value="400.0" type="STRING" enable="1" />
|
352 |
|
|
// Retrieval info: <PRIVATE name = "mem_rtt_wr" value="Dynamic ODT off" type="STRING" enable="1" />
|
353 |
|
|
// Retrieval info: <PRIVATE name = "mem_tcl_100_fmax" value="400.0" type="STRING" enable="1" />
|
354 |
|
|
// Retrieval info: <PRIVATE name = "mem_pasr" value="Full Array" type="STRING" enable="1" />
|
355 |
|
|
// Retrieval info: <PRIVATE name = "mem_asrm" value="Manual SR Reference (SRT)" type="STRING" enable="1" />
|
356 |
|
|
// Retrieval info: <PRIVATE name = "mem_mpr_oper" value="Predefined Pattern" type="STRING" enable="1" />
|
357 |
|
|
// Retrieval info: <PRIVATE name = "mem_tcl_80_fmax" value="400.0" type="STRING" enable="1" />
|
358 |
|
|
// Retrieval info: <PRIVATE name = "mem_drv_impedance" value="RZQ/7" type="STRING" enable="1" />
|
359 |
|
|
// Retrieval info: <PRIVATE name = "mem_rtt_nom" value="ODT Disabled" type="STRING" enable="1" />
|
360 |
|
|
// Retrieval info: <PRIVATE name = "mem_tcl_70_fmax" value="400.0" type="STRING" enable="1" />
|
361 |
|
|
// Retrieval info: <PRIVATE name = "mem_wtcl" value="5.0" type="STRING" enable="1" />
|
362 |
|
|
// Retrieval info: <PRIVATE name = "mem_dll_pch" value="Fast Exit" type="STRING" enable="1" />
|
363 |
|
|
// Retrieval info: <PRIVATE name = "mem_atcl" value="Disabled" type="STRING" enable="1" />
|
364 |
|
|
// Retrieval info: </NAMESPACE>
|
365 |
|
|
// Retrieval info: <NAMESPACE name = "simgen">
|
366 |
|
|
// Retrieval info: <PRIVATE name = "use_alt_top" value="1" type="STRING" enable="1" />
|
367 |
|
|
// Retrieval info: <PRIVATE name = "alt_top" value="altera_ddr_phy_alt_mem_phy_seq_wrapper" type="STRING" enable="1" />
|
368 |
|
|
// Retrieval info: <PRIVATE name = "family" value="Cyclone III" type="STRING" enable="1" />
|
369 |
|
|
// Retrieval info: <PRIVATE name = "filename" value="altera_ddr_phy_alt_mem_phy_seq_wrapper.vo" type="STRING" enable="1" />
|
370 |
|
|
// Retrieval info: </NAMESPACE>
|
371 |
|
|
// Retrieval info: <NAMESPACE name = "simgen2">
|
372 |
|
|
// Retrieval info: <PRIVATE name = "family" value="Cyclone III" type="STRING" enable="1" />
|
373 |
|
|
// Retrieval info: <PRIVATE name = "command" value="--simgen_arbitrary_blackbox=+altera_ddr_phy_alt_mem_phy_seq_wrapper;+altera_ddr_phy_alt_mem_phy_reconfig;+altera_ddr_phy_alt_mem_phy_pll;+altera_ddr_phy_alt_mem_phy_delay --ini=simgen_tri_bus_opt=on" type="STRING" enable="1" />
|
374 |
|
|
// Retrieval info: <PRIVATE name = "parameter" value="SIMGEN_INITIALIZATION_FILE=/opt/workspace/xzeng/esig/trunk/or1k_soc/rtl/altera_ddr_ctrl/altera_ddr_phy_simgen_init.txt" type="STRING" enable="1" />
|
375 |
|
|
// Retrieval info: </NAMESPACE>
|
376 |
|
|
// Retrieval info: <NAMESPACE name = "simgen_enable">
|
377 |
|
|
// Retrieval info: <PRIVATE name = "language" value="Verilog HDL" type="STRING" enable="1" />
|
378 |
|
|
// Retrieval info: <PRIVATE name = "enabled" value="1" type="STRING" enable="1" />
|
379 |
|
|
// Retrieval info: </NAMESPACE>
|
380 |
|
|
// Retrieval info: <NAMESPACE name = "greybox">
|
381 |
|
|
// Retrieval info: <PRIVATE name = "gb_enabled" value="1" type="STRING" enable="1" />
|
382 |
|
|
// Retrieval info: <PRIVATE name = "use_alt_top" value="true" type="STRING" enable="1" />
|
383 |
|
|
// Retrieval info: <PRIVATE name = "alt_top" value="altera_ddr" type="STRING" enable="1" />
|
384 |
|
|
// Retrieval info: <PRIVATE name = "gb_extra_libdirs" value="/opt/workspace/xzeng/esig/trunk/or1k_soc/rtl/altera_ddr_ctrl/" type="STRING" enable="1" />
|
385 |
|
|
// Retrieval info: <PRIVATE name = "filename" value="altera_ddr_syn.v" type="STRING" enable="1" />
|
386 |
|
|
// Retrieval info: </NAMESPACE>
|
387 |
|
|
// Retrieval info: <NAMESPACE name = "qip">
|
388 |
|
|
// Retrieval info: <PRIVATE name = "gx_libs" value="1" type="STRING" enable="1" />
|
389 |
|
|
// Retrieval info: </NAMESPACE>
|
390 |
|
|
// Retrieval info: <NAMESPACE name = "serializer"/>
|
391 |
|
|
// Retrieval info: <NAMESPACE name = "quartus_settings">
|
392 |
|
|
// Retrieval info: <PRIVATE name = "DEVICE" value="EP3C25F324C6" type="STRING" enable="1" />
|
393 |
|
|
// Retrieval info: <PRIVATE name = "FAMILY" value="Cyclone III" type="STRING" enable="1" />
|
394 |
|
|
// Retrieval info: <PRIVATE name = "WEB_BROWSER" value="/usr/bin/firefox" type="STRING" enable="1" />
|
395 |
|
|
// Retrieval info: <PRIVATE name = "LICENSE_FILE" value="/opt/altera9.0/license.dat" type="STRING" enable="1" />
|
396 |
|
|
// Retrieval info: </NAMESPACE>
|
397 |
|
|
// Retrieval info: </PRIVATES>
|
398 |
|
|
// Retrieval info: <FILES/>
|
399 |
|
|
// Retrieval info: <PORTS/>
|
400 |
|
|
// Retrieval info: <LIBRARIES/>
|
401 |
|
|
// Retrieval info: </STATIC_SECTION>
|
402 |
|
|
// Retrieval info: </NETLIST_SECTION>
|
403 |
|
|
// Retrieval info: </MEGACORE>
|
404 |
|
|
// =========================================================
|
405 |
|
|
// IPFS_FILES: altera_ddr_phy_alt_mem_phy_seq_wrapper.vo;
|
406 |
|
|
// =========================================================
|