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xianfeng |
// megafunction wizard: %altmemphy v9.0%
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// GENERATION: XML
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// ============================================================
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// Megafunction Name(s):
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// altera_ddr_phy_alt_mem_phy
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// ============================================================
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// Generated by altmemphy 9.0 [Altera, IP Toolbench 1.3.0 Build 235]
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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// ************************************************************
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// Copyright (C) 1991-2009 Altera Corporation
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// Any megafunction design, and related net list (encrypted or decrypted),
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// support information, device programming or simulation file, and any other
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// associated documentation or information provided by Altera or a partner
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// under Altera's Megafunction Partnership Program may be used only to
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// program PLD devices (but not masked PLD devices) from Altera. Any other
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// use of such megafunction design, net list, support information, device
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// programming or simulation file, or any other related documentation or
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// information is prohibited for any other purpose, including, but not
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// limited to modification, reverse engineering, de-compiling, or use with
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// any other silicon devices, unless such use is explicitly licensed under
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// a separate agreement with Altera or a megafunction partner. Title to
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// the intellectual property, including patents, copyrights, trademarks,
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// trade secrets, or maskworks, embodied in any such megafunction design,
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// net list, support information, device programming or simulation file, or
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// any other related documentation or information provided by Altera or a
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// megafunction partner, remains with Altera, the megafunction partner, or
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// their respective licensors. No other licenses, including any licenses
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// needed under any third party's intellectual property, are provided herein.
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module altera_ddr_phy (
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pll_ref_clk,
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global_reset_n,
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soft_reset_n,
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ctl_dqs_burst,
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ctl_wdata_valid,
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ctl_wdata,
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ctl_dm,
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ctl_addr,
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ctl_ba,
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ctl_cas_n,
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ctl_cke,
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ctl_cs_n,
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ctl_odt,
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ctl_ras_n,
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ctl_we_n,
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ctl_rst_n,
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ctl_mem_clk_disable,
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ctl_doing_rd,
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ctl_cal_req,
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ctl_cal_byte_lane_sel_n,
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dbg_clk,
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dbg_reset_n,
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dbg_addr,
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dbg_wr,
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dbg_rd,
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dbg_cs,
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dbg_wr_data,
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reset_request_n,
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ctl_clk,
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ctl_reset_n,
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ctl_wlat,
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ctl_rdata,
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ctl_rdata_valid,
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ctl_rlat,
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ctl_cal_success,
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ctl_cal_fail,
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mem_addr,
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mem_ba,
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mem_cas_n,
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mem_cke,
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mem_cs_n,
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mem_dm,
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mem_odt,
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mem_ras_n,
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mem_we_n,
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mem_reset_n,
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dbg_rd_data,
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dbg_waitrequest,
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aux_half_rate_clk,
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aux_full_rate_clk,
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mem_clk,
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mem_clk_n,
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mem_dq,
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mem_dqs,
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mem_dqs_n);
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input pll_ref_clk;
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input global_reset_n;
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input soft_reset_n;
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input [1:0] ctl_dqs_burst;
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input [1:0] ctl_wdata_valid;
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input [31:0] ctl_wdata;
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input [3:0] ctl_dm;
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input [12:0] ctl_addr;
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input [1:0] ctl_ba;
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input [0:0] ctl_cas_n;
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input [0:0] ctl_cke;
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input [0:0] ctl_cs_n;
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input [0:0] ctl_odt;
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input [0:0] ctl_ras_n;
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input [0:0] ctl_we_n;
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input [0:0] ctl_rst_n;
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input [0:0] ctl_mem_clk_disable;
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input [1:0] ctl_doing_rd;
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input ctl_cal_req;
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input [1:0] ctl_cal_byte_lane_sel_n;
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input dbg_clk;
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input dbg_reset_n;
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input [12:0] dbg_addr;
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input dbg_wr;
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input dbg_rd;
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input dbg_cs;
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input [31:0] dbg_wr_data;
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output reset_request_n;
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output ctl_clk;
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output ctl_reset_n;
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output [4:0] ctl_wlat;
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output [31:0] ctl_rdata;
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output [0:0] ctl_rdata_valid;
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output [4:0] ctl_rlat;
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output ctl_cal_success;
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output ctl_cal_fail;
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output [12:0] mem_addr;
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output [1:0] mem_ba;
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output mem_cas_n;
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output [0:0] mem_cke;
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output [0:0] mem_cs_n;
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output [1:0] mem_dm;
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output [0:0] mem_odt;
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output mem_ras_n;
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output mem_we_n;
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output mem_reset_n;
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output [31:0] dbg_rd_data;
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output dbg_waitrequest;
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output aux_half_rate_clk;
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output aux_full_rate_clk;
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inout [0:0] mem_clk;
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inout [0:0] mem_clk_n;
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inout [15:0] mem_dq;
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inout [1:0] mem_dqs;
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inout [1:0] mem_dqs_n;
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altera_ddr_phy_alt_mem_phy altera_ddr_phy_alt_mem_phy_inst(
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.pll_ref_clk(pll_ref_clk),
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.global_reset_n(global_reset_n),
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.soft_reset_n(soft_reset_n),
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.ctl_dqs_burst(ctl_dqs_burst),
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.ctl_wdata_valid(ctl_wdata_valid),
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.ctl_wdata(ctl_wdata),
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.ctl_dm(ctl_dm),
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.ctl_addr(ctl_addr),
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.ctl_ba(ctl_ba),
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.ctl_cas_n(ctl_cas_n),
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.ctl_cke(ctl_cke),
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.ctl_cs_n(ctl_cs_n),
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.ctl_odt(ctl_odt),
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.ctl_ras_n(ctl_ras_n),
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.ctl_we_n(ctl_we_n),
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.ctl_rst_n(ctl_rst_n),
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.ctl_mem_clk_disable(ctl_mem_clk_disable),
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.ctl_doing_rd(ctl_doing_rd),
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.ctl_cal_req(ctl_cal_req),
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.ctl_cal_byte_lane_sel_n(ctl_cal_byte_lane_sel_n),
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.dbg_clk(dbg_clk),
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.dbg_reset_n(dbg_reset_n),
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.dbg_addr(dbg_addr),
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.dbg_wr(dbg_wr),
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.dbg_rd(dbg_rd),
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.dbg_cs(dbg_cs),
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.dbg_wr_data(dbg_wr_data),
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.reset_request_n(reset_request_n),
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.ctl_clk(ctl_clk),
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.ctl_reset_n(ctl_reset_n),
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.ctl_wlat(ctl_wlat),
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.ctl_rdata(ctl_rdata),
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.ctl_rdata_valid(ctl_rdata_valid),
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.ctl_rlat(ctl_rlat),
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.ctl_cal_success(ctl_cal_success),
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.ctl_cal_fail(ctl_cal_fail),
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.mem_addr(mem_addr),
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.mem_ba(mem_ba),
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.mem_cas_n(mem_cas_n),
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.mem_cke(mem_cke),
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.mem_cs_n(mem_cs_n),
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.mem_dm(mem_dm),
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.mem_odt(mem_odt),
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.mem_ras_n(mem_ras_n),
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.mem_we_n(mem_we_n),
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.mem_reset_n(mem_reset_n),
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.dbg_rd_data(dbg_rd_data),
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.dbg_waitrequest(dbg_waitrequest),
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.aux_half_rate_clk(aux_half_rate_clk),
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.aux_full_rate_clk(aux_full_rate_clk),
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.mem_clk(mem_clk),
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.mem_clk_n(mem_clk_n),
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.mem_dq(mem_dq),
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.mem_dqs(mem_dqs),
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.mem_dqs_n(mem_dqs_n));
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defparam
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altera_ddr_phy_alt_mem_phy_inst.FAMILY = "Cyclone III",
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altera_ddr_phy_alt_mem_phy_inst.MEM_IF_MEMTYPE = "DDR",
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altera_ddr_phy_alt_mem_phy_inst.DLL_DELAY_BUFFER_MODE = "LOW",
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altera_ddr_phy_alt_mem_phy_inst.DLL_DELAY_CHAIN_LENGTH = 12,
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altera_ddr_phy_alt_mem_phy_inst.DQS_DELAY_CTL_WIDTH = 6,
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altera_ddr_phy_alt_mem_phy_inst.DQS_OUT_MODE = "DELAY_CHAIN2",
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altera_ddr_phy_alt_mem_phy_inst.DQS_PHASE = 6000,
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altera_ddr_phy_alt_mem_phy_inst.DQS_PHASE_SETTING = 2,
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altera_ddr_phy_alt_mem_phy_inst.DWIDTH_RATIO = 2,
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altera_ddr_phy_alt_mem_phy_inst.MEM_IF_DWIDTH = 16,
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altera_ddr_phy_alt_mem_phy_inst.MEM_IF_ADDR_WIDTH = 13,
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altera_ddr_phy_alt_mem_phy_inst.MEM_IF_BANKADDR_WIDTH = 2,
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altera_ddr_phy_alt_mem_phy_inst.MEM_IF_CS_WIDTH = 1,
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altera_ddr_phy_alt_mem_phy_inst.MEM_IF_DM_WIDTH = 2,
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altera_ddr_phy_alt_mem_phy_inst.MEM_IF_DM_PINS_EN = 1,
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altera_ddr_phy_alt_mem_phy_inst.MEM_IF_DQ_PER_DQS = 8,
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altera_ddr_phy_alt_mem_phy_inst.MEM_IF_DQS_WIDTH = 2,
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altera_ddr_phy_alt_mem_phy_inst.MEM_IF_OCT_EN = 0,
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altera_ddr_phy_alt_mem_phy_inst.MEM_IF_CLK_PAIR_COUNT = 1,
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altera_ddr_phy_alt_mem_phy_inst.MEM_IF_CLK_PS = 6667,
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altera_ddr_phy_alt_mem_phy_inst.MEM_IF_CLK_PS_STR = "6667 ps",
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altera_ddr_phy_alt_mem_phy_inst.MEM_IF_MR_0 = 50,
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altera_ddr_phy_alt_mem_phy_inst.MEM_IF_MR_1 = 0,
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altera_ddr_phy_alt_mem_phy_inst.MEM_IF_MR_2 = 0,
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altera_ddr_phy_alt_mem_phy_inst.MEM_IF_MR_3 = 0,
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altera_ddr_phy_alt_mem_phy_inst.PLL_STEPS_PER_CYCLE = 64,
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altera_ddr_phy_alt_mem_phy_inst.SCAN_CLK_DIVIDE_BY = 2,
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altera_ddr_phy_alt_mem_phy_inst.MEM_IF_DQSN_EN = 0,
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altera_ddr_phy_alt_mem_phy_inst.DLL_EXPORT_IMPORT = "EXPORT",
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altera_ddr_phy_alt_mem_phy_inst.MEM_IF_ADDR_CMD_PHASE = 90,
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altera_ddr_phy_alt_mem_phy_inst.RANK_HAS_ADDR_SWAP = 0;
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endmodule
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// =========================================================
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// altmemphy Wizard Data
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// ===============================
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// DO NOT EDIT FOLLOWING DATA
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// @Altera, IP Toolbench@
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// Warning: If you modify this section, altmemphy Wizard may not be able to reproduce your chosen configuration.
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//
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// Retrieval info: <?xml version="1.0"?>
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// Retrieval info: <MEGACORE title="ALTMEMPHY" version="9.0" build="198" iptb_version="1.3.0 Build 235" format_version="120" >
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// Retrieval info: <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.DDRPHYMVCModel" active_core="altera_ddr_phy_alt_mem_phy" >
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// Retrieval info: <STATIC_SECTION>
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// Retrieval info: <PRIVATES>
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// Retrieval info: <NAMESPACE name = "parameterization">
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// Retrieval info: <PRIVATE name = "pipeline_commands" value="false" type="STRING" enable="1" />
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// Retrieval info: <PRIVATE name = "debug_en" value="false" type="STRING" enable="1" />
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// Retrieval info: <PRIVATE name = "export_debug_port" value="false" type="STRING" enable="1" />
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// Retrieval info: <PRIVATE name = "use_generated_memory_model" value="true" type="STRING" enable="1" />
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// Retrieval info: <PRIVATE name = "dedicated_memory_clk_phase_label" value="Dedicated memory clock phase:" type="STRING" enable="1" />
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// Retrieval info: <PRIVATE name = "mem_if_clk_mhz" value="150.0" type="STRING" enable="1" />
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// Retrieval info: <PRIVATE name = "quartus_project_exists" value="true" type="STRING" enable="1" />
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// Retrieval info: <PRIVATE name = "local_if_drate" value="Full" type="STRING" enable="1" />
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// Retrieval info: <PRIVATE name = "enable_v72_rsu" value="false" type="STRING" enable="1" />
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// Retrieval info: <PRIVATE name = "local_if_clk_mhz_label" value="(150.0 MHz)" type="STRING" enable="1" />
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// Retrieval info: <PRIVATE name = "new_variant" value="false" type="STRING" enable="1" />
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// Retrieval info: <PRIVATE name = "mem_if_memtype" value="DDR SDRAM" type="STRING" enable="1" />
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// Retrieval info: <PRIVATE name = "pll_ref_clk_mhz" value="50.0" type="STRING" enable="1" />
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// Retrieval info: <PRIVATE name = "mem_if_clk_ps_label" value="(6667 ps)" type="STRING" enable="1" />
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// Retrieval info: <PRIVATE name = "family" value="Cyclone III" type="STRING" enable="1" />
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// Retrieval info: <PRIVATE name = "project_family" value="Cyclone III" type="STRING" enable="1" />
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// Retrieval info: <PRIVATE name = "speed_grade" value="6" type="STRING" enable="1" />
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// Retrieval info: <PRIVATE name = "dedicated_memory_clk_phase" value="0" type="STRING" enable="1" />
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// Retrieval info: <PRIVATE name = "pll_ref_clk_ps_label" value="(20000 ps)" type="STRING" enable="1" />
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// Retrieval info: <PRIVATE name = "avalon_burst_length" value="1" type="STRING" enable="1" />
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// Retrieval info: <PRIVATE name = "WIDTH_RATIO" value="4" type="STRING" enable="1" />
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// Retrieval info: <PRIVATE name = "mem_if_pchaddr_bit" value="10" type="STRING" enable="1" />
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// Retrieval info: <PRIVATE name = "mem_if_clk_pair_count" value="1" type="STRING" enable="1" />
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// Retrieval info: <PRIVATE name = "vendor" value="Other" type="STRING" enable="1" />
|
| 276 |
|
|
// Retrieval info: <PRIVATE name = "chip_or_dimm" value="Discrete Device" type="STRING" enable="1" />
|
| 277 |
|
|
// Retrieval info: <PRIVATE name = "mem_fmax" value="200.0" type="STRING" enable="1" />
|
| 278 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_cs_per_dimm" value="1" type="STRING" enable="1" />
|
| 279 |
|
|
// Retrieval info: <PRIVATE name = "pre_latency_label" value="Fix read latency at:" type="STRING" enable="1" />
|
| 280 |
|
|
// Retrieval info: <PRIVATE name = "dedicated_memory_clk_en" value="false" type="STRING" enable="1" />
|
| 281 |
|
|
// Retrieval info: <PRIVATE name = "mirror_addressing" value="0" type="STRING" enable="1" />
|
| 282 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_bankaddr_width" value="2" type="STRING" enable="1" />
|
| 283 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_preset_rlat" value="0" type="STRING" enable="1" />
|
| 284 |
|
|
// Retrieval info: <PRIVATE name = "post_latency_label" value="cycles (0 cycles=minimum latency, non-deterministic)" type="STRING" enable="1" />
|
| 285 |
|
|
// Retrieval info: <PRIVATE name = "mem_dyn_deskew_en" value="false" type="STRING" enable="1" />
|
| 286 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_cs_width" value="1" type="STRING" enable="1" />
|
| 287 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_rowaddr_width" value="13" type="STRING" enable="1" />
|
| 288 |
|
|
// Retrieval info: <PRIVATE name = "local_if_dwidth_label" value="32" type="STRING" enable="1" />
|
| 289 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_dm_pins_en" value="Yes" type="STRING" enable="1" />
|
| 290 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_preset" value="PSC A2S56D40CTP-G5" type="STRING" enable="1" />
|
| 291 |
|
|
// Retrieval info: <PRIVATE name = "fast_simulation_en" value="FAST" type="STRING" enable="1" />
|
| 292 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_coladdr_width" value="9" type="STRING" enable="1" />
|
| 293 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_dq_per_dqs" value="8" type="STRING" enable="1" />
|
| 294 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_dwidth" value="16" type="STRING" enable="1" />
|
| 295 |
|
|
// Retrieval info: <PRIVATE name = "mem_tiha_ps" value="600" type="STRING" enable="1" />
|
| 296 |
|
|
// Retrieval info: <PRIVATE name = "mem_tdsh_ck" value="0.2" type="STRING" enable="1" />
|
| 297 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_trfc_ns" value="70.0" type="STRING" enable="1" />
|
| 298 |
|
|
// Retrieval info: <PRIVATE name = "mem_tqh_ck" value="0.36" type="STRING" enable="1" />
|
| 299 |
|
|
// Retrieval info: <PRIVATE name = "mem_tisa_ps" value="600" type="STRING" enable="1" />
|
| 300 |
|
|
// Retrieval info: <PRIVATE name = "mem_tdss_ck" value="0.2" type="STRING" enable="1" />
|
| 301 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_tinit_us" value="200.0" type="STRING" enable="1" />
|
| 302 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_trcd_ns" value="15.0" type="STRING" enable="1" />
|
| 303 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_twtr_ck" value="2" type="STRING" enable="1" />
|
| 304 |
|
|
// Retrieval info: <PRIVATE name = "mem_tdqss_ck" value="0.28" type="STRING" enable="1" />
|
| 305 |
|
|
// Retrieval info: <PRIVATE name = "mem_tqhs_ps" value="500" type="STRING" enable="1" />
|
| 306 |
|
|
// Retrieval info: <PRIVATE name = "mem_tdsa_ps" value="400" type="STRING" enable="1" />
|
| 307 |
|
|
// Retrieval info: <PRIVATE name = "mem_tac_ps" value="700" type="STRING" enable="1" />
|
| 308 |
|
|
// Retrieval info: <PRIVATE name = "mem_tdha_ps" value="400" type="STRING" enable="1" />
|
| 309 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_tras_ns" value="40.0" type="STRING" enable="1" />
|
| 310 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_twr_ns" value="15.0" type="STRING" enable="1" />
|
| 311 |
|
|
// Retrieval info: <PRIVATE name = "mem_tdqsck_ps" value="550" type="STRING" enable="1" />
|
| 312 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_trp_ns" value="15.0" type="STRING" enable="1" />
|
| 313 |
|
|
// Retrieval info: <PRIVATE name = "mem_tdqsq_ps" value="400" type="STRING" enable="1" />
|
| 314 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_tmrd_ns" value="10.0" type="STRING" enable="1" />
|
| 315 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_trefi_us" value="7.0" type="STRING" enable="1" />
|
| 316 |
|
|
// Retrieval info: <PRIVATE name = "mem_tcl" value="3.0" type="STRING" enable="1" />
|
| 317 |
|
|
// Retrieval info: <PRIVATE name = "mem_tcl_40_fmax" value="533.0" type="STRING" enable="1" />
|
| 318 |
|
|
// Retrieval info: <PRIVATE name = "mem_odt" value="Disabled" type="STRING" enable="1" />
|
| 319 |
|
|
// Retrieval info: <PRIVATE name = "mem_dll_en" value="Yes" type="STRING" enable="1" />
|
| 320 |
|
|
// Retrieval info: <PRIVATE name = "ac_phase" value="90" type="STRING" enable="1" />
|
| 321 |
|
|
// Retrieval info: <PRIVATE name = "mem_drv_str" value="Normal" type="STRING" enable="1" />
|
| 322 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_oct_en" value="false" type="STRING" enable="1" />
|
| 323 |
|
|
// Retrieval info: <PRIVATE name = "input_period" value="0" type="STRING" enable="1" />
|
| 324 |
|
|
// Retrieval info: <PRIVATE name = "mem_tcl_60_fmax" value="533.0" type="STRING" enable="1" />
|
| 325 |
|
|
// Retrieval info: <PRIVATE name = "board_skew_ps" value="20" type="STRING" enable="1" />
|
| 326 |
|
|
// Retrieval info: <PRIVATE name = "mem_if_dqsn_en" value="false" type="STRING" enable="1" />
|
| 327 |
|
|
// Retrieval info: <PRIVATE name = "dll_external" value="false" type="STRING" enable="1" />
|
| 328 |
|
|
// Retrieval info: <PRIVATE name = "mem_tcl_15_fmax" value="533.0" type="STRING" enable="1" />
|
| 329 |
|
|
// Retrieval info: <PRIVATE name = "mem_tcl_30_fmax" value="200.0" type="STRING" enable="1" />
|
| 330 |
|
|
// Retrieval info: <PRIVATE name = "mem_bl" value="4" type="STRING" enable="1" />
|
| 331 |
|
|
// Retrieval info: <PRIVATE name = "ac_clk_select" value="90" type="STRING" enable="1" />
|
| 332 |
|
|
// Retrieval info: <PRIVATE name = "mem_tcl_50_fmax" value="533.0" type="STRING" enable="1" />
|
| 333 |
|
|
// Retrieval info: <PRIVATE name = "mem_tcl_25_fmax" value="200.0" type="STRING" enable="1" />
|
| 334 |
|
|
// Retrieval info: <PRIVATE name = "mem_tcl_20_fmax" value="133.333" type="STRING" enable="1" />
|
| 335 |
|
|
// Retrieval info: <PRIVATE name = "pll_reconfig_ports_en" value="false" type="STRING" enable="1" />
|
| 336 |
|
|
// Retrieval info: <PRIVATE name = "mem_btype" value="Sequential" type="STRING" enable="1" />
|
| 337 |
|
|
// Retrieval info: <PRIVATE name = "ctl_ecc_en" value="false" type="STRING" enable="1" />
|
| 338 |
|
|
// Retrieval info: <PRIVATE name = "user_refresh_en" value="false" type="STRING" enable="1" />
|
| 339 |
|
|
// Retrieval info: <PRIVATE name = "local_if_type_avalon" value="true" type="STRING" enable="1" />
|
| 340 |
|
|
// Retrieval info: <PRIVATE name = "ctl_self_refresh_en" value="false" type="STRING" enable="1" />
|
| 341 |
|
|
// Retrieval info: <PRIVATE name = "clk_source_sharing_en" value="false" type="STRING" enable="1" />
|
| 342 |
|
|
// Retrieval info: <PRIVATE name = "phy_if_type_afi" value="true" type="STRING" enable="1" />
|
| 343 |
|
|
// Retrieval info: <PRIVATE name = "ctl_autopch_en" value="false" type="STRING" enable="1" />
|
| 344 |
|
|
// Retrieval info: <PRIVATE name = "shared_sys_clk_source" value="XX" type="STRING" enable="1" />
|
| 345 |
|
|
// Retrieval info: <PRIVATE name = "ref_clk_source" value="XX" type="STRING" enable="1" />
|
| 346 |
|
|
// Retrieval info: <PRIVATE name = "ctl_powerdn_en" value="false" type="STRING" enable="1" />
|
| 347 |
|
|
// Retrieval info: <PRIVATE name = "tool_context" value="STANDALONE" type="STRING" enable="1" />
|
| 348 |
|
|
// Retrieval info: <PRIVATE name = "mem_srtr" value="Normal" type="STRING" enable="1" />
|
| 349 |
|
|
// Retrieval info: <PRIVATE name = "mem_mpr_loc" value="Predefined Pattern" type="STRING" enable="1" />
|
| 350 |
|
|
// Retrieval info: <PRIVATE name = "dss_tinit_rst_us" value="200.0" type="STRING" enable="1" />
|
| 351 |
|
|
// Retrieval info: <PRIVATE name = "mem_tcl_90_fmax" value="400.0" type="STRING" enable="1" />
|
| 352 |
|
|
// Retrieval info: <PRIVATE name = "mem_rtt_wr" value="Dynamic ODT off" type="STRING" enable="1" />
|
| 353 |
|
|
// Retrieval info: <PRIVATE name = "mem_tcl_100_fmax" value="400.0" type="STRING" enable="1" />
|
| 354 |
|
|
// Retrieval info: <PRIVATE name = "mem_pasr" value="Full Array" type="STRING" enable="1" />
|
| 355 |
|
|
// Retrieval info: <PRIVATE name = "mem_asrm" value="Manual SR Reference (SRT)" type="STRING" enable="1" />
|
| 356 |
|
|
// Retrieval info: <PRIVATE name = "mem_mpr_oper" value="Predefined Pattern" type="STRING" enable="1" />
|
| 357 |
|
|
// Retrieval info: <PRIVATE name = "mem_tcl_80_fmax" value="400.0" type="STRING" enable="1" />
|
| 358 |
|
|
// Retrieval info: <PRIVATE name = "mem_drv_impedance" value="RZQ/7" type="STRING" enable="1" />
|
| 359 |
|
|
// Retrieval info: <PRIVATE name = "mem_rtt_nom" value="ODT Disabled" type="STRING" enable="1" />
|
| 360 |
|
|
// Retrieval info: <PRIVATE name = "mem_tcl_70_fmax" value="400.0" type="STRING" enable="1" />
|
| 361 |
|
|
// Retrieval info: <PRIVATE name = "mem_wtcl" value="5.0" type="STRING" enable="1" />
|
| 362 |
|
|
// Retrieval info: <PRIVATE name = "mem_dll_pch" value="Fast Exit" type="STRING" enable="1" />
|
| 363 |
|
|
// Retrieval info: <PRIVATE name = "mem_atcl" value="Disabled" type="STRING" enable="1" />
|
| 364 |
|
|
// Retrieval info: </NAMESPACE>
|
| 365 |
|
|
// Retrieval info: <NAMESPACE name = "simgen">
|
| 366 |
|
|
// Retrieval info: <PRIVATE name = "use_alt_top" value="1" type="STRING" enable="1" />
|
| 367 |
|
|
// Retrieval info: <PRIVATE name = "alt_top" value="altera_ddr_phy_alt_mem_phy_seq_wrapper" type="STRING" enable="1" />
|
| 368 |
|
|
// Retrieval info: <PRIVATE name = "family" value="Cyclone III" type="STRING" enable="1" />
|
| 369 |
|
|
// Retrieval info: <PRIVATE name = "filename" value="altera_ddr_phy_alt_mem_phy_seq_wrapper.vo" type="STRING" enable="1" />
|
| 370 |
|
|
// Retrieval info: </NAMESPACE>
|
| 371 |
|
|
// Retrieval info: <NAMESPACE name = "simgen2">
|
| 372 |
|
|
// Retrieval info: <PRIVATE name = "family" value="Cyclone III" type="STRING" enable="1" />
|
| 373 |
|
|
// Retrieval info: <PRIVATE name = "command" value="--simgen_arbitrary_blackbox=+altera_ddr_phy_alt_mem_phy_seq_wrapper;+altera_ddr_phy_alt_mem_phy_reconfig;+altera_ddr_phy_alt_mem_phy_pll;+altera_ddr_phy_alt_mem_phy_delay --ini=simgen_tri_bus_opt=on" type="STRING" enable="1" />
|
| 374 |
|
|
// Retrieval info: <PRIVATE name = "parameter" value="SIMGEN_INITIALIZATION_FILE=/opt/workspace/xzeng/esig/trunk/or1k_soc/rtl/altera_ddr_ctrl/altera_ddr_phy_simgen_init.txt" type="STRING" enable="1" />
|
| 375 |
|
|
// Retrieval info: </NAMESPACE>
|
| 376 |
|
|
// Retrieval info: <NAMESPACE name = "simgen_enable">
|
| 377 |
|
|
// Retrieval info: <PRIVATE name = "language" value="Verilog HDL" type="STRING" enable="1" />
|
| 378 |
|
|
// Retrieval info: <PRIVATE name = "enabled" value="1" type="STRING" enable="1" />
|
| 379 |
|
|
// Retrieval info: </NAMESPACE>
|
| 380 |
|
|
// Retrieval info: <NAMESPACE name = "greybox">
|
| 381 |
|
|
// Retrieval info: <PRIVATE name = "gb_enabled" value="1" type="STRING" enable="1" />
|
| 382 |
|
|
// Retrieval info: <PRIVATE name = "use_alt_top" value="true" type="STRING" enable="1" />
|
| 383 |
|
|
// Retrieval info: <PRIVATE name = "alt_top" value="altera_ddr" type="STRING" enable="1" />
|
| 384 |
|
|
// Retrieval info: <PRIVATE name = "gb_extra_libdirs" value="/opt/workspace/xzeng/esig/trunk/or1k_soc/rtl/altera_ddr_ctrl/" type="STRING" enable="1" />
|
| 385 |
|
|
// Retrieval info: <PRIVATE name = "filename" value="altera_ddr_syn.v" type="STRING" enable="1" />
|
| 386 |
|
|
// Retrieval info: </NAMESPACE>
|
| 387 |
|
|
// Retrieval info: <NAMESPACE name = "qip">
|
| 388 |
|
|
// Retrieval info: <PRIVATE name = "gx_libs" value="1" type="STRING" enable="1" />
|
| 389 |
|
|
// Retrieval info: </NAMESPACE>
|
| 390 |
|
|
// Retrieval info: <NAMESPACE name = "serializer"/>
|
| 391 |
|
|
// Retrieval info: <NAMESPACE name = "quartus_settings">
|
| 392 |
|
|
// Retrieval info: <PRIVATE name = "DEVICE" value="EP3C25F324C6" type="STRING" enable="1" />
|
| 393 |
|
|
// Retrieval info: <PRIVATE name = "FAMILY" value="Cyclone III" type="STRING" enable="1" />
|
| 394 |
|
|
// Retrieval info: <PRIVATE name = "WEB_BROWSER" value="/usr/bin/firefox" type="STRING" enable="1" />
|
| 395 |
|
|
// Retrieval info: <PRIVATE name = "LICENSE_FILE" value="/opt/altera9.0/license.dat" type="STRING" enable="1" />
|
| 396 |
|
|
// Retrieval info: </NAMESPACE>
|
| 397 |
|
|
// Retrieval info: </PRIVATES>
|
| 398 |
|
|
// Retrieval info: <FILES/>
|
| 399 |
|
|
// Retrieval info: <PORTS/>
|
| 400 |
|
|
// Retrieval info: <LIBRARIES/>
|
| 401 |
|
|
// Retrieval info: </STATIC_SECTION>
|
| 402 |
|
|
// Retrieval info: </NETLIST_SECTION>
|
| 403 |
|
|
// Retrieval info: </MEGACORE>
|
| 404 |
|
|
// =========================================================
|
| 405 |
|
|
// IPFS_FILES: altera_ddr_phy_alt_mem_phy_seq_wrapper.vo;
|
| 406 |
|
|
// =========================================================
|
