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xianfeng |
// megafunction wizard: %ALTPLL%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altpll
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// ============================================================
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// File Name: altera_ddr_phy_alt_mem_phy_pll.v
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// Megafunction Name(s):
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// altpll
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 9.0 Build 235 06/17/2009 SP 2 SJ Full Version
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// ************************************************************
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//Copyright (C) 1991-2009 Altera Corporation
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
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//Subscription Agreement, Altera MegaCore Function License
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//Agreement, or other applicable license agreement, including,
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//without limitation, that your use is for the sole purpose of
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//programming logic devices manufactured by Altera and sold by
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//Altera or its authorized distributors. Please refer to the
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//applicable agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module altera_ddr_phy_alt_mem_phy_pll (
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areset,
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inclk0,
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phasecounterselect,
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phasestep,
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phaseupdown,
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scanclk,
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c0,
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c1,
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c2,
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c3,
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c4,
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locked,
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phasedone);
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input areset;
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input inclk0;
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input [2:0] phasecounterselect;
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input phasestep;
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input phaseupdown;
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input scanclk;
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output c0;
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output c1;
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output c2;
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output c3;
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output c4;
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output locked;
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output phasedone;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri0 areset;
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tri0 [2:0] phasecounterselect;
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tri0 phasestep;
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tri0 phaseupdown;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [4:0] sub_wire0;
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wire sub_wire6;
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wire sub_wire7;
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wire [0:0] sub_wire10 = 1'h0;
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wire [4:4] sub_wire5 = sub_wire0[4:4];
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wire [3:3] sub_wire4 = sub_wire0[3:3];
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wire [2:2] sub_wire3 = sub_wire0[2:2];
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wire [1:1] sub_wire2 = sub_wire0[1:1];
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wire [0:0] sub_wire1 = sub_wire0[0:0];
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wire c0 = sub_wire1;
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wire c1 = sub_wire2;
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wire c2 = sub_wire3;
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wire c3 = sub_wire4;
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wire c4 = sub_wire5;
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wire locked = sub_wire6;
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wire phasedone = sub_wire7;
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wire sub_wire8 = inclk0;
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wire [1:0] sub_wire9 = {sub_wire10, sub_wire8};
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altpll altpll_component (
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.phasestep (phasestep),
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.phaseupdown (phaseupdown),
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.inclk (sub_wire9),
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.phasecounterselect (phasecounterselect),
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.areset (areset),
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.scanclk (scanclk),
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.clk (sub_wire0),
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.locked (sub_wire6),
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.phasedone (sub_wire7),
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.activeclock (),
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.clkbad (),
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.clkena ({6{1'b1}}),
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.clkloss (),
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.clkswitch (1'b0),
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.configupdate (1'b0),
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.enable0 (),
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.enable1 (),
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.extclk (),
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.extclkena ({4{1'b1}}),
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.fbin (1'b1),
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.fbmimicbidir (),
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.fbout (),
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.pfdena (1'b1),
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.pllena (1'b1),
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.scanaclr (1'b0),
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.scanclkena (1'b1),
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.scandata (1'b0),
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.scandataout (),
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.scandone (),
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.scanread (1'b0),
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.scanwrite (1'b0),
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.sclkout0 (),
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.sclkout1 (),
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.vcooverrange (),
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.vcounderrange ());
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defparam
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altpll_component.bandwidth_type = "AUTO",
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altpll_component.clk0_divide_by = 2,
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altpll_component.clk0_duty_cycle = 50,
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altpll_component.clk0_multiply_by = 3,
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altpll_component.clk0_phase_shift = "0",
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altpll_component.clk1_divide_by = 1,
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altpll_component.clk1_duty_cycle = 50,
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altpll_component.clk1_multiply_by = 3,
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altpll_component.clk1_phase_shift = "0",
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altpll_component.clk2_divide_by = 1,
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altpll_component.clk2_duty_cycle = 50,
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altpll_component.clk2_multiply_by = 3,
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altpll_component.clk2_phase_shift = "-1667",
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altpll_component.clk3_divide_by = 1,
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altpll_component.clk3_duty_cycle = 50,
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altpll_component.clk3_multiply_by = 3,
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altpll_component.clk3_phase_shift = "0",
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altpll_component.clk4_divide_by = 1,
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altpll_component.clk4_duty_cycle = 50,
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altpll_component.clk4_multiply_by = 3,
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altpll_component.clk4_phase_shift = "0",
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altpll_component.compensate_clock = "CLK1",
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altpll_component.inclk0_input_frequency = 20000,
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altpll_component.intended_device_family = "Cyclone III",
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altpll_component.lpm_type = "altpll",
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altpll_component.operation_mode = "NORMAL",
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altpll_component.pll_type = "AUTO",
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altpll_component.port_activeclock = "PORT_UNUSED",
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altpll_component.port_areset = "PORT_USED",
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altpll_component.port_clkbad0 = "PORT_UNUSED",
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altpll_component.port_clkbad1 = "PORT_UNUSED",
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altpll_component.port_clkloss = "PORT_UNUSED",
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altpll_component.port_clkswitch = "PORT_UNUSED",
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altpll_component.port_configupdate = "PORT_UNUSED",
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altpll_component.port_fbin = "PORT_UNUSED",
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altpll_component.port_inclk0 = "PORT_USED",
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altpll_component.port_inclk1 = "PORT_UNUSED",
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altpll_component.port_locked = "PORT_USED",
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altpll_component.port_pfdena = "PORT_UNUSED",
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altpll_component.port_phasecounterselect = "PORT_USED",
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altpll_component.port_phasedone = "PORT_USED",
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altpll_component.port_phasestep = "PORT_USED",
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altpll_component.port_phaseupdown = "PORT_USED",
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altpll_component.port_pllena = "PORT_UNUSED",
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altpll_component.port_scanaclr = "PORT_UNUSED",
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altpll_component.port_scanclk = "PORT_USED",
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altpll_component.port_scanclkena = "PORT_UNUSED",
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altpll_component.port_scandata = "PORT_UNUSED",
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altpll_component.port_scandataout = "PORT_UNUSED",
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altpll_component.port_scandone = "PORT_UNUSED",
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altpll_component.port_scanread = "PORT_UNUSED",
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altpll_component.port_scanwrite = "PORT_UNUSED",
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altpll_component.port_clk0 = "PORT_USED",
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altpll_component.port_clk1 = "PORT_USED",
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altpll_component.port_clk2 = "PORT_USED",
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altpll_component.port_clk3 = "PORT_USED",
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altpll_component.port_clk4 = "PORT_USED",
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altpll_component.port_clk5 = "PORT_UNUSED",
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altpll_component.port_clkena0 = "PORT_UNUSED",
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altpll_component.port_clkena1 = "PORT_UNUSED",
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altpll_component.port_clkena2 = "PORT_UNUSED",
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altpll_component.port_clkena3 = "PORT_UNUSED",
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altpll_component.port_clkena4 = "PORT_UNUSED",
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altpll_component.port_clkena5 = "PORT_UNUSED",
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altpll_component.port_extclk0 = "PORT_UNUSED",
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altpll_component.port_extclk1 = "PORT_UNUSED",
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altpll_component.port_extclk2 = "PORT_UNUSED",
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altpll_component.port_extclk3 = "PORT_UNUSED",
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altpll_component.self_reset_on_loss_lock = "OFF",
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altpll_component.vco_frequency_control = "MANUAL_PHASE",
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altpll_component.vco_phase_shift_step = 104,
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altpll_component.width_clock = 5,
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altpll_component.width_phasecounterselect = 3;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
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// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
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// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
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// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
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// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
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// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
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// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
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// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
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// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
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// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
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// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
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// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
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// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
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// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1"
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// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
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// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
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// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
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// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
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// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
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// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
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// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
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// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
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// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
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// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
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// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
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// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
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// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "75.000000"
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// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "150.000000"
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// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "150.000000"
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// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "150.000000"
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// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "150.000000"
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// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
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// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
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// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
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// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
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// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
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// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
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// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
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// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
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// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
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// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
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// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
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// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
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// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
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// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
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// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
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// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "300.000"
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// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
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// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
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// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
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// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
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// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
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// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "deg"
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// Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_EDIT STRING "104.00000000"
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// Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_UNIT STRING "ps"
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// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
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// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
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// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
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// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
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// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
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// Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
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// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
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// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
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// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
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// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
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// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "2"
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// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
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// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "75.00000000"
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// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "150.00000000"
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// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "150.00000000"
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// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "150.00000000"
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// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "150.00000000"
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// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
|
289 |
|
|
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
|
290 |
|
|
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
|
291 |
|
|
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
|
292 |
|
|
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1"
|
293 |
|
|
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
294 |
|
|
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
295 |
|
|
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
296 |
|
|
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
|
297 |
|
|
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
|
298 |
|
|
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
299 |
|
|
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "1"
|
300 |
|
|
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
301 |
|
|
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
302 |
|
|
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-90.00000000"
|
303 |
|
|
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
|
304 |
|
|
// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
|
305 |
|
|
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "1"
|
306 |
|
|
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
307 |
|
|
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
308 |
|
|
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
|
309 |
|
|
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
|
310 |
|
|
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg"
|
311 |
|
|
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
312 |
|
|
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
|
313 |
|
|
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
314 |
|
|
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
315 |
|
|
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
316 |
|
|
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
317 |
|
|
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
318 |
|
|
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
319 |
|
|
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
320 |
|
|
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
321 |
|
|
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "alt_mem_phy_pll.mif"
|
322 |
|
|
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
323 |
|
|
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
324 |
|
|
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
325 |
|
|
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
326 |
|
|
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
327 |
|
|
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
328 |
|
|
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
329 |
|
|
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
330 |
|
|
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
331 |
|
|
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
332 |
|
|
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
333 |
|
|
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
334 |
|
|
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
335 |
|
|
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
|
336 |
|
|
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
|
337 |
|
|
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
338 |
|
|
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
339 |
|
|
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
340 |
|
|
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
341 |
|
|
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
342 |
|
|
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
343 |
|
|
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
|
344 |
|
|
// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
|
345 |
|
|
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
346 |
|
|
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
347 |
|
|
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
348 |
|
|
// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
|
349 |
|
|
// Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
|
350 |
|
|
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
351 |
|
|
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
352 |
|
|
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
353 |
|
|
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
354 |
|
|
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
|
355 |
|
|
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
356 |
|
|
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"
|
357 |
|
|
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
358 |
|
|
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
|
359 |
|
|
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
360 |
|
|
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "3"
|
361 |
|
|
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
362 |
|
|
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
|
363 |
|
|
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
364 |
|
|
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "3"
|
365 |
|
|
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-1667"
|
366 |
|
|
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
|
367 |
|
|
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
|
368 |
|
|
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "3"
|
369 |
|
|
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
|
370 |
|
|
// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1"
|
371 |
|
|
// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
|
372 |
|
|
// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "3"
|
373 |
|
|
// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
|
374 |
|
|
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1"
|
375 |
|
|
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
|
376 |
|
|
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
377 |
|
|
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
378 |
|
|
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
379 |
|
|
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
380 |
|
|
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
381 |
|
|
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
|
382 |
|
|
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
383 |
|
|
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
384 |
|
|
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
385 |
|
|
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
386 |
|
|
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
387 |
|
|
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
388 |
|
|
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
389 |
|
|
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
390 |
|
|
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
391 |
|
|
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
392 |
|
|
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_USED"
|
393 |
|
|
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_USED"
|
394 |
|
|
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_USED"
|
395 |
|
|
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_USED"
|
396 |
|
|
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
397 |
|
|
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
398 |
|
|
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
|
399 |
|
|
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
400 |
|
|
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
401 |
|
|
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
402 |
|
|
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
403 |
|
|
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
404 |
|
|
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
405 |
|
|
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
406 |
|
|
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
407 |
|
|
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
408 |
|
|
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
|
409 |
|
|
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
|
410 |
|
|
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
411 |
|
|
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
412 |
|
|
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
413 |
|
|
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
414 |
|
|
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
415 |
|
|
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
416 |
|
|
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
417 |
|
|
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
418 |
|
|
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
419 |
|
|
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
420 |
|
|
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
421 |
|
|
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
|
422 |
|
|
// Retrieval info: CONSTANT: VCO_FREQUENCY_CONTROL STRING "MANUAL_PHASE"
|
423 |
|
|
// Retrieval info: CONSTANT: VCO_PHASE_SHIFT_STEP NUMERIC "104"
|
424 |
|
|
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
425 |
|
|
// Retrieval info: CONSTANT: WIDTH_PHASECOUNTERSELECT NUMERIC "3"
|
426 |
|
|
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
427 |
|
|
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
|
428 |
|
|
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
429 |
|
|
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
430 |
|
|
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
431 |
|
|
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
|
432 |
|
|
// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
|
433 |
|
|
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
434 |
|
|
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
435 |
|
|
// Retrieval info: USED_PORT: phasecounterselect 0 0 3 0 INPUT GND "phasecounterselect[2..0]"
|
436 |
|
|
// Retrieval info: USED_PORT: phasedone 0 0 0 0 OUTPUT GND "phasedone"
|
437 |
|
|
// Retrieval info: USED_PORT: phasestep 0 0 0 0 INPUT GND "phasestep"
|
438 |
|
|
// Retrieval info: USED_PORT: phaseupdown 0 0 0 0 INPUT GND "phaseupdown"
|
439 |
|
|
// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
|
440 |
|
|
// Retrieval info: CONNECT: phasedone 0 0 0 0 @phasedone 0 0 0 0
|
441 |
|
|
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
442 |
|
|
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
443 |
|
|
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
444 |
|
|
// Retrieval info: CONNECT: @phaseupdown 0 0 0 0 phaseupdown 0 0 0 0
|
445 |
|
|
// Retrieval info: CONNECT: @phasecounterselect 0 0 3 0 phasecounterselect 0 0 3 0
|
446 |
|
|
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
447 |
|
|
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
|
448 |
|
|
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
449 |
|
|
// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
|
450 |
|
|
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
451 |
|
|
// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
|
452 |
|
|
// Retrieval info: CONNECT: @phasestep 0 0 0 0 phasestep 0 0 0 0
|
453 |
|
|
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
|
454 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_ddr_phy_alt_mem_phy_pll.v TRUE
|
455 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_ddr_phy_alt_mem_phy_pll.inc FALSE
|
456 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_ddr_phy_alt_mem_phy_pll.cmp FALSE
|
457 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_ddr_phy_alt_mem_phy_pll.bsf FALSE
|
458 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_ddr_phy_alt_mem_phy_pll_inst.v TRUE
|
459 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_ddr_phy_alt_mem_phy_pll_bb.v TRUE
|
460 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_ddr_phy_alt_mem_phy_pll_waveforms.html TRUE
|
461 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_ddr_phy_alt_mem_phy_pll_wave*.jpg FALSE
|
462 |
|
|
// Retrieval info: LIB_FILE: altera_mf
|