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URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [altera_ddr_ctrl/] [altera_ddr_phy_alt_mem_phy_pll_inst.v] - Blame information for rev 12

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Line No. Rev Author Line
1 12 xianfeng
altera_ddr_phy_alt_mem_phy_pll  altera_ddr_phy_alt_mem_phy_pll_inst (
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        .areset ( areset_sig ),
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        .inclk0 ( inclk0_sig ),
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        .phasecounterselect ( phasecounterselect_sig ),
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        .phasestep ( phasestep_sig ),
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        .phaseupdown ( phaseupdown_sig ),
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        .scanclk ( scanclk_sig ),
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        .c0 ( c0_sig ),
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        .c1 ( c1_sig ),
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        .c2 ( c2_sig ),
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        .c3 ( c3_sig ),
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        .c4 ( c4_sig ),
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        .locked ( locked_sig ),
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        .phasedone ( phasedone_sig )
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        );

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