Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

--

-- -----------------------------------------------------------------------------

--  Abstract        : constants package for the non-levelling AFI PHY sequencer

--                    The constant package (alt_mem_phy_constants_pkg) contains global

--                    'constants' which are fixed thoughout the sequencer and will not

--                    change (for constants which may change between sequencer

--                    instances generics are used)

-- -----------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

--

package altera_ddr_phy_alt_mem_phy_constants_pkg is

    -- -------------------------------

    -- Register number definitions

    -- -------------------------------

    constant c_max_mode_reg_index          : natural := 13;   -- number of MR bits..

    -- Top bit of vector (i.e. width -1) used for address decoding :

    constant c_debug_reg_addr_top          : natural := 3;

    constant c_mmi_access_codeword         : std_logic_vector(31 downto 0) := X"00D0_0DEB";  -- to check for legal Avalon interface accesses

    -- Register addresses.

    constant c_regofst_cal_status          : natural := 0;

    constant c_regofst_debug_access        : natural := 1;

    constant c_regofst_hl_css              : natural := 2;

    constant c_regofst_mr_register_a       : natural := 5;

    constant c_regofst_mr_register_b       : natural := 6;

    constant c_regofst_codvw_status        : natural := 12;

    constant c_regofst_if_param            : natural := 13;

    constant c_regofst_if_test             : natural := 14;   -- pll_phs_shft, ac_1t, extra stuff

    constant c_regofst_test_status         : natural := 15;

    constant c_hl_css_reg_cal_dis_bit                    : natural := 0;

    constant c_hl_css_reg_phy_initialise_dis_bit         : natural := 1;

    constant c_hl_css_reg_init_dram_dis_bit              : natural := 2;

    constant c_hl_css_reg_write_ihi_dis_bit              : natural := 3;

    constant c_hl_css_reg_write_btp_dis_bit              : natural := 4;

    constant c_hl_css_reg_write_mtp_dis_bit              : natural := 5;

    constant c_hl_css_reg_read_mtp_dis_bit               : natural := 6;

    constant c_hl_css_reg_rrp_reset_dis_bit              : natural := 7;

    constant c_hl_css_reg_rrp_sweep_dis_bit              : natural := 8;

    constant c_hl_css_reg_rrp_seek_dis_bit               : natural := 9;

    constant c_hl_css_reg_rdv_dis_bit                    : natural := 10;

    constant c_hl_css_reg_poa_dis_bit                    : natural := 11;

    constant c_hl_css_reg_was_dis_bit                    : natural := 12;

    constant c_hl_css_reg_adv_rd_lat_dis_bit             : natural := 13;

    constant c_hl_css_reg_adv_wr_lat_dis_bit             : natural := 14;

    constant c_hl_css_reg_prep_customer_mr_setup_dis_bit : natural := 15;

    constant c_hl_css_reg_tracking_dis_bit               : natural := 16;

    constant c_hl_ccs_num_stages                         : natural := 17;

    -- -----------------------------------------------------

    -- Constants for DRAM addresses used during calibration:

    -- -----------------------------------------------------

    -- the mtp training pattern is x30F5

    -- 1. write 0011 0000 and 1100 0000 such that one location will contains 0011 0000

    -- 2. write in 1111 0101

    -- also require locations containing all ones and all zeros

    -- default choice of calibration burst length (overriden to 8 for reads for DDR3 devices)

    constant c_cal_burst_len        : natural := 4;

    constant c_cal_ofs_step_size    : natural := 8;

    constant c_cal_ofs_zeros        : natural := 0 * c_cal_ofs_step_size;

    constant c_cal_ofs_ones         : natural := 1 * c_cal_ofs_step_size;

    constant c_cal_ofs_x30_almt_0   : natural := 2 * c_cal_ofs_step_size;

    constant c_cal_ofs_x30_almt_1   : natural := 3 * c_cal_ofs_step_size;

    constant c_cal_ofs_xF5          : natural := 5 * c_cal_ofs_step_size;

    constant c_cal_ofs_wd_lat       : natural := 6 * c_cal_ofs_step_size;

    constant c_cal_data_len         : natural := c_cal_ofs_wd_lat + c_cal_ofs_step_size;

    constant c_cal_ofs_mtp              : natural := 6*c_cal_ofs_step_size;

    constant c_cal_ofs_mtp_len      : natural := 4*4;

    constant c_cal_ofs_01_pairs     : natural := 2 * c_cal_burst_len;

    constant c_cal_ofs_10_pairs     : natural := 3 * c_cal_burst_len;

    constant c_cal_ofs_1100_step    : natural := 4 * c_cal_burst_len;

    constant c_cal_ofs_0011_step    : natural := 5 * c_cal_burst_len;

    -- -----------------------------------------------------

    -- Reset values. - These are chosen as default values for one PHY variation

    --                 with DDR2 memory and CAS latency 6, however in each calibration

    --                 mode these values will be set for a given PHY configuration.

    -- -----------------------------------------------------

    constant c_default_rd_lat : natural := 20;

    constant c_default_wr_lat : natural := 5;

    -- -----------------------------------------------------

    -- Errorcodes

    -- -----------------------------------------------------

    -- implemented

    constant C_SUCCESS                             : natural := 0;

    constant C_ERR_RESYNC_NO_VALID_PHASES          : natural := 5;  -- No valid data-valid windows found

    constant C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS   : natural := 6;  -- Multiple equally-sized data valid windows

    constant C_ERR_RESYNC_NO_INVALID_PHASES        : natural := 7;  -- No invalid data-valid windows found.  Training patterns are designed so that there should always be at least one invalid phase.

    constant C_ERR_CRITICAL                        : natural := 15; -- A condition that can't happen just happened.

    constant C_ERR_READ_MTP_NO_VALID_ALMT          : natural := 23;

    constant C_ERR_READ_MTP_BOTH_ALMT_PASS         : natural := 24;

        constant C_ERR_WD_LAT_DISAGREEMENT                         : natural := 22; -- MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS copies of write-latency are written to memory.  If all of these are not the same this error is generated.

    constant C_ERR_MAX_RD_LAT_EXCEEDED             : natural := 25;

    constant C_ERR_MAX_TRK_SHFT_EXCEEDED           : natural := 26;

    -- not implemented yet

    constant c_err_ac_lat_some_beats_are_different : natural := 1;    -- implies DQ_1T setup failure or earlier.

    constant c_err_could_not_find_read_lat         : natural := 2;    -- dodgy RDP setup

    constant c_err_could_not_find_write_lat        : natural := 3;    -- dodgy WDP setup

    constant c_err_clock_cycle_iteration_timeout   : natural :=  8;    -- depends on srate calling error  -- GENERIC

    constant c_err_clock_cycle_it_timeout_rdp      : natural :=  9;

    constant c_err_clock_cycle_it_timeout_rdv      : natural := 10;

    constant c_err_clock_cycle_it_timeout_poa      : natural := 11;

    constant c_err_pll_ack_timeout                 : natural := 13;

    constant c_err_WindowProc_multiple_rsc_windows : natural := 16;

    constant c_err_WindowProc_window_det_no_ones   : natural := 17;

    constant c_err_WindowProc_window_det_no_zeros  : natural := 18;

    constant c_err_WindowProc_undefined            : natural := 19;   -- catch all

    constant c_err_tracked_mmc_offset_overflow     : natural := 20;

    constant c_err_no_mimic_feedback               : natural := 21;

    constant c_err_ctrl_ack_timeout                : natural := 32;

    constant c_err_ctrl_done_timeout               : natural := 33;

    -- -----------------------------------------------------

    -- PLL phase locations per device family

    -- (unused but a limited set is maintained here for reference)

    -- -----------------------------------------------------

    constant c_pll_resync_phs_select_ciii : natural := 5;

    constant c_pll_mimic_phs_select_ciii  : natural := 4;

    constant c_pll_resync_phs_select_siii : natural := 5;

    constant c_pll_mimic_phs_select_siii  : natural := 7;

    -- -----------------------------------------------------

    -- Maximum sizing constraints

    -- -----------------------------------------------------

    constant C_MAX_NUM_PLL_RSC_PHASES : natural := 32;

    -- -----------------------------------------------------

    -- IO control Params

    -- -----------------------------------------------------

    constant c_set_oct_to_rs : std_logic := '0';

    constant c_set_oct_to_rt : std_logic := '1';

    constant c_set_odt_rt    : std_logic := '1';

    constant c_set_odt_off   : std_logic := '0';

--

end altera_ddr_phy_alt_mem_phy_constants_pkg;

--

-- -----------------------------------------------------------------------------

--  Abstract        : record package for the non-levelling AFI sequencer

--                    The record package (alt_mem_phy_record_pkg) is used to combine

--                    command and status signals (into records) to be passed between

--                    sequencer blocks. It also contains type and record definitions

--                    for the stages of DRAM memory calibration.

-- -----------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

--

package altera_ddr_phy_alt_mem_phy_record_pkg is

    -- set some maximum constraints to bound natural numbers below

    constant c_max_num_dqs_groups : natural := 24;

    constant c_max_num_pins       : natural := 8;

    constant c_max_ranks          : natural := 16;

    type t_family is (

        cyclone3,

        stratix2,

        stratix3

    );

-- -----------------------------------------------------------------------

--  the following are required for the non-levelling AFI PHY sequencer block interfaces

-- -----------------------------------------------------------------------

    -- admin mode register settings (from mmi block)

    type t_admin_ctrl is record

        mr0 : std_logic_vector(12 downto 0);

        mr1 : std_logic_vector(12 downto 0);

        mr2 : std_logic_vector(12 downto 0);

        mr3 : std_logic_vector(12 downto 0);

    end record;

    function defaults return t_admin_ctrl;

    -- current admin status

    type t_admin_stat is record

        mr0       : std_logic_vector(12 downto 0);

        mr1       : std_logic_vector(12 downto 0);

        mr2       : std_logic_vector(12 downto 0);

        mr3       : std_logic_vector(12 downto 0);

        init_done : std_logic;

    end record;

    function defaults return t_admin_stat;

    -- mmi to iram ctrl signals

    type t_iram_ctrl is record

        addr    : natural range 0 to 1023;

        wdata   : std_logic_vector(31 downto 0);

        write   : std_logic;

        read    : std_logic;

    end record;

    function defaults return t_iram_ctrl;

   -- broadcast iram status to mmi and dgrb

    type t_iram_stat is record

        rdata            : std_logic_vector(31 downto 0);

        done             : std_logic;

        err              : std_logic;

        err_code         : std_logic_vector(3 downto 0);

        init_done        : std_logic;

        out_of_mem       : std_logic;

        contested_access : std_logic;

    end record;

    function defaults return t_iram_stat;

    -- codvw status signals from dgrb to mmi block

    type t_dgrb_mmi is record

        cal_codvw_phase   : std_logic_vector(7 downto 0);

        cal_codvw_size    : std_logic_vector(7 downto 0);

        codvw_trk_shift   : std_logic_vector(11 downto 0);

        codvw_grt_one_dvw : std_logic;

    end record;

    function defaults return t_dgrb_mmi;

    -- signal to id which block is active

    type t_ctrl_active_block is (

                                    idle,

                                    admin,

                                    dgwb,

                                    dgrb,

                                    proc,  -- unused in non-levelling AFI sequencer

                                    setup, -- unused in non-levelling AFI sequencer

                                    iram

                              );

    function ret_proc return t_ctrl_active_block;

    function ret_dgrb return t_ctrl_active_block;

    -- control record for dgwb, dgrb, iram and admin blocks:

    -- the possible commands

    type t_ctrl_cmd_id is (

                            cmd_idle,

                            -- initialisation stages

                            cmd_phy_initialise,

                            cmd_init_dram,

                            cmd_write_ihi,

                            -- calibration stages

                            cmd_write_btp,

                            cmd_write_mtp,

                            cmd_read_mtp,

                            cmd_rrp_reset,

                            cmd_rrp_sweep,

                            cmd_rrp_seek,

                            cmd_rdv,

                            cmd_poa,

                            cmd_was,

                            -- advertise controller settings and re-configure for customer operation mode.

                            cmd_prep_adv_rd_lat,

                            cmd_prep_adv_wr_lat,

                            cmd_prep_customer_mr_setup,

                            cmd_tr_due

                          );

    -- which block should execute each command

    function curr_active_block (

        ctrl_cmd_id : t_ctrl_cmd_id

       ) return  t_ctrl_active_block;

    -- specify command operands as a record

    type t_command_op is record

        current_cs : natural range 0 to c_max_ranks-1; -- which chip select is being calibrated

        single_bit : std_logic;                        -- current operation should be single bit

        mtp_almt   : natural range 0 to 1;             -- signals mtp alignment to be used for operation

    end record;

    function defaults return t_command_op;

    -- command request record (sent to each block)

    type t_ctrl_command is record

        command       : t_ctrl_cmd_id;

        command_op    : t_command_op;

        command_req   : std_logic;

    end record;

    function defaults return t_ctrl_command;

    -- a generic status record for each block

    type t_ctrl_stat is record

        command_ack    : std_logic;

        command_done   : std_logic;

        command_result : std_logic_vector(7 downto 0 );

        command_err    : std_logic;

    end record;

    function defaults return t_ctrl_stat;

    -- push interface for dgwb / dgrb blocks (only the dgrb uses this interface at present)

    type t_iram_push is record

        iram_done     : std_logic;

        iram_write    : std_logic;

        iram_wordnum  : natural range 0 to 255;        -- acts as an offset to current location

        iram_bitnum   : natural range 0 to 31;         -- for bitwise packing modes

        iram_pushdata : std_logic_vector(31 downto 0); -- only bit zero used for bitwise packing_mode

    end record;

    function defaults return t_iram_push;

    -- control block "master" state machine

    type t_master_sm_state is

    (

        s_reset,

        s_phy_initialise,         -- wait for dll lock and init done flag from iram

        s_init_dram,              -- dram initialisation (in admin block)

        s_write_ihi,              -- write header information in iRAM

        s_cal,                    -- check if calibration to be executed

        s_write_btp,              -- write burst training pattern

        s_write_mtp,              -- write more training pattern

        s_read_mtp,               -- read training patterns to find correct alignment for 1100 burst

                                  -- (this is a special case of s_rrp_seek with no resych phase setting)

        s_rrp_reset,              -- read resync phase setup - reset initial conditions

        s_rrp_sweep,              -- read resync phase setup - sweep phases per chip select

        s_rrp_seek,               -- read resync phase setup - seek correct phase

        s_rdv,                    -- read data valid setup

        s_was,                    -- write datapath setup (ac to write data timing)

        s_adv_rd_lat,             -- advertise read latency

        s_adv_wr_lat,             -- advertise write latency

        s_poa,                    -- calibrate the postamble (dqs based capture only)

        s_tracking_setup,         -- perform tracking (1st pass to setup mimic window)

        s_prep_customer_mr_setup, -- apply user mode register settings (in admin block)

        s_tracking,               -- perform tracking (subsequent passes in user mode)

        s_operational,            -- calibration successful and in user mode

        s_non_operational         -- calibration unsuccessful and in user mode

    );

    -- record (set in mmi block) to disable calibration states

    type t_hl_css_reg is record

        phy_initialise_dis         : std_logic;

        init_dram_dis              : std_logic;

        write_ihi_dis              : std_logic;

        cal_dis                    : std_logic;

        write_btp_dis              : std_logic;

        write_mtp_dis              : std_logic;

        read_mtp_dis               : std_logic;

        rrp_reset_dis              : std_logic;

        rrp_sweep_dis              : std_logic;

        rrp_seek_dis               : std_logic;

        rdv_dis                    : std_logic;

        poa_dis                    : std_logic;

        was_dis                    : std_logic;

        adv_rd_lat_dis             : std_logic;

        adv_wr_lat_dis             : std_logic;

        prep_customer_mr_setup_dis : std_logic;

        tracking_dis               : std_logic;

    end record;

    function defaults return t_hl_css_reg;

    -- record (set in ctrl block) to identify when a command has been acknowledged

    type t_cal_stage_ack_seen is record

        cal                    : std_logic;

        phy_initialise         : std_logic;

        init_dram              : std_logic;

        write_ihi              : std_logic;

        write_btp              : std_logic;

        write_mtp              : std_logic;

        read_mtp               : std_logic;

        rrp_reset              : std_logic;

        rrp_sweep              : std_logic;

        rrp_seek               : std_logic;

        rdv                    : std_logic;

        poa                    : std_logic;

        was                    : std_logic;

        adv_rd_lat             : std_logic;

        adv_wr_lat             : std_logic;

        prep_customer_mr_setup : std_logic;

        tracking_setup         : std_logic;

    end record;

    function defaults return t_cal_stage_ack_seen;

    -- ctrl to mmi block interface (calibration status)

    type t_ctrl_mmi is record

        master_state_r             : t_master_sm_state;

        ctrl_calibration_success   : std_logic;

        ctrl_calibration_fail      : std_logic;

        ctrl_current_stage_done    : std_logic;

        ctrl_current_stage         : t_ctrl_cmd_id;

        ctrl_current_active_block  : t_ctrl_active_block;

        ctrl_cal_stage_ack_seen    : t_cal_stage_ack_seen;

        ctrl_err_code              : std_logic_vector(7 downto 0);

    end record;

    function defaults return t_ctrl_mmi;

    -- mmi to ctrl block interface (calibration control signals)

    type t_mmi_ctrl is record

        hl_css                   : t_hl_css_reg;

        calibration_start        : std_logic;

        tracking_period_ms       : natural range 0 to 255;

        tracking_orvd_to_10ms    : std_logic;

    end record;

    function defaults return t_mmi_ctrl;

    -- algorithm parameterisation (generated in mmi block)

    type t_algm_paramaterisation is record

         num_phases_per_tck_pll : natural range 1 to 80;

         nominal_dqs_delay      : natural range 0 to 4;

         pll_360_sweeps         : natural range 0 to 15;

         nominal_poa_phase_lead : natural range 0 to 7;

         maximum_poa_delay      : natural range 0 to 15;

         odt_enabled            : boolean;

         extend_octrt_by        : natural range 0 to 15;

         delay_octrt_by         : natural range 0 to 15;

         tracking_period_ms     : natural range 0 to 255;

    end record;

    -- interface between mmi and pll to control phase shifting

    type t_mmi_pll_reconfig is record

        pll_phs_shft_phase_sel : natural range 0 to 15;

        pll_phs_shft_up_wc     : std_logic;

        pll_phs_shft_dn_wc     : std_logic;

    end record;

    type t_pll_mmi is record

        pll_busy : std_logic;

        err      : std_logic_vector(1 downto 0);

    end record;

    -- specify the iram configuration this is default

    -- currently always dq_bitwise packing and a write mode of overwrite_ram

    type t_iram_packing_mode is (

                                    dq_bitwise,

                                    dq_wordwise

                                );

    type t_iram_write_mode is (

                                    overwrite_ram,

                                    or_into_ram,

                                    and_into_ram

                              );

    type t_ctrl_iram is record

        packing_mode : t_iram_packing_mode;

        write_mode   : t_iram_write_mode;

        active_block : t_ctrl_active_block;

    end record;

    function defaults return t_ctrl_iram;

-- -----------------------------------------------------------------------

--  the following are required for compliance to levelling AFI PHY interface but

--  are non-functional for non-levelling AFI PHY sequencer

-- -----------------------------------------------------------------------

    type t_sc_ctrl_if is record

        read             : std_logic;

        write            : std_logic;

        dqs_group_sel    : std_logic_vector( 4 downto 0);

        sc_in_group_sel  : std_logic_vector( 5 downto 0);

        wdata            : std_logic_vector(45 downto 0);

        op_type          : std_logic_vector( 1 downto 0);

    end record;

    function defaults return t_sc_ctrl_if;

    type t_sc_stat is record

        rdata           : std_logic_vector(45 downto 0);

        busy            : std_logic;

        error_det       : std_logic;

        err_code        : std_logic_vector(1 downto 0);

        sc_cap          : std_logic_vector(7 downto 0);

    end record;

    function defaults return t_sc_stat;

    type t_element_to_reconfigure is (

                                       pp_t9,

                                       pp_t10,

                                       pp_t1,

                                       dqslb_rsc_phs,

                                       dqslb_poa_phs_ofst,

                                       dqslb_dqs_phs,

                                       dqslb_dq_phs_ofst,

                                       dqslb_dq_1t,

                                       dqslb_dqs_1t,

                                       dqslb_rsc_1t,

                                       dqslb_div2_phs,

                                       dqslb_oct_t9,

                                       dqslb_oct_t10,

                                       dqslb_poa_t7,

                                       dqslb_poa_t11,

                                       dqslb_dqs_dly,

                                       dqslb_lvlng_byps

                                     );

    type t_sc_type is (

                        DQS_LB,

                        DQS_DQ_DM_PINS,

                        DQ_DM_PINS,

                        dqs_dqsn_pins,

                        dq_pin,

                        dqs_pin,

                        dm_pin,

                        dq_pins

                       );

    type t_sc_int_ctrl is record

        group_num  : natural range 0 to c_max_num_dqs_groups;

        group_type : t_sc_type;

        pin_num    : natural range 0 to c_max_num_pins;

        sc_element : t_element_to_reconfigure;

        prog_val   : std_logic_vector(3 downto 0);

        ram_set    : std_logic;

        sc_update  : std_logic;

    end record;

    function defaults return t_sc_int_ctrl;

--

end altera_ddr_phy_alt_mem_phy_record_pkg;

--

package body altera_ddr_phy_alt_mem_phy_record_pkg IS

-- -----------------------------------------------------------------------

--  function implementations for the above declarations

--  these are mainly default conditions for records

-- -----------------------------------------------------------------------

    function defaults return t_admin_ctrl is

        variable output : t_admin_ctrl;

    begin

        output.mr0 := (others => '0');

        output.mr1 := (others => '0');

        output.mr2 := (others => '0');

        output.mr3 := (others => '0');

        return output;

    end function;

    function defaults return t_admin_stat is

        variable output : t_admin_stat;

    begin

        output.mr0 := (others => '0');

        output.mr1 := (others => '0');

        output.mr2 := (others => '0');

        output.mr3 := (others => '0');

        return output;

    end function;

    function defaults return t_iram_ctrl is

        variable output : t_iram_ctrl;

    begin

        output.addr    := 0;

        output.wdata   := (others => '0');

        output.write   := '0';

        output.read    := '0';

        return output;

    end function;

    function defaults return t_iram_stat is

        variable output : t_iram_stat;

    begin

        output.rdata            := (others => '0');

        output.done             := '0';

        output.err              := '0';

        output.err_code         := (others => '0');

        output.init_done        := '0';

        output.out_of_mem       := '0';

        output.contested_access := '0';

        return output;

    end function;

    function defaults return t_dgrb_mmi is

        variable output : t_dgrb_mmi;

    begin

        output.cal_codvw_phase   := (others => '0');

        output.cal_codvw_size    := (others => '0');

        output.codvw_trk_shift   := (others => '0');

        output.codvw_grt_one_dvw := '0';

        return output;

    end function;

    function ret_proc return t_ctrl_active_block is

        variable output : t_ctrl_active_block;

    begin

        output := proc;

        return output;

    end function;

    function ret_dgrb return t_ctrl_active_block is

        variable output : t_ctrl_active_block;

    begin

        output := dgrb;

        return output;

    end function;

    function defaults return t_ctrl_iram is

        variable output : t_ctrl_iram;

    begin

        output.packing_mode := dq_bitwise;

        output.write_mode   := overwrite_ram;

        output.active_block := idle;

        return output;

    end function;

    function defaults return t_command_op is

        variable output : t_command_op;

    begin

        output.current_cs := 0;

        output.single_bit := '0';

        output.mtp_almt   := 0;

        return output;

    end function;

    function defaults return t_ctrl_command is

        variable output : t_ctrl_command;

    begin

        output.command     := cmd_idle;

        output.command_req := '0';

        output.command_op  := defaults;

        return output;

    end function;

    -- decode which block is associated with which command

    function curr_active_block (

        ctrl_cmd_id : t_ctrl_cmd_id

       ) return  t_ctrl_active_block is

    begin

        case ctrl_cmd_id is

            when cmd_idle                   => return idle;

            when cmd_phy_initialise         => return idle;

            when cmd_init_dram              => return admin;

            when cmd_write_ihi              => return iram;

            when cmd_write_btp              => return dgwb;

            when cmd_write_mtp              => return dgwb;

            when cmd_read_mtp               => return dgrb;

            when cmd_rrp_reset              => return dgrb;

            when cmd_rrp_sweep              => return dgrb;

            when cmd_rrp_seek               => return dgrb;

            when cmd_rdv                    => return dgrb;

            when cmd_poa                    => return dgrb;