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12 |
xianfeng |
--
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-- -----------------------------------------------------------------------------
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-- Abstract : constants package for the non-levelling AFI PHY sequencer
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-- The constant package (alt_mem_phy_constants_pkg) contains global
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-- 'constants' which are fixed thoughout the sequencer and will not
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-- change (for constants which may change between sequencer
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-- instances generics are used)
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-- -----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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--
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package altera_ddr_phy_alt_mem_phy_constants_pkg is
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-- -------------------------------
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-- Register number definitions
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-- -------------------------------
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constant c_max_mode_reg_index : natural := 13; -- number of MR bits..
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-- Top bit of vector (i.e. width -1) used for address decoding :
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constant c_debug_reg_addr_top : natural := 3;
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constant c_mmi_access_codeword : std_logic_vector(31 downto 0) := X"00D0_0DEB"; -- to check for legal Avalon interface accesses
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-- Register addresses.
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constant c_regofst_cal_status : natural := 0;
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constant c_regofst_debug_access : natural := 1;
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constant c_regofst_hl_css : natural := 2;
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constant c_regofst_mr_register_a : natural := 5;
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constant c_regofst_mr_register_b : natural := 6;
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constant c_regofst_codvw_status : natural := 12;
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constant c_regofst_if_param : natural := 13;
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constant c_regofst_if_test : natural := 14; -- pll_phs_shft, ac_1t, extra stuff
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constant c_regofst_test_status : natural := 15;
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constant c_hl_css_reg_cal_dis_bit : natural := 0;
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constant c_hl_css_reg_phy_initialise_dis_bit : natural := 1;
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constant c_hl_css_reg_init_dram_dis_bit : natural := 2;
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constant c_hl_css_reg_write_ihi_dis_bit : natural := 3;
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constant c_hl_css_reg_write_btp_dis_bit : natural := 4;
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constant c_hl_css_reg_write_mtp_dis_bit : natural := 5;
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constant c_hl_css_reg_read_mtp_dis_bit : natural := 6;
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constant c_hl_css_reg_rrp_reset_dis_bit : natural := 7;
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constant c_hl_css_reg_rrp_sweep_dis_bit : natural := 8;
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constant c_hl_css_reg_rrp_seek_dis_bit : natural := 9;
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constant c_hl_css_reg_rdv_dis_bit : natural := 10;
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constant c_hl_css_reg_poa_dis_bit : natural := 11;
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constant c_hl_css_reg_was_dis_bit : natural := 12;
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constant c_hl_css_reg_adv_rd_lat_dis_bit : natural := 13;
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constant c_hl_css_reg_adv_wr_lat_dis_bit : natural := 14;
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constant c_hl_css_reg_prep_customer_mr_setup_dis_bit : natural := 15;
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constant c_hl_css_reg_tracking_dis_bit : natural := 16;
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constant c_hl_ccs_num_stages : natural := 17;
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-- -----------------------------------------------------
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-- Constants for DRAM addresses used during calibration:
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-- -----------------------------------------------------
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-- the mtp training pattern is x30F5
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-- 1. write 0011 0000 and 1100 0000 such that one location will contains 0011 0000
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-- 2. write in 1111 0101
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-- also require locations containing all ones and all zeros
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-- default choice of calibration burst length (overriden to 8 for reads for DDR3 devices)
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constant c_cal_burst_len : natural := 4;
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constant c_cal_ofs_step_size : natural := 8;
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constant c_cal_ofs_zeros : natural := 0 * c_cal_ofs_step_size;
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constant c_cal_ofs_ones : natural := 1 * c_cal_ofs_step_size;
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constant c_cal_ofs_x30_almt_0 : natural := 2 * c_cal_ofs_step_size;
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constant c_cal_ofs_x30_almt_1 : natural := 3 * c_cal_ofs_step_size;
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constant c_cal_ofs_xF5 : natural := 5 * c_cal_ofs_step_size;
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constant c_cal_ofs_wd_lat : natural := 6 * c_cal_ofs_step_size;
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constant c_cal_data_len : natural := c_cal_ofs_wd_lat + c_cal_ofs_step_size;
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constant c_cal_ofs_mtp : natural := 6*c_cal_ofs_step_size;
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constant c_cal_ofs_mtp_len : natural := 4*4;
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constant c_cal_ofs_01_pairs : natural := 2 * c_cal_burst_len;
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constant c_cal_ofs_10_pairs : natural := 3 * c_cal_burst_len;
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constant c_cal_ofs_1100_step : natural := 4 * c_cal_burst_len;
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constant c_cal_ofs_0011_step : natural := 5 * c_cal_burst_len;
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-- -----------------------------------------------------
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-- Reset values. - These are chosen as default values for one PHY variation
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-- with DDR2 memory and CAS latency 6, however in each calibration
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-- mode these values will be set for a given PHY configuration.
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-- -----------------------------------------------------
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constant c_default_rd_lat : natural := 20;
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constant c_default_wr_lat : natural := 5;
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-- -----------------------------------------------------
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-- Errorcodes
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-- -----------------------------------------------------
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-- implemented
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constant C_SUCCESS : natural := 0;
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constant C_ERR_RESYNC_NO_VALID_PHASES : natural := 5; -- No valid data-valid windows found
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constant C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS : natural := 6; -- Multiple equally-sized data valid windows
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constant C_ERR_RESYNC_NO_INVALID_PHASES : natural := 7; -- No invalid data-valid windows found. Training patterns are designed so that there should always be at least one invalid phase.
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constant C_ERR_CRITICAL : natural := 15; -- A condition that can't happen just happened.
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constant C_ERR_READ_MTP_NO_VALID_ALMT : natural := 23;
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constant C_ERR_READ_MTP_BOTH_ALMT_PASS : natural := 24;
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constant C_ERR_WD_LAT_DISAGREEMENT : natural := 22; -- MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS copies of write-latency are written to memory. If all of these are not the same this error is generated.
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constant C_ERR_MAX_RD_LAT_EXCEEDED : natural := 25;
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constant C_ERR_MAX_TRK_SHFT_EXCEEDED : natural := 26;
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-- not implemented yet
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constant c_err_ac_lat_some_beats_are_different : natural := 1; -- implies DQ_1T setup failure or earlier.
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constant c_err_could_not_find_read_lat : natural := 2; -- dodgy RDP setup
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constant c_err_could_not_find_write_lat : natural := 3; -- dodgy WDP setup
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constant c_err_clock_cycle_iteration_timeout : natural := 8; -- depends on srate calling error -- GENERIC
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constant c_err_clock_cycle_it_timeout_rdp : natural := 9;
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constant c_err_clock_cycle_it_timeout_rdv : natural := 10;
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constant c_err_clock_cycle_it_timeout_poa : natural := 11;
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constant c_err_pll_ack_timeout : natural := 13;
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constant c_err_WindowProc_multiple_rsc_windows : natural := 16;
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constant c_err_WindowProc_window_det_no_ones : natural := 17;
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constant c_err_WindowProc_window_det_no_zeros : natural := 18;
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constant c_err_WindowProc_undefined : natural := 19; -- catch all
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constant c_err_tracked_mmc_offset_overflow : natural := 20;
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constant c_err_no_mimic_feedback : natural := 21;
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constant c_err_ctrl_ack_timeout : natural := 32;
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constant c_err_ctrl_done_timeout : natural := 33;
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-- -----------------------------------------------------
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-- PLL phase locations per device family
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-- (unused but a limited set is maintained here for reference)
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-- -----------------------------------------------------
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constant c_pll_resync_phs_select_ciii : natural := 5;
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constant c_pll_mimic_phs_select_ciii : natural := 4;
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constant c_pll_resync_phs_select_siii : natural := 5;
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constant c_pll_mimic_phs_select_siii : natural := 7;
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-- -----------------------------------------------------
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-- Maximum sizing constraints
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-- -----------------------------------------------------
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constant C_MAX_NUM_PLL_RSC_PHASES : natural := 32;
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-- -----------------------------------------------------
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-- IO control Params
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-- -----------------------------------------------------
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constant c_set_oct_to_rs : std_logic := '0';
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constant c_set_oct_to_rt : std_logic := '1';
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constant c_set_odt_rt : std_logic := '1';
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constant c_set_odt_off : std_logic := '0';
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--
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end altera_ddr_phy_alt_mem_phy_constants_pkg;
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--
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-- -----------------------------------------------------------------------------
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-- Abstract : record package for the non-levelling AFI sequencer
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-- The record package (alt_mem_phy_record_pkg) is used to combine
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-- command and status signals (into records) to be passed between
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-- sequencer blocks. It also contains type and record definitions
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-- for the stages of DRAM memory calibration.
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-- -----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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--
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package altera_ddr_phy_alt_mem_phy_record_pkg is
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-- set some maximum constraints to bound natural numbers below
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constant c_max_num_dqs_groups : natural := 24;
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constant c_max_num_pins : natural := 8;
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constant c_max_ranks : natural := 16;
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type t_family is (
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cyclone3,
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stratix2,
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stratix3
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);
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-- -----------------------------------------------------------------------
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-- the following are required for the non-levelling AFI PHY sequencer block interfaces
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-- -----------------------------------------------------------------------
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-- admin mode register settings (from mmi block)
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type t_admin_ctrl is record
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mr0 : std_logic_vector(12 downto 0);
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mr1 : std_logic_vector(12 downto 0);
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mr2 : std_logic_vector(12 downto 0);
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mr3 : std_logic_vector(12 downto 0);
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end record;
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function defaults return t_admin_ctrl;
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-- current admin status
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type t_admin_stat is record
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mr0 : std_logic_vector(12 downto 0);
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mr1 : std_logic_vector(12 downto 0);
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mr2 : std_logic_vector(12 downto 0);
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mr3 : std_logic_vector(12 downto 0);
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init_done : std_logic;
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end record;
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function defaults return t_admin_stat;
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-- mmi to iram ctrl signals
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type t_iram_ctrl is record
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addr : natural range 0 to 1023;
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wdata : std_logic_vector(31 downto 0);
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write : std_logic;
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read : std_logic;
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end record;
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function defaults return t_iram_ctrl;
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-- broadcast iram status to mmi and dgrb
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type t_iram_stat is record
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rdata : std_logic_vector(31 downto 0);
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done : std_logic;
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err : std_logic;
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err_code : std_logic_vector(3 downto 0);
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init_done : std_logic;
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out_of_mem : std_logic;
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contested_access : std_logic;
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end record;
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function defaults return t_iram_stat;
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-- codvw status signals from dgrb to mmi block
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type t_dgrb_mmi is record
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cal_codvw_phase : std_logic_vector(7 downto 0);
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cal_codvw_size : std_logic_vector(7 downto 0);
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codvw_trk_shift : std_logic_vector(11 downto 0);
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codvw_grt_one_dvw : std_logic;
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end record;
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function defaults return t_dgrb_mmi;
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-- signal to id which block is active
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type t_ctrl_active_block is (
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idle,
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admin,
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dgwb,
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dgrb,
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proc, -- unused in non-levelling AFI sequencer
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setup, -- unused in non-levelling AFI sequencer
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iram
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);
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function ret_proc return t_ctrl_active_block;
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function ret_dgrb return t_ctrl_active_block;
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-- control record for dgwb, dgrb, iram and admin blocks:
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-- the possible commands
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type t_ctrl_cmd_id is (
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cmd_idle,
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-- initialisation stages
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cmd_phy_initialise,
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cmd_init_dram,
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cmd_write_ihi,
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-- calibration stages
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cmd_write_btp,
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cmd_write_mtp,
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cmd_read_mtp,
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cmd_rrp_reset,
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cmd_rrp_sweep,
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cmd_rrp_seek,
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cmd_rdv,
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cmd_poa,
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cmd_was,
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-- advertise controller settings and re-configure for customer operation mode.
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cmd_prep_adv_rd_lat,
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cmd_prep_adv_wr_lat,
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cmd_prep_customer_mr_setup,
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cmd_tr_due
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);
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-- which block should execute each command
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function curr_active_block (
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ctrl_cmd_id : t_ctrl_cmd_id
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) return t_ctrl_active_block;
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-- specify command operands as a record
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type t_command_op is record
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current_cs : natural range 0 to c_max_ranks-1; -- which chip select is being calibrated
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single_bit : std_logic; -- current operation should be single bit
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mtp_almt : natural range 0 to 1; -- signals mtp alignment to be used for operation
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end record;
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function defaults return t_command_op;
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-- command request record (sent to each block)
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type t_ctrl_command is record
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command : t_ctrl_cmd_id;
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command_op : t_command_op;
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command_req : std_logic;
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end record;
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function defaults return t_ctrl_command;
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-- a generic status record for each block
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type t_ctrl_stat is record
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command_ack : std_logic;
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command_done : std_logic;
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command_result : std_logic_vector(7 downto 0 );
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command_err : std_logic;
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end record;
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334 |
|
|
|
335 |
|
|
function defaults return t_ctrl_stat;
|
336 |
|
|
|
337 |
|
|
-- push interface for dgwb / dgrb blocks (only the dgrb uses this interface at present)
|
338 |
|
|
type t_iram_push is record
|
339 |
|
|
iram_done : std_logic;
|
340 |
|
|
iram_write : std_logic;
|
341 |
|
|
iram_wordnum : natural range 0 to 255; -- acts as an offset to current location
|
342 |
|
|
iram_bitnum : natural range 0 to 31; -- for bitwise packing modes
|
343 |
|
|
iram_pushdata : std_logic_vector(31 downto 0); -- only bit zero used for bitwise packing_mode
|
344 |
|
|
end record;
|
345 |
|
|
|
346 |
|
|
function defaults return t_iram_push;
|
347 |
|
|
|
348 |
|
|
-- control block "master" state machine
|
349 |
|
|
type t_master_sm_state is
|
350 |
|
|
(
|
351 |
|
|
s_reset,
|
352 |
|
|
s_phy_initialise, -- wait for dll lock and init done flag from iram
|
353 |
|
|
s_init_dram, -- dram initialisation (in admin block)
|
354 |
|
|
s_write_ihi, -- write header information in iRAM
|
355 |
|
|
s_cal, -- check if calibration to be executed
|
356 |
|
|
s_write_btp, -- write burst training pattern
|
357 |
|
|
s_write_mtp, -- write more training pattern
|
358 |
|
|
s_read_mtp, -- read training patterns to find correct alignment for 1100 burst
|
359 |
|
|
-- (this is a special case of s_rrp_seek with no resych phase setting)
|
360 |
|
|
s_rrp_reset, -- read resync phase setup - reset initial conditions
|
361 |
|
|
s_rrp_sweep, -- read resync phase setup - sweep phases per chip select
|
362 |
|
|
s_rrp_seek, -- read resync phase setup - seek correct phase
|
363 |
|
|
s_rdv, -- read data valid setup
|
364 |
|
|
s_was, -- write datapath setup (ac to write data timing)
|
365 |
|
|
s_adv_rd_lat, -- advertise read latency
|
366 |
|
|
s_adv_wr_lat, -- advertise write latency
|
367 |
|
|
s_poa, -- calibrate the postamble (dqs based capture only)
|
368 |
|
|
s_tracking_setup, -- perform tracking (1st pass to setup mimic window)
|
369 |
|
|
s_prep_customer_mr_setup, -- apply user mode register settings (in admin block)
|
370 |
|
|
s_tracking, -- perform tracking (subsequent passes in user mode)
|
371 |
|
|
s_operational, -- calibration successful and in user mode
|
372 |
|
|
s_non_operational -- calibration unsuccessful and in user mode
|
373 |
|
|
);
|
374 |
|
|
|
375 |
|
|
-- record (set in mmi block) to disable calibration states
|
376 |
|
|
type t_hl_css_reg is record
|
377 |
|
|
|
378 |
|
|
phy_initialise_dis : std_logic;
|
379 |
|
|
init_dram_dis : std_logic;
|
380 |
|
|
write_ihi_dis : std_logic;
|
381 |
|
|
cal_dis : std_logic;
|
382 |
|
|
write_btp_dis : std_logic;
|
383 |
|
|
write_mtp_dis : std_logic;
|
384 |
|
|
read_mtp_dis : std_logic;
|
385 |
|
|
rrp_reset_dis : std_logic;
|
386 |
|
|
rrp_sweep_dis : std_logic;
|
387 |
|
|
rrp_seek_dis : std_logic;
|
388 |
|
|
rdv_dis : std_logic;
|
389 |
|
|
poa_dis : std_logic;
|
390 |
|
|
was_dis : std_logic;
|
391 |
|
|
adv_rd_lat_dis : std_logic;
|
392 |
|
|
adv_wr_lat_dis : std_logic;
|
393 |
|
|
prep_customer_mr_setup_dis : std_logic;
|
394 |
|
|
tracking_dis : std_logic;
|
395 |
|
|
end record;
|
396 |
|
|
|
397 |
|
|
function defaults return t_hl_css_reg;
|
398 |
|
|
|
399 |
|
|
-- record (set in ctrl block) to identify when a command has been acknowledged
|
400 |
|
|
type t_cal_stage_ack_seen is record
|
401 |
|
|
|
402 |
|
|
cal : std_logic;
|
403 |
|
|
phy_initialise : std_logic;
|
404 |
|
|
init_dram : std_logic;
|
405 |
|
|
write_ihi : std_logic;
|
406 |
|
|
write_btp : std_logic;
|
407 |
|
|
write_mtp : std_logic;
|
408 |
|
|
read_mtp : std_logic;
|
409 |
|
|
rrp_reset : std_logic;
|
410 |
|
|
rrp_sweep : std_logic;
|
411 |
|
|
rrp_seek : std_logic;
|
412 |
|
|
rdv : std_logic;
|
413 |
|
|
poa : std_logic;
|
414 |
|
|
was : std_logic;
|
415 |
|
|
adv_rd_lat : std_logic;
|
416 |
|
|
adv_wr_lat : std_logic;
|
417 |
|
|
prep_customer_mr_setup : std_logic;
|
418 |
|
|
tracking_setup : std_logic;
|
419 |
|
|
end record;
|
420 |
|
|
|
421 |
|
|
function defaults return t_cal_stage_ack_seen;
|
422 |
|
|
|
423 |
|
|
-- ctrl to mmi block interface (calibration status)
|
424 |
|
|
type t_ctrl_mmi is record
|
425 |
|
|
master_state_r : t_master_sm_state;
|
426 |
|
|
ctrl_calibration_success : std_logic;
|
427 |
|
|
ctrl_calibration_fail : std_logic;
|
428 |
|
|
ctrl_current_stage_done : std_logic;
|
429 |
|
|
ctrl_current_stage : t_ctrl_cmd_id;
|
430 |
|
|
ctrl_current_active_block : t_ctrl_active_block;
|
431 |
|
|
ctrl_cal_stage_ack_seen : t_cal_stage_ack_seen;
|
432 |
|
|
ctrl_err_code : std_logic_vector(7 downto 0);
|
433 |
|
|
end record;
|
434 |
|
|
|
435 |
|
|
function defaults return t_ctrl_mmi;
|
436 |
|
|
|
437 |
|
|
-- mmi to ctrl block interface (calibration control signals)
|
438 |
|
|
type t_mmi_ctrl is record
|
439 |
|
|
hl_css : t_hl_css_reg;
|
440 |
|
|
calibration_start : std_logic;
|
441 |
|
|
tracking_period_ms : natural range 0 to 255;
|
442 |
|
|
tracking_orvd_to_10ms : std_logic;
|
443 |
|
|
end record;
|
444 |
|
|
|
445 |
|
|
function defaults return t_mmi_ctrl;
|
446 |
|
|
|
447 |
|
|
-- algorithm parameterisation (generated in mmi block)
|
448 |
|
|
type t_algm_paramaterisation is record
|
449 |
|
|
num_phases_per_tck_pll : natural range 1 to 80;
|
450 |
|
|
nominal_dqs_delay : natural range 0 to 4;
|
451 |
|
|
pll_360_sweeps : natural range 0 to 15;
|
452 |
|
|
nominal_poa_phase_lead : natural range 0 to 7;
|
453 |
|
|
maximum_poa_delay : natural range 0 to 15;
|
454 |
|
|
odt_enabled : boolean;
|
455 |
|
|
extend_octrt_by : natural range 0 to 15;
|
456 |
|
|
delay_octrt_by : natural range 0 to 15;
|
457 |
|
|
tracking_period_ms : natural range 0 to 255;
|
458 |
|
|
end record;
|
459 |
|
|
|
460 |
|
|
-- interface between mmi and pll to control phase shifting
|
461 |
|
|
type t_mmi_pll_reconfig is record
|
462 |
|
|
pll_phs_shft_phase_sel : natural range 0 to 15;
|
463 |
|
|
pll_phs_shft_up_wc : std_logic;
|
464 |
|
|
pll_phs_shft_dn_wc : std_logic;
|
465 |
|
|
end record;
|
466 |
|
|
|
467 |
|
|
type t_pll_mmi is record
|
468 |
|
|
pll_busy : std_logic;
|
469 |
|
|
err : std_logic_vector(1 downto 0);
|
470 |
|
|
end record;
|
471 |
|
|
|
472 |
|
|
-- specify the iram configuration this is default
|
473 |
|
|
-- currently always dq_bitwise packing and a write mode of overwrite_ram
|
474 |
|
|
|
475 |
|
|
type t_iram_packing_mode is (
|
476 |
|
|
dq_bitwise,
|
477 |
|
|
dq_wordwise
|
478 |
|
|
);
|
479 |
|
|
|
480 |
|
|
type t_iram_write_mode is (
|
481 |
|
|
overwrite_ram,
|
482 |
|
|
or_into_ram,
|
483 |
|
|
and_into_ram
|
484 |
|
|
);
|
485 |
|
|
|
486 |
|
|
type t_ctrl_iram is record
|
487 |
|
|
packing_mode : t_iram_packing_mode;
|
488 |
|
|
write_mode : t_iram_write_mode;
|
489 |
|
|
active_block : t_ctrl_active_block;
|
490 |
|
|
end record;
|
491 |
|
|
|
492 |
|
|
function defaults return t_ctrl_iram;
|
493 |
|
|
|
494 |
|
|
-- -----------------------------------------------------------------------
|
495 |
|
|
-- the following are required for compliance to levelling AFI PHY interface but
|
496 |
|
|
-- are non-functional for non-levelling AFI PHY sequencer
|
497 |
|
|
-- -----------------------------------------------------------------------
|
498 |
|
|
|
499 |
|
|
type t_sc_ctrl_if is record
|
500 |
|
|
read : std_logic;
|
501 |
|
|
write : std_logic;
|
502 |
|
|
dqs_group_sel : std_logic_vector( 4 downto 0);
|
503 |
|
|
sc_in_group_sel : std_logic_vector( 5 downto 0);
|
504 |
|
|
wdata : std_logic_vector(45 downto 0);
|
505 |
|
|
op_type : std_logic_vector( 1 downto 0);
|
506 |
|
|
end record;
|
507 |
|
|
|
508 |
|
|
function defaults return t_sc_ctrl_if;
|
509 |
|
|
|
510 |
|
|
type t_sc_stat is record
|
511 |
|
|
rdata : std_logic_vector(45 downto 0);
|
512 |
|
|
busy : std_logic;
|
513 |
|
|
error_det : std_logic;
|
514 |
|
|
err_code : std_logic_vector(1 downto 0);
|
515 |
|
|
sc_cap : std_logic_vector(7 downto 0);
|
516 |
|
|
end record;
|
517 |
|
|
|
518 |
|
|
function defaults return t_sc_stat;
|
519 |
|
|
|
520 |
|
|
type t_element_to_reconfigure is (
|
521 |
|
|
pp_t9,
|
522 |
|
|
pp_t10,
|
523 |
|
|
pp_t1,
|
524 |
|
|
dqslb_rsc_phs,
|
525 |
|
|
dqslb_poa_phs_ofst,
|
526 |
|
|
dqslb_dqs_phs,
|
527 |
|
|
dqslb_dq_phs_ofst,
|
528 |
|
|
dqslb_dq_1t,
|
529 |
|
|
dqslb_dqs_1t,
|
530 |
|
|
dqslb_rsc_1t,
|
531 |
|
|
dqslb_div2_phs,
|
532 |
|
|
dqslb_oct_t9,
|
533 |
|
|
dqslb_oct_t10,
|
534 |
|
|
dqslb_poa_t7,
|
535 |
|
|
dqslb_poa_t11,
|
536 |
|
|
dqslb_dqs_dly,
|
537 |
|
|
dqslb_lvlng_byps
|
538 |
|
|
);
|
539 |
|
|
|
540 |
|
|
type t_sc_type is (
|
541 |
|
|
DQS_LB,
|
542 |
|
|
DQS_DQ_DM_PINS,
|
543 |
|
|
DQ_DM_PINS,
|
544 |
|
|
dqs_dqsn_pins,
|
545 |
|
|
dq_pin,
|
546 |
|
|
dqs_pin,
|
547 |
|
|
dm_pin,
|
548 |
|
|
dq_pins
|
549 |
|
|
);
|
550 |
|
|
|
551 |
|
|
type t_sc_int_ctrl is record
|
552 |
|
|
group_num : natural range 0 to c_max_num_dqs_groups;
|
553 |
|
|
group_type : t_sc_type;
|
554 |
|
|
pin_num : natural range 0 to c_max_num_pins;
|
555 |
|
|
sc_element : t_element_to_reconfigure;
|
556 |
|
|
prog_val : std_logic_vector(3 downto 0);
|
557 |
|
|
ram_set : std_logic;
|
558 |
|
|
sc_update : std_logic;
|
559 |
|
|
end record;
|
560 |
|
|
|
561 |
|
|
function defaults return t_sc_int_ctrl;
|
562 |
|
|
|
563 |
|
|
--
|
564 |
|
|
end altera_ddr_phy_alt_mem_phy_record_pkg;
|
565 |
|
|
|
566 |
|
|
--
|
567 |
|
|
package body altera_ddr_phy_alt_mem_phy_record_pkg IS
|
568 |
|
|
|
569 |
|
|
-- -----------------------------------------------------------------------
|
570 |
|
|
-- function implementations for the above declarations
|
571 |
|
|
-- these are mainly default conditions for records
|
572 |
|
|
-- -----------------------------------------------------------------------
|
573 |
|
|
|
574 |
|
|
function defaults return t_admin_ctrl is
|
575 |
|
|
variable output : t_admin_ctrl;
|
576 |
|
|
begin
|
577 |
|
|
output.mr0 := (others => '0');
|
578 |
|
|
output.mr1 := (others => '0');
|
579 |
|
|
output.mr2 := (others => '0');
|
580 |
|
|
output.mr3 := (others => '0');
|
581 |
|
|
return output;
|
582 |
|
|
end function;
|
583 |
|
|
|
584 |
|
|
function defaults return t_admin_stat is
|
585 |
|
|
variable output : t_admin_stat;
|
586 |
|
|
begin
|
587 |
|
|
output.mr0 := (others => '0');
|
588 |
|
|
output.mr1 := (others => '0');
|
589 |
|
|
output.mr2 := (others => '0');
|
590 |
|
|
output.mr3 := (others => '0');
|
591 |
|
|
return output;
|
592 |
|
|
end function;
|
593 |
|
|
|
594 |
|
|
|
595 |
|
|
function defaults return t_iram_ctrl is
|
596 |
|
|
variable output : t_iram_ctrl;
|
597 |
|
|
begin
|
598 |
|
|
output.addr := 0;
|
599 |
|
|
output.wdata := (others => '0');
|
600 |
|
|
output.write := '0';
|
601 |
|
|
output.read := '0';
|
602 |
|
|
return output;
|
603 |
|
|
end function;
|
604 |
|
|
|
605 |
|
|
function defaults return t_iram_stat is
|
606 |
|
|
variable output : t_iram_stat;
|
607 |
|
|
begin
|
608 |
|
|
output.rdata := (others => '0');
|
609 |
|
|
output.done := '0';
|
610 |
|
|
output.err := '0';
|
611 |
|
|
output.err_code := (others => '0');
|
612 |
|
|
output.init_done := '0';
|
613 |
|
|
output.out_of_mem := '0';
|
614 |
|
|
output.contested_access := '0';
|
615 |
|
|
return output;
|
616 |
|
|
end function;
|
617 |
|
|
|
618 |
|
|
function defaults return t_dgrb_mmi is
|
619 |
|
|
variable output : t_dgrb_mmi;
|
620 |
|
|
begin
|
621 |
|
|
output.cal_codvw_phase := (others => '0');
|
622 |
|
|
output.cal_codvw_size := (others => '0');
|
623 |
|
|
output.codvw_trk_shift := (others => '0');
|
624 |
|
|
output.codvw_grt_one_dvw := '0';
|
625 |
|
|
return output;
|
626 |
|
|
end function;
|
627 |
|
|
|
628 |
|
|
function ret_proc return t_ctrl_active_block is
|
629 |
|
|
variable output : t_ctrl_active_block;
|
630 |
|
|
begin
|
631 |
|
|
output := proc;
|
632 |
|
|
return output;
|
633 |
|
|
end function;
|
634 |
|
|
|
635 |
|
|
function ret_dgrb return t_ctrl_active_block is
|
636 |
|
|
variable output : t_ctrl_active_block;
|
637 |
|
|
begin
|
638 |
|
|
output := dgrb;
|
639 |
|
|
return output;
|
640 |
|
|
end function;
|
641 |
|
|
|
642 |
|
|
function defaults return t_ctrl_iram is
|
643 |
|
|
variable output : t_ctrl_iram;
|
644 |
|
|
begin
|
645 |
|
|
output.packing_mode := dq_bitwise;
|
646 |
|
|
output.write_mode := overwrite_ram;
|
647 |
|
|
output.active_block := idle;
|
648 |
|
|
return output;
|
649 |
|
|
end function;
|
650 |
|
|
|
651 |
|
|
function defaults return t_command_op is
|
652 |
|
|
variable output : t_command_op;
|
653 |
|
|
begin
|
654 |
|
|
output.current_cs := 0;
|
655 |
|
|
output.single_bit := '0';
|
656 |
|
|
output.mtp_almt := 0;
|
657 |
|
|
return output;
|
658 |
|
|
end function;
|
659 |
|
|
|
660 |
|
|
function defaults return t_ctrl_command is
|
661 |
|
|
variable output : t_ctrl_command;
|
662 |
|
|
begin
|
663 |
|
|
output.command := cmd_idle;
|
664 |
|
|
output.command_req := '0';
|
665 |
|
|
output.command_op := defaults;
|
666 |
|
|
return output;
|
667 |
|
|
end function;
|
668 |
|
|
|
669 |
|
|
-- decode which block is associated with which command
|
670 |
|
|
function curr_active_block (
|
671 |
|
|
ctrl_cmd_id : t_ctrl_cmd_id
|
672 |
|
|
) return t_ctrl_active_block is
|
673 |
|
|
begin
|
674 |
|
|
case ctrl_cmd_id is
|
675 |
|
|
when cmd_idle => return idle;
|
676 |
|
|
when cmd_phy_initialise => return idle;
|
677 |
|
|
when cmd_init_dram => return admin;
|
678 |
|
|
when cmd_write_ihi => return iram;
|
679 |
|
|
when cmd_write_btp => return dgwb;
|
680 |
|
|
when cmd_write_mtp => return dgwb;
|
681 |
|
|
when cmd_read_mtp => return dgrb;
|
682 |
|
|
when cmd_rrp_reset => return dgrb;
|
683 |
|
|
when cmd_rrp_sweep => return dgrb;
|
684 |
|
|
when cmd_rrp_seek => return dgrb;
|
685 |
|
|
when cmd_rdv => return dgrb;
|
686 |
|
|
when cmd_poa => return dgrb;
|
687 |
|
|
when cmd_was => return dgwb;
|
688 |
|
|
when cmd_prep_adv_rd_lat => return dgrb;
|
689 |
|
|
when cmd_prep_adv_wr_lat => return dgrb;
|
690 |
|
|
when cmd_prep_customer_mr_setup => return admin;
|
691 |
|
|
when cmd_tr_due => return dgrb;
|
692 |
|
|
when others => return idle;
|
693 |
|
|
end case;
|
694 |
|
|
end function;
|
695 |
|
|
|
696 |
|
|
function defaults return t_ctrl_stat is
|
697 |
|
|
variable output : t_ctrl_stat;
|
698 |
|
|
begin
|
699 |
|
|
output.command_ack := '0';
|
700 |
|
|
output.command_done := '0';
|
701 |
|
|
output.command_err := '0';
|
702 |
|
|
output.command_result := (others => '0');
|
703 |
|
|
return output;
|
704 |
|
|
end function;
|
705 |
|
|
|
706 |
|
|
function defaults return t_iram_push is
|
707 |
|
|
variable output : t_iram_push;
|
708 |
|
|
begin
|
709 |
|
|
output.iram_done := '0';
|
710 |
|
|
output.iram_write := '0';
|
711 |
|
|
output.iram_wordnum := 0;
|
712 |
|
|
output.iram_bitnum := 0;
|
713 |
|
|
output.iram_pushdata := (others => '0');
|
714 |
|
|
return output;
|
715 |
|
|
end function;
|
716 |
|
|
|
717 |
|
|
function defaults return t_hl_css_reg is
|
718 |
|
|
variable output : t_hl_css_reg;
|
719 |
|
|
begin
|
720 |
|
|
output.phy_initialise_dis := '0';
|
721 |
|
|
output.init_dram_dis := '0';
|
722 |
|
|
output.write_ihi_dis := '0';
|
723 |
|
|
output.cal_dis := '0';
|
724 |
|
|
output.write_btp_dis := '0';
|
725 |
|
|
output.write_mtp_dis := '0';
|
726 |
|
|
output.read_mtp_dis := '0';
|
727 |
|
|
output.rrp_reset_dis := '0';
|
728 |
|
|
output.rrp_sweep_dis := '0';
|
729 |
|
|
output.rrp_seek_dis := '0';
|
730 |
|
|
output.rdv_dis := '0';
|
731 |
|
|
output.poa_dis := '0';
|
732 |
|
|
output.was_dis := '0';
|
733 |
|
|
output.adv_rd_lat_dis := '0';
|
734 |
|
|
output.adv_wr_lat_dis := '0';
|
735 |
|
|
output.prep_customer_mr_setup_dis := '0';
|
736 |
|
|
output.tracking_dis := '0';
|
737 |
|
|
return output;
|
738 |
|
|
|
739 |
|
|
end function;
|
740 |
|
|
|
741 |
|
|
function defaults return t_cal_stage_ack_seen is
|
742 |
|
|
variable output : t_cal_stage_ack_seen;
|
743 |
|
|
begin
|
744 |
|
|
|
745 |
|
|
output.cal := '0';
|
746 |
|
|
output.phy_initialise := '0';
|
747 |
|
|
output.init_dram := '0';
|
748 |
|
|
output.write_ihi := '0';
|
749 |
|
|
output.write_btp := '0';
|
750 |
|
|
output.write_mtp := '0';
|
751 |
|
|
output.read_mtp := '0';
|
752 |
|
|
output.rrp_reset := '0';
|
753 |
|
|
output.rrp_sweep := '0';
|
754 |
|
|
output.rrp_seek := '0';
|
755 |
|
|
output.rdv := '0';
|
756 |
|
|
output.poa := '0';
|
757 |
|
|
output.was := '0';
|
758 |
|
|
output.adv_rd_lat := '0';
|
759 |
|
|
output.adv_wr_lat := '0';
|
760 |
|
|
output.prep_customer_mr_setup := '0';
|
761 |
|
|
output.tracking_setup := '0';
|
762 |
|
|
|
763 |
|
|
return output;
|
764 |
|
|
end function;
|
765 |
|
|
|
766 |
|
|
|
767 |
|
|
function defaults return t_mmi_ctrl is
|
768 |
|
|
variable output : t_mmi_ctrl;
|
769 |
|
|
begin
|
770 |
|
|
output.hl_css := defaults;
|
771 |
|
|
output.calibration_start := '0';
|
772 |
|
|
output.tracking_period_ms := 0;
|
773 |
|
|
output.tracking_orvd_to_10ms := '0';
|
774 |
|
|
return output;
|
775 |
|
|
end function;
|
776 |
|
|
|
777 |
|
|
|
778 |
|
|
|
779 |
|
|
function defaults return t_ctrl_mmi is
|
780 |
|
|
variable output : t_ctrl_mmi;
|
781 |
|
|
begin
|
782 |
|
|
output.master_state_r := s_reset;
|
783 |
|
|
output.ctrl_calibration_success := '0';
|
784 |
|
|
output.ctrl_calibration_fail := '0';
|
785 |
|
|
output.ctrl_current_stage_done := '0';
|
786 |
|
|
output.ctrl_current_stage := cmd_idle;
|
787 |
|
|
output.ctrl_current_active_block := idle;
|
788 |
|
|
output.ctrl_cal_stage_ack_seen := defaults;
|
789 |
|
|
output.ctrl_err_code := (others => '0');
|
790 |
|
|
return output;
|
791 |
|
|
end function;
|
792 |
|
|
|
793 |
|
|
-------------------------------------------------------------------------
|
794 |
|
|
-- the following are required for compliance to levelling AFI PHY interface but
|
795 |
|
|
-- are non-functional for non-levelling AFi PHY sequencer
|
796 |
|
|
-------------------------------------------------------------------------
|
797 |
|
|
|
798 |
|
|
function defaults return t_sc_ctrl_if is
|
799 |
|
|
variable output : t_sc_ctrl_if;
|
800 |
|
|
begin
|
801 |
|
|
output.read := '0';
|
802 |
|
|
output.write := '0';
|
803 |
|
|
output.dqs_group_sel := (others => '0');
|
804 |
|
|
output.sc_in_group_sel := (others => '0');
|
805 |
|
|
output.wdata := (others => '0');
|
806 |
|
|
output.op_type := (others => '0');
|
807 |
|
|
return output;
|
808 |
|
|
end function;
|
809 |
|
|
|
810 |
|
|
function defaults return t_sc_stat is
|
811 |
|
|
variable output : t_sc_stat;
|
812 |
|
|
begin
|
813 |
|
|
output.rdata := (others => '0');
|
814 |
|
|
output.busy := '0';
|
815 |
|
|
output.error_det := '0';
|
816 |
|
|
output.err_code := (others => '0');
|
817 |
|
|
output.sc_cap := (others => '0');
|
818 |
|
|
return output;
|
819 |
|
|
end function;
|
820 |
|
|
|
821 |
|
|
function defaults return t_sc_int_ctrl is
|
822 |
|
|
variable output : t_sc_int_ctrl;
|
823 |
|
|
begin
|
824 |
|
|
output.group_num := 0;
|
825 |
|
|
output.group_type := DQ_PIN;
|
826 |
|
|
output.pin_num := 0;
|
827 |
|
|
output.sc_element := pp_t9;
|
828 |
|
|
output.prog_val := (others => '0');
|
829 |
|
|
output.ram_set := '0';
|
830 |
|
|
output.sc_update := '0';
|
831 |
|
|
return output;
|
832 |
|
|
end function;
|
833 |
|
|
|
834 |
|
|
--
|
835 |
|
|
END altera_ddr_phy_alt_mem_phy_record_pkg;
|
836 |
|
|
--/* Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
|
837 |
|
|
-- use of Altera Corporation's design tools, logic functions and other
|
838 |
|
|
-- software and tools, and its AMPP partner logic functions, and any
|
839 |
|
|
-- output files any of the foregoing (including device programming or
|
840 |
|
|
-- simulation files), and any associated documentation or information are
|
841 |
|
|
-- expressly subject to the terms and conditions of the Altera Program
|
842 |
|
|
-- License Subscription Agreement or other applicable license agreement,
|
843 |
|
|
-- including, without limitation, that your use is for the sole purpose
|
844 |
|
|
-- of programming logic devices manufactured by Altera and sold by Altera
|
845 |
|
|
-- or its authorized distributors. Please refer to the applicable
|
846 |
|
|
-- agreement for further details. */
|
847 |
|
|
|
848 |
|
|
--
|
849 |
|
|
|
850 |
|
|
-- -----------------------------------------------------------------------------
|
851 |
|
|
-- Abstract : address and command package, shared between all variations of
|
852 |
|
|
-- the AFI sequencer
|
853 |
|
|
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is
|
854 |
|
|
-- used to combine DRAM address and command signals in one record
|
855 |
|
|
-- and unify the functions operating on this record.
|
856 |
|
|
--
|
857 |
|
|
--
|
858 |
|
|
-- -----------------------------------------------------------------------------
|
859 |
|
|
|
860 |
|
|
library ieee;
|
861 |
|
|
use ieee.std_logic_1164.all;
|
862 |
|
|
use ieee.numeric_std.all;
|
863 |
|
|
|
864 |
|
|
--
|
865 |
|
|
package altera_ddr_phy_alt_mem_phy_addr_cmd_pkg is
|
866 |
|
|
|
867 |
|
|
-- the following are bounds on the maximum range of address and command signals
|
868 |
|
|
constant c_max_addr_bits : natural := 15;
|
869 |
|
|
constant c_max_ba_bits : natural := 3;
|
870 |
|
|
constant c_max_ranks : natural := 16;
|
871 |
|
|
constant c_max_mode_reg_bit : natural := 12;
|
872 |
|
|
constant c_max_cmds_per_clk : natural := 4; -- quarter rate
|
873 |
|
|
|
874 |
|
|
-- a prefix for all report signals to identify phy and sequencer block
|
875 |
|
|
--
|
876 |
|
|
constant ac_report_prefix : string := "altera_ddr_phy_alt_mem_phy_seq (addr_cmd_pkg) : ";
|
877 |
|
|
|
878 |
|
|
-- -------------------------------------------------------------
|
879 |
|
|
-- this record represents a single mem_clk command cycle
|
880 |
|
|
-- -------------------------------------------------------------
|
881 |
|
|
type t_addr_cmd is record
|
882 |
|
|
addr : natural range 0 to 2**c_max_addr_bits - 1;
|
883 |
|
|
ba : natural range 0 to 2**c_max_ba_bits - 1;
|
884 |
|
|
cas_n : boolean;
|
885 |
|
|
ras_n : boolean;
|
886 |
|
|
we_n : boolean;
|
887 |
|
|
cke : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
|
888 |
|
|
cs_n : natural range 2**c_max_ranks - 1 downto 0; -- bounded max of 8 ranks
|
889 |
|
|
odt : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
|
890 |
|
|
rst_n : boolean;
|
891 |
|
|
end record t_addr_cmd;
|
892 |
|
|
|
893 |
|
|
-- -------------------------------------------------------------
|
894 |
|
|
-- this vector is used to describe the fact that for slower clock domains
|
895 |
|
|
-- mutiple commands per clock can be issued and encapsulates all these options in a
|
896 |
|
|
-- type which can scale with rate
|
897 |
|
|
-- -------------------------------------------------------------
|
898 |
|
|
type t_addr_cmd_vector is array (natural range <>) of t_addr_cmd;
|
899 |
|
|
|
900 |
|
|
-- -------------------------------------------------------------
|
901 |
|
|
-- this record is used to define the memory interface type and allow packing and checking
|
902 |
|
|
-- (it should be used as a generic to a entity or from a poject level constant)
|
903 |
|
|
-- -------------------------------------------------------------
|
904 |
|
|
|
905 |
|
|
-- enumeration for mem_type
|
906 |
|
|
type t_mem_type is
|
907 |
|
|
(
|
908 |
|
|
DDR,
|
909 |
|
|
DDR2,
|
910 |
|
|
DDR3
|
911 |
|
|
);
|
912 |
|
|
|
913 |
|
|
-- memory interface configuration parameters
|
914 |
|
|
type t_addr_cmd_config_rec is record
|
915 |
|
|
num_addr_bits : natural;
|
916 |
|
|
num_ba_bits : natural;
|
917 |
|
|
num_ranks : natural;
|
918 |
|
|
cmds_per_clk : natural range 1 to c_max_cmds_per_clk; -- commands per clock cycle (equal to DWIDTH_RATIO/2)
|
919 |
|
|
mem_type : t_mem_type;
|
920 |
|
|
end record;
|
921 |
|
|
|
922 |
|
|
-- -----------------------------------
|
923 |
|
|
-- the following type is used to switch between signals
|
924 |
|
|
-- (for example, in the mask function below)
|
925 |
|
|
-- -----------------------------------
|
926 |
|
|
type t_addr_cmd_signals is
|
927 |
|
|
(
|
928 |
|
|
addr,
|
929 |
|
|
ba,
|
930 |
|
|
cas_n,
|
931 |
|
|
ras_n,
|
932 |
|
|
we_n,
|
933 |
|
|
cke,
|
934 |
|
|
cs_n,
|
935 |
|
|
odt,
|
936 |
|
|
rst_n
|
937 |
|
|
);
|
938 |
|
|
|
939 |
|
|
-- -----------------------------------
|
940 |
|
|
-- odt record
|
941 |
|
|
-- to hold the odt settings
|
942 |
|
|
-- (an odt_record) per rank (in odt_array)
|
943 |
|
|
-- -----------------------------------
|
944 |
|
|
type t_odt_record is record
|
945 |
|
|
write : natural;
|
946 |
|
|
read : natural;
|
947 |
|
|
end record t_odt_record;
|
948 |
|
|
type t_odt_array is array (natural range <>) of t_odt_record;
|
949 |
|
|
|
950 |
|
|
-- -------------------------------------------------------------
|
951 |
|
|
-- exposed functions and procedures
|
952 |
|
|
--
|
953 |
|
|
-- these functions cover the following memory types:
|
954 |
|
|
-- DDR3, DDR2, DDR
|
955 |
|
|
--
|
956 |
|
|
-- and the following operations:
|
957 |
|
|
-- MRS, REF, PRE, PREA, ACT,
|
958 |
|
|
-- WR, WRS8, WRS4, WRA, WRAS8, WRAS4,
|
959 |
|
|
-- RD, RDS8, RDS4, RDA, RDAS8, RDAS4,
|
960 |
|
|
--
|
961 |
|
|
-- for DDR3 on the fly burst length setting for reads/writes
|
962 |
|
|
-- is supported
|
963 |
|
|
-- -------------------------------------------------------------
|
964 |
|
|
|
965 |
|
|
function defaults ( config_rec : in t_addr_cmd_config_rec
|
966 |
|
|
) return t_addr_cmd_vector;
|
967 |
|
|
|
968 |
|
|
function reset ( config_rec : in t_addr_cmd_config_rec
|
969 |
|
|
) return t_addr_cmd_vector;
|
970 |
|
|
|
971 |
|
|
function int_pup_reset ( config_rec : in t_addr_cmd_config_rec
|
972 |
|
|
) return t_addr_cmd_vector;
|
973 |
|
|
|
974 |
|
|
function deselect ( config_rec : in t_addr_cmd_config_rec;
|
975 |
|
|
previous : in t_addr_cmd_vector
|
976 |
|
|
) return t_addr_cmd_vector;
|
977 |
|
|
|
978 |
|
|
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
|
979 |
|
|
previous : in t_addr_cmd_vector;
|
980 |
|
|
ranks : in natural range 0 to 2**c_max_ranks -1
|
981 |
|
|
) return t_addr_cmd_vector;
|
982 |
|
|
|
983 |
|
|
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
|
984 |
|
|
ranks : in natural range 0 to 2**c_max_ranks -1
|
985 |
|
|
) return t_addr_cmd_vector;
|
986 |
|
|
|
987 |
|
|
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
|
988 |
|
|
previous : in t_addr_cmd_vector;
|
989 |
|
|
ranks : in natural range 0 to 2**c_max_ranks -1;
|
990 |
|
|
bank : in natural range 0 to 2**c_max_ba_bits -1
|
991 |
|
|
) return t_addr_cmd_vector;
|
992 |
|
|
|
993 |
|
|
function activate ( config_rec : in t_addr_cmd_config_rec;
|
994 |
|
|
previous : in t_addr_cmd_vector;
|
995 |
|
|
bank : in natural range 0 to 2**c_max_ba_bits -1;
|
996 |
|
|
row : in natural range 0 to 2**c_max_addr_bits -1;
|
997 |
|
|
ranks : in natural range 0 to 2**c_max_ranks - 1
|
998 |
|
|
) return t_addr_cmd_vector;
|
999 |
|
|
|
1000 |
|
|
function write ( config_rec : in t_addr_cmd_config_rec;
|
1001 |
|
|
previous : in t_addr_cmd_vector;
|
1002 |
|
|
bank : in natural range 0 to 2**c_max_ba_bits -1;
|
1003 |
|
|
col : in natural range 0 to 2**c_max_addr_bits -1;
|
1004 |
|
|
ranks : in natural range 0 to 2**c_max_ranks - 1;
|
1005 |
|
|
op_length : in natural range 1 to 8;
|
1006 |
|
|
auto_prech : in boolean
|
1007 |
|
|
) return t_addr_cmd_vector;
|
1008 |
|
|
|
1009 |
|
|
function read ( config_rec : in t_addr_cmd_config_rec;
|
1010 |
|
|
previous : in t_addr_cmd_vector;
|
1011 |
|
|
bank : in natural range 0 to 2**c_max_ba_bits -1;
|
1012 |
|
|
col : in natural range 0 to 2**c_max_addr_bits -1;
|
1013 |
|
|
ranks : in natural range 0 to 2**c_max_ranks - 1;
|
1014 |
|
|
op_length : in natural range 1 to 8;
|
1015 |
|
|
auto_prech : in boolean
|
1016 |
|
|
) return t_addr_cmd_vector;
|
1017 |
|
|
|
1018 |
|
|
function refresh ( config_rec : in t_addr_cmd_config_rec;
|
1019 |
|
|
previous : in t_addr_cmd_vector;
|
1020 |
|
|
ranks : in natural range 0 to 2**c_max_ranks -1
|
1021 |
|
|
) return t_addr_cmd_vector;
|
1022 |
|
|
|
1023 |
|
|
function self_refresh_entry ( config_rec : in t_addr_cmd_config_rec;
|
1024 |
|
|
previous : in t_addr_cmd_vector;
|
1025 |
|
|
ranks : in natural range 0 to 2**c_max_ranks -1
|
1026 |
|
|
) return t_addr_cmd_vector;
|
1027 |
|
|
|
1028 |
|
|
function load_mode ( config_rec : in t_addr_cmd_config_rec;
|
1029 |
|
|
mode_register_num : in natural range 0 to 3;
|
1030 |
|
|
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
|
1031 |
|
|
ranks : in natural range 0 to 2**c_max_ranks -1;
|
1032 |
|
|
remap_addr_and_ba : in boolean
|
1033 |
|
|
) return t_addr_cmd_vector;
|
1034 |
|
|
|
1035 |
|
|
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
|
1036 |
|
|
mode_reg_val : in std_logic_vector;
|
1037 |
|
|
rank_num : in natural range 0 to 2**c_max_ranks - 1;
|
1038 |
|
|
reorder_addr_bits : in boolean
|
1039 |
|
|
) return t_addr_cmd_vector;
|
1040 |
|
|
|
1041 |
|
|
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
|
1042 |
|
|
previous : in t_addr_cmd_vector;
|
1043 |
|
|
ranks : in natural range 0 to 2**c_max_ranks -1
|
1044 |
|
|
) return t_addr_cmd_vector;
|
1045 |
|
|
|
1046 |
|
|
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
|
1047 |
|
|
previous : in t_addr_cmd_vector;
|
1048 |
|
|
ranks : in natural range 0 to 2**c_max_ranks -1
|
1049 |
|
|
) return t_addr_cmd_vector;
|
1050 |
|
|
|
1051 |
|
|
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
|
1052 |
|
|
previous : in t_addr_cmd_vector;
|
1053 |
|
|
ranks : in natural range 0 to 2**c_max_ranks -1
|
1054 |
|
|
) return t_addr_cmd_vector;
|
1055 |
|
|
|
1056 |
|
|
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
|
1057 |
|
|
rank : in natural range 0 to 2**c_max_ranks -1
|
1058 |
|
|
) return t_addr_cmd_vector;
|
1059 |
|
|
|
1060 |
|
|
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
|
1061 |
|
|
rank : in natural range 0 to 2**c_max_ranks -1
|
1062 |
|
|
) return t_addr_cmd_vector;
|
1063 |
|
|
|
1064 |
|
|
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
|
1065 |
|
|
record_to_mask : in t_addr_cmd_vector;
|
1066 |
|
|
mem_ac_swapped_ranks : in std_logic_vector
|
1067 |
|
|
) return t_addr_cmd_vector;
|
1068 |
|
|
|
1069 |
|
|
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
|
1070 |
|
|
record_to_mask : in t_addr_cmd_vector;
|
1071 |
|
|
mem_ac_swapped_ranks : in std_logic_vector
|
1072 |
|
|
) return t_addr_cmd_vector;
|
1073 |
|
|
|
1074 |
|
|
-- -------------------------------------------------------------
|
1075 |
|
|
-- the following function sets up the odt settings
|
1076 |
|
|
-- NOTES: currently only supports DDR/DDR2 memories
|
1077 |
|
|
-- -------------------------------------------------------------
|
1078 |
|
|
|
1079 |
|
|
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
|
1080 |
|
|
function set_odt_values (ranks : natural;
|
1081 |
|
|
ranks_per_slot : natural;
|
1082 |
|
|
mem_type : in string
|
1083 |
|
|
) return t_odt_array;
|
1084 |
|
|
|
1085 |
|
|
-- -------------------------------------------------------------
|
1086 |
|
|
-- the following function enables assignment to the constant config_rec
|
1087 |
|
|
-- -------------------------------------------------------------
|
1088 |
|
|
function set_config_rec ( num_addr_bits : in natural;
|
1089 |
|
|
num_ba_bits : in natural;
|
1090 |
|
|
num_ranks : in natural;
|
1091 |
|
|
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
|
1092 |
|
|
mem_type : in string
|
1093 |
|
|
) return t_addr_cmd_config_rec;
|
1094 |
|
|
|
1095 |
|
|
|
1096 |
|
|
-- -------------------------------------------------------------
|
1097 |
|
|
-- the following function and procedure unpack address and
|
1098 |
|
|
-- command signals from the t_addr_cmd_vector format
|
1099 |
|
|
-- -------------------------------------------------------------
|
1100 |
|
|
|
1101 |
|
|
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
|
1102 |
|
|
config_rec : in t_addr_cmd_config_rec;
|
1103 |
|
|
addr : out std_logic_vector;
|
1104 |
|
|
ba : out std_logic_vector;
|
1105 |
|
|
cas_n : out std_logic_vector;
|
1106 |
|
|
ras_n : out std_logic_vector;
|
1107 |
|
|
we_n : out std_logic_vector;
|
1108 |
|
|
cke : out std_logic_vector;
|
1109 |
|
|
cs_n : out std_logic_vector;
|
1110 |
|
|
odt : out std_logic_vector;
|
1111 |
|
|
rst_n : out std_logic_vector);
|
1112 |
|
|
|
1113 |
|
|
|
1114 |
|
|
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
|
1115 |
|
|
addr_cmd_vector : in t_addr_cmd_vector;
|
1116 |
|
|
signal addr : out std_logic_vector;
|
1117 |
|
|
signal ba : out std_logic_vector;
|
1118 |
|
|
signal cas_n : out std_logic_vector;
|
1119 |
|
|
signal ras_n : out std_logic_vector;
|
1120 |
|
|
signal we_n : out std_logic_vector;
|
1121 |
|
|
signal cke : out std_logic_vector;
|
1122 |
|
|
signal cs_n : out std_logic_vector;
|
1123 |
|
|
signal odt : out std_logic_vector;
|
1124 |
|
|
signal rst_n : out std_logic_vector);
|
1125 |
|
|
|
1126 |
|
|
-- -------------------------------------------------------------
|
1127 |
|
|
-- the following functions perform bit masking to 0 or 1 (as
|
1128 |
|
|
-- specified by mask_value) to a chosen address/command signal (signal_name)
|
1129 |
|
|
-- across all signal bits or to a selected bit (mask_bit)
|
1130 |
|
|
-- -------------------------------------------------------------
|
1131 |
|
|
|
1132 |
|
|
-- mask all signal bits procedure
|
1133 |
|
|
function mask ( config_rec : in t_addr_cmd_config_rec;
|
1134 |
|
|
addr_cmd_vector : in t_addr_cmd_vector;
|
1135 |
|
|
signal_name : in t_addr_cmd_signals;
|
1136 |
|
|
mask_value : in std_logic) return t_addr_cmd_vector;
|
1137 |
|
|
|
1138 |
|
|
procedure mask( config_rec : in t_addr_cmd_config_rec;
|
1139 |
|
|
signal addr_cmd_vector : inout t_addr_cmd_vector;
|
1140 |
|
|
signal_name : in t_addr_cmd_signals;
|
1141 |
|
|
mask_value : in std_logic);
|
1142 |
|
|
|
1143 |
|
|
-- mask signal bit (mask_bit) procedure
|
1144 |
|
|
function mask ( config_rec : in t_addr_cmd_config_rec;
|
1145 |
|
|
addr_cmd_vector : in t_addr_cmd_vector;
|
1146 |
|
|
signal_name : in t_addr_cmd_signals;
|
1147 |
|
|
mask_value : in std_logic;
|
1148 |
|
|
mask_bit : in natural) return t_addr_cmd_vector;
|
1149 |
|
|
|
1150 |
|
|
--
|
1151 |
|
|
end altera_ddr_phy_alt_mem_phy_addr_cmd_pkg;
|
1152 |
|
|
|
1153 |
|
|
|
1154 |
|
|
--
|
1155 |
|
|
package body altera_ddr_phy_alt_mem_phy_addr_cmd_pkg IS
|
1156 |
|
|
|
1157 |
|
|
-- -------------------------------------------------------------
|
1158 |
|
|
-- Basic functions for a single command
|
1159 |
|
|
-- -------------------------------------------------------------
|
1160 |
|
|
|
1161 |
|
|
-- -------------------------------------------------------------
|
1162 |
|
|
-- defaults the bus no JEDEC abbreviated name
|
1163 |
|
|
-- -------------------------------------------------------------
|
1164 |
|
|
function defaults ( config_rec : in t_addr_cmd_config_rec
|
1165 |
|
|
) return t_addr_cmd
|
1166 |
|
|
is
|
1167 |
|
|
variable v_retval : t_addr_cmd;
|
1168 |
|
|
begin
|
1169 |
|
|
|
1170 |
|
|
v_retval.addr := 0;
|
1171 |
|
|
v_retval.ba := 0;
|
1172 |
|
|
v_retval.cas_n := false;
|
1173 |
|
|
v_retval.ras_n := false;
|
1174 |
|
|
v_retval.we_n := false;
|
1175 |
|
|
v_retval.cke := (2 ** config_rec.num_ranks) -1;
|
1176 |
|
|
v_retval.cs_n := (2 ** config_rec.num_ranks) -1;
|
1177 |
|
|
v_retval.odt := 0;
|
1178 |
|
|
v_retval.rst_n := false;
|
1179 |
|
|
|
1180 |
|
|
return v_retval;
|
1181 |
|
|
|
1182 |
|
|
end function;
|
1183 |
|
|
|
1184 |
|
|
-- -------------------------------------------------------------
|
1185 |
|
|
-- resets the addr/cmd signal (Same as default with cke and rst_n 0 )
|
1186 |
|
|
-- -------------------------------------------------------------
|
1187 |
|
|
function reset ( config_rec : in t_addr_cmd_config_rec
|
1188 |
|
|
) return t_addr_cmd
|
1189 |
|
|
is
|
1190 |
|
|
variable v_retval : t_addr_cmd;
|
1191 |
|
|
begin
|
1192 |
|
|
|
1193 |
|
|
v_retval := defaults(config_rec);
|
1194 |
|
|
v_retval.cke := 0;
|
1195 |
|
|
if config_rec.mem_type = DDR3 then
|
1196 |
|
|
v_retval.rst_n := true;
|
1197 |
|
|
end if;
|
1198 |
|
|
return v_retval;
|
1199 |
|
|
|
1200 |
|
|
end function;
|
1201 |
|
|
|
1202 |
|
|
-- -------------------------------------------------------------
|
1203 |
|
|
-- issues deselect (command) JEDEC abbreviated name: DES
|
1204 |
|
|
-- -------------------------------------------------------------
|
1205 |
|
|
function deselect ( config_rec : in t_addr_cmd_config_rec;
|
1206 |
|
|
previous : in t_addr_cmd
|
1207 |
|
|
) return t_addr_cmd
|
1208 |
|
|
is
|
1209 |
|
|
variable v_retval : t_addr_cmd;
|
1210 |
|
|
begin
|
1211 |
|
|
|
1212 |
|
|
v_retval := previous;
|
1213 |
|
|
|
1214 |
|
|
v_retval.cs_n := (2 ** config_rec.num_ranks) -1;
|
1215 |
|
|
v_retval.cke := (2 ** config_rec.num_ranks) -1;
|
1216 |
|
|
v_retval.rst_n := false;
|
1217 |
|
|
|
1218 |
|
|
return v_retval;
|
1219 |
|
|
|
1220 |
|
|
end function;
|
1221 |
|
|
|
1222 |
|
|
-- -------------------------------------------------------------
|
1223 |
|
|
-- issues a precharge all command JEDEC abbreviated name: PREA
|
1224 |
|
|
-- -------------------------------------------------------------
|
1225 |
|
|
function precharge_all( config_rec : in t_addr_cmd_config_rec;
|
1226 |
|
|
previous : in t_addr_cmd;
|
1227 |
|
|
ranks : in natural range 0 to 2**c_max_ranks -1
|
1228 |
|
|
) return t_addr_cmd
|
1229 |
|
|
is
|
1230 |
|
|
variable v_retval : t_addr_cmd;
|
1231 |
|
|
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
|
1232 |
|
|
begin
|
1233 |
|
|
|
1234 |
|
|
v_retval := previous;
|
1235 |
|
|
|
1236 |
|
|
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
|
1237 |
|
|
v_addr(10) := '1'; -- set AP bit high
|
1238 |
|
|
v_retval.addr := to_integer(v_addr);
|
1239 |
|
|
|
1240 |
|
|
v_retval.ras_n := true;
|
1241 |
|
|
v_retval.cas_n := false;
|
1242 |
|
|
v_retval.we_n := true;
|
1243 |
|
|
v_retval.cs_n := (2 ** config_rec.num_ranks) - 1 - ranks;
|
1244 |
|
|
v_retval.cke := (2 ** config_rec.num_ranks) -1;
|
1245 |
|
|
v_retval.rst_n := false;
|
1246 |
|
|
|
1247 |
|
|
return v_retval;
|
1248 |
|
|
|
1249 |
|
|
end function;
|
1250 |
|
|
|
1251 |
|
|
-- -------------------------------------------------------------
|
1252 |
|
|
-- precharge (close) a bank JEDEC abbreviated name: PRE
|
1253 |
|
|
-- -------------------------------------------------------------
|
1254 |
|
|
function precharge_bank( config_rec : in t_addr_cmd_config_rec;
|
1255 |
|
|
previous : in t_addr_cmd;
|
1256 |
|
|
ranks : in natural range 0 to 2**c_max_ranks -1;
|
1257 |
|
|
bank : in natural range 0 to 2**c_max_ba_bits -1
|
1258 |
|
|
) return t_addr_cmd
|
1259 |
|
|
is
|
1260 |
|
|
variable v_retval : t_addr_cmd;
|
1261 |
|
|
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
|
1262 |
|
|
begin
|
1263 |
|
|
|
1264 |
|
|
v_retval := previous;
|
1265 |
|
|
|
1266 |
|
|
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
|
1267 |
|
|
v_addr(10) := '0'; -- set AP bit low
|
1268 |
|
|
v_retval.addr := to_integer(v_addr);
|
1269 |
|
|
|
1270 |
|
|
v_retval.ba := bank;
|
1271 |
|
|
|
1272 |
|
|
v_retval.ras_n := true;
|
1273 |
|
|
v_retval.cas_n := false;
|
1274 |
|
|
v_retval.we_n := true;
|
1275 |
|
|
v_retval.cs_n := (2 ** config_rec.num_ranks) - ranks;
|
1276 |
|
|
v_retval.cke := (2 ** config_rec.num_ranks) -1;
|
1277 |
|
|
v_retval.rst_n := false;
|
1278 |
|
|
|
1279 |
|
|
return v_retval;
|
1280 |
|
|
|
1281 |
|
|
end function;
|
1282 |
|
|
|
1283 |
|
|
|
1284 |
|
|
-- -------------------------------------------------------------
|
1285 |
|
|
-- Issues a activate (open row) JEDEC abbreviated name: ACT
|
1286 |
|
|
-- -------------------------------------------------------------
|
1287 |
|
|
function activate (config_rec : in t_addr_cmd_config_rec;
|
1288 |
|
|
previous : in t_addr_cmd;
|
1289 |
|
|
bank : in natural range 0 to 2**c_max_ba_bits - 1;
|
1290 |
|
|
row : in natural range 0 to 2**c_max_addr_bits - 1;
|
1291 |
|
|
ranks : in natural range 0 to 2**c_max_ranks - 1
|
1292 |
|
|
) return t_addr_cmd
|
1293 |
|
|
is
|
1294 |
|
|
variable v_retval : t_addr_cmd;
|
1295 |
|
|
begin
|
1296 |
|
|
|
1297 |
|
|
v_retval.addr := row;
|
1298 |
|
|
v_retval.ba := bank;
|
1299 |
|
|
v_retval.cas_n := false;
|
1300 |
|
|
v_retval.ras_n := true;
|
1301 |
|
|
v_retval.we_n := false;
|
1302 |
|
|
v_retval.cke := (2 ** config_rec.num_ranks) -1;
|
1303 |
|
|
v_retval.cs_n := (2 ** config_rec.num_ranks) -1 - ranks;
|
1304 |
|
|
v_retval.odt := previous.odt;
|
1305 |
|
|
v_retval.rst_n := false;
|
1306 |
|
|
|
1307 |
|
|
return v_retval;
|
1308 |
|
|
|
1309 |
|
|
end function;
|
1310 |
|
|
|
1311 |
|
|
|
1312 |
|
|
-- -------------------------------------------------------------
|
1313 |
|
|
-- issues a write command JEDEC abbreviated name:WR, WRA
|
1314 |
|
|
-- WRS4, WRAS4
|
1315 |
|
|
-- WRS8, WRAS8
|
1316 |
|
|
-- has the ability to support:
|
1317 |
|
|
-- DDR3:
|
1318 |
|
|
-- BL4, BL8, fixed BL
|
1319 |
|
|
-- Auto Precharge (AP)
|
1320 |
|
|
-- DDR2, DDR:
|
1321 |
|
|
-- fixed BL
|
1322 |
|
|
-- Auto Precharge (AP)
|
1323 |
|
|
-- -------------------------------------------------------------
|
1324 |
|
|
function write (config_rec : in t_addr_cmd_config_rec;
|
1325 |
|
|
previous : in t_addr_cmd;
|
1326 |
|
|
bank : in natural range 0 to 2**c_max_ba_bits -1;
|
1327 |
|
|
col : in natural range 0 to 2**c_max_addr_bits -1;
|
1328 |
|
|
ranks : in natural range 0 to 2**c_max_ranks -1;
|
1329 |
|
|
op_length : in natural range 1 to 8;
|
1330 |
|
|
auto_prech : in boolean
|
1331 |
|
|
) return t_addr_cmd
|
1332 |
|
|
is
|
1333 |
|
|
variable v_retval : t_addr_cmd;
|
1334 |
|
|
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
|
1335 |
|
|
begin
|
1336 |
|
|
|
1337 |
|
|
-- calculate correct address signal
|
1338 |
|
|
v_addr := to_unsigned(col, c_max_addr_bits);
|
1339 |
|
|
|
1340 |
|
|
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
|
1341 |
|
|
v_retval.addr := to_integer(v_addr(9 downto 0));
|
1342 |
|
|
|
1343 |
|
|
if v_addr(10) = '1' then
|
1344 |
|
|
v_retval.addr := v_retval.addr + 2**11;
|
1345 |
|
|
end if;
|
1346 |
|
|
|
1347 |
|
|
if auto_prech = true then -- set AP bit (A10)
|
1348 |
|
|
v_retval.addr := v_retval.addr + 2**10;
|
1349 |
|
|
end if;
|
1350 |
|
|
|
1351 |
|
|
if config_rec.mem_type = DDR3 then
|
1352 |
|
|
|
1353 |
|
|
if op_length = 8 then -- set BL_OTF sel bit (A12)
|
1354 |
|
|
v_retval.addr := v_retval.addr + 2**12;
|
1355 |
|
|
elsif op_length = 4 then
|
1356 |
|
|
null;
|
1357 |
|
|
else
|
1358 |
|
|
report ac_report_prefix & "DDR3 DRAM only supports writes of burst length 4 or 8, the requested length was: " & integer'image(op_length) severity failure;
|
1359 |
|
|
end if;
|
1360 |
|
|
|
1361 |
|
|
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
|
1362 |
|
|
|
1363 |
|
|
null;
|
1364 |
|
|
|
1365 |
|
|
else
|
1366 |
|
|
report ac_report_prefix & "only DDR memories are supported for memory writes" severity failure;
|
1367 |
|
|
end if;
|
1368 |
|
|
|
1369 |
|
|
-- set a/c signal assignments for write
|
1370 |
|
|
v_retval.ba := bank;
|
1371 |
|
|
v_retval.cas_n := true;
|
1372 |
|
|
v_retval.ras_n := false;
|
1373 |
|
|
v_retval.we_n := true;
|
1374 |
|
|
v_retval.cke := (2 ** config_rec.num_ranks) -1;
|
1375 |
|
|
v_retval.cs_n := (2 ** config_rec.num_ranks) -1 - ranks;
|
1376 |
|
|
v_retval.odt := ranks;
|
1377 |
|
|
v_retval.rst_n := false;
|
1378 |
|
|
|
1379 |
|
|
return v_retval;
|
1380 |
|
|
|
1381 |
|
|
end function;
|
1382 |
|
|
|
1383 |
|
|
-- -------------------------------------------------------------
|
1384 |
|
|
-- issues a read command JEDEC abbreviated name: RD, RDA
|
1385 |
|
|
-- RDS4, RDAS4
|
1386 |
|
|
-- RDS8, RDAS8
|
1387 |
|
|
-- has the ability to support:
|
1388 |
|
|
-- DDR3:
|
1389 |
|
|
-- BL4, BL8, fixed BL
|
1390 |
|
|
-- Auto Precharge (AP)
|
1391 |
|
|
-- DDR2, DDR:
|
1392 |
|
|
-- fixed BL, Auto Precharge (AP)
|
1393 |
|
|
-- -------------------------------------------------------------
|
1394 |
|
|
function read (config_rec : in t_addr_cmd_config_rec;
|
1395 |
|
|
previous : in t_addr_cmd;
|
1396 |
|
|
bank : in natural range 0 to 2**c_max_ba_bits -1;
|
1397 |
|
|
col : in natural range 0 to 2**c_max_addr_bits -1;
|
1398 |
|
|
ranks : in natural range 0 to 2**c_max_ranks -1;
|
1399 |
|
|
op_length : in natural range 1 to 8;
|
1400 |
|
|
auto_prech : in boolean
|
1401 |
|
|
) return t_addr_cmd
|
1402 |
|
|
is
|
1403 |
|
|
variable v_retval : t_addr_cmd;
|
1404 |
|
|
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
|
1405 |
|
|
begin
|
1406 |
|
|
|
1407 |
|
|
-- calculate correct address signal
|
1408 |
|
|
v_addr := to_unsigned(col, c_max_addr_bits);
|
1409 |
|
|
|
1410 |
|
|
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
|
1411 |
|
|
v_retval.addr := to_integer(v_addr(9 downto 0));
|
1412 |
|
|
|
1413 |
|
|
if v_addr(10) = '1' then
|
1414 |
|
|
v_retval.addr := v_retval.addr + 2**11;
|
1415 |
|
|
end if;
|
1416 |
|
|
|
1417 |
|
|
if auto_prech = true then -- set AP bit (A10)
|
1418 |
|
|
v_retval.addr := v_retval.addr + 2**10;
|
1419 |
|
|
end if;
|
1420 |
|
|
|
1421 |
|
|
if config_rec.mem_type = DDR3 then
|
1422 |
|
|
|
1423 |
|
|
if op_length = 8 then -- set BL_OTF sel bit (A12)
|
1424 |
|
|
v_retval.addr := v_retval.addr + 2**12;
|
1425 |
|
|
elsif op_length = 4 then
|
1426 |
|
|
null;
|
1427 |
|
|
else
|
1428 |
|
|
report ac_report_prefix & "DDR3 DRAM only supports reads of burst length 4 or 8" severity failure;
|
1429 |
|
|
end if;
|
1430 |
|
|
|
1431 |
|
|
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
|
1432 |
|
|
|
1433 |
|
|
null;
|
1434 |
|
|
|
1435 |
|
|
else
|
1436 |
|
|
report ac_report_prefix & "only DDR memories are supported for memory reads" severity failure;
|
1437 |
|
|
end if;
|
1438 |
|
|
|
1439 |
|
|
-- set a/c signals for read command
|
1440 |
|
|
v_retval.ba := bank;
|
1441 |
|
|
v_retval.cas_n := true;
|
1442 |
|
|
v_retval.ras_n := false;
|
1443 |
|
|
v_retval.we_n := false;
|
1444 |
|
|
v_retval.cke := (2 ** config_rec.num_ranks) -1;
|
1445 |
|
|
v_retval.cs_n := (2 ** config_rec.num_ranks) -1 - ranks;
|
1446 |
|
|
v_retval.odt := 0;
|
1447 |
|
|
v_retval.rst_n := false;
|
1448 |
|
|
return v_retval;
|
1449 |
|
|
|
1450 |
|
|
end function;
|
1451 |
|
|
|
1452 |
|
|
-- -------------------------------------------------------------
|
1453 |
|
|
-- issues a refresh command JEDEC abbreviated name: REF
|
1454 |
|
|
-- -------------------------------------------------------------
|
1455 |
|
|
function refresh (config_rec : in t_addr_cmd_config_rec;
|
1456 |
|
|
previous : in t_addr_cmd;
|
1457 |
|
|
ranks : in natural range 0 to 2**c_max_ranks -1
|
1458 |
|
|
)
|
1459 |
|
|
return t_addr_cmd
|
1460 |
|
|
is
|
1461 |
|
|
variable v_retval : t_addr_cmd;
|
1462 |
|
|
begin
|
1463 |
|
|
|
1464 |
|
|
v_retval := previous;
|
1465 |
|
|
|
1466 |
|
|
v_retval.cas_n := true;
|
1467 |
|
|
v_retval.ras_n := true;
|
1468 |
|
|
v_retval.we_n := false;
|
1469 |
|
|
v_retval.cke := (2 ** config_rec.num_ranks) -1;
|
1470 |
|
|
v_retval.cs_n := (2 ** config_rec.num_ranks) -1 - ranks;
|
1471 |
|
|
v_retval.rst_n := false;
|
1472 |
|
|
|
1473 |
|
|
-- addr, BA and ODT are don't care therfore leave as previous value
|
1474 |
|
|
|
1475 |
|
|
return v_retval;
|
1476 |
|
|
|
1477 |
|
|
end function;
|
1478 |
|
|
|
1479 |
|
|
|
1480 |
|
|
-- -------------------------------------------------------------
|
1481 |
|
|
-- issues a mode register set command JEDEC abbreviated name: MRS
|
1482 |
|
|
-- -------------------------------------------------------------
|
1483 |
|
|
function load_mode ( config_rec : in t_addr_cmd_config_rec;
|
1484 |
|
|
mode_register_num : in natural range 0 to 3;
|
1485 |
|
|
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
|
1486 |
|
|
ranks : in natural range 0 to 2**c_max_ranks -1;
|
1487 |
|
|
remap_addr_and_ba : in boolean
|
1488 |
|
|
) return t_addr_cmd
|
1489 |
|
|
is
|
1490 |
|
|
variable v_retval : t_addr_cmd;
|
1491 |
|
|
variable v_addr_remap : unsigned(c_max_mode_reg_bit downto 0);
|
1492 |
|
|
begin
|
1493 |
|
|
|
1494 |
|
|
v_retval.cas_n := true;
|
1495 |
|
|
v_retval.ras_n := true;
|
1496 |
|
|
v_retval.we_n := true;
|
1497 |
|
|
v_retval.cke := (2 ** config_rec.num_ranks) -1;
|
1498 |
|
|
v_retval.cs_n := (2 ** config_rec.num_ranks) -1 - ranks;
|
1499 |
|
|
v_retval.odt := 0;
|
1500 |
|
|
v_retval.rst_n := false;
|
1501 |
|
|
|
1502 |
|
|
v_retval.ba := mode_register_num;
|
1503 |
|
|
v_retval.addr := to_integer(unsigned(mode_reg_value));
|
1504 |
|
|
|
1505 |
|
|
if remap_addr_and_ba = true then
|
1506 |
|
|
v_addr_remap := unsigned(mode_reg_value);
|
1507 |
|
|
v_addr_remap(8 downto 7) := v_addr_remap(7) & v_addr_remap(8);
|
1508 |
|
|
v_addr_remap(6 downto 5) := v_addr_remap(5) & v_addr_remap(6);
|
1509 |
|
|
v_addr_remap(4 downto 3) := v_addr_remap(3) & v_addr_remap(4);
|
1510 |
|
|
|
1511 |
|
|
v_retval.addr := to_integer(v_addr_remap);
|
1512 |
|
|
|
1513 |
|
|
v_addr_remap := to_unsigned(mode_register_num, c_max_mode_reg_bit + 1);
|
1514 |
|
|
v_addr_remap(1 downto 0) := v_addr_remap(0) & v_addr_remap(1);
|
1515 |
|
|
|
1516 |
|
|
v_retval.ba := to_integer(v_addr_remap);
|
1517 |
|
|
|
1518 |
|
|
end if;
|
1519 |
|
|
|
1520 |
|
|
return v_retval;
|
1521 |
|
|
|
1522 |
|
|
end function;
|
1523 |
|
|
|
1524 |
|
|
|
1525 |
|
|
-- -------------------------------------------------------------
|
1526 |
|
|
-- maintains SR or PD mode on slected ranks.
|
1527 |
|
|
-- -------------------------------------------------------------
|
1528 |
|
|
function maintain_pd_or_sr (config_rec : in t_addr_cmd_config_rec;
|
1529 |
|
|
previous : in t_addr_cmd;
|
1530 |
|
|
ranks : in natural range 0 to 2**c_max_ranks -1
|
1531 |
|
|
)
|
1532 |
|
|
return t_addr_cmd
|
1533 |
|
|
is
|
1534 |
|
|
variable v_retval : t_addr_cmd;
|
1535 |
|
|
begin
|
1536 |
|
|
v_retval := previous;
|
1537 |
|
|
v_retval.cke := (2 ** config_rec.num_ranks) - 1 - ranks;
|
1538 |
|
|
return v_retval;
|
1539 |
|
|
end function;
|
1540 |
|
|
|
1541 |
|
|
|
1542 |
|
|
-- -------------------------------------------------------------
|
1543 |
|
|
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
|
1544 |
|
|
-- NOTE - can only be issued to a single RANK at a time.
|
1545 |
|
|
-- -------------------------------------------------------------
|
1546 |
|
|
function ZQCS (config_rec : in t_addr_cmd_config_rec;
|
1547 |
|
|
rank : in natural range 0 to 2**c_max_ranks -1
|
1548 |
|
|
)
|
1549 |
|
|
return t_addr_cmd
|
1550 |
|
|
is
|
1551 |
|
|
variable v_retval : t_addr_cmd;
|
1552 |
|
|
begin
|
1553 |
|
|
|
1554 |
|
|
|
1555 |
|
|
v_retval.cas_n := false;
|
1556 |
|
|
v_retval.ras_n := false;
|
1557 |
|
|
v_retval.we_n := true;
|
1558 |
|
|
v_retval.cke := (2 ** config_rec.num_ranks) -1;
|
1559 |
|
|
v_retval.cs_n := (2 ** config_rec.num_ranks) -1 - rank;
|
1560 |
|
|
v_retval.rst_n := false;
|
1561 |
|
|
|
1562 |
|
|
v_retval.addr := 0; -- clear bit 10
|
1563 |
|
|
v_retval.ba := 0;
|
1564 |
|
|
v_retval.odt := 0;
|
1565 |
|
|
return v_retval;
|
1566 |
|
|
|
1567 |
|
|
end function;
|
1568 |
|
|
|
1569 |
|
|
|
1570 |
|
|
|
1571 |
|
|
-- -------------------------------------------------------------
|
1572 |
|
|
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
|
1573 |
|
|
-- NOTE - can only be issued to a single RANK at a time.
|
1574 |
|
|
-- -------------------------------------------------------------
|
1575 |
|
|
function ZQCL (config_rec : in t_addr_cmd_config_rec;
|
1576 |
|
|
rank : in natural range 0 to 2**c_max_ranks -1
|
1577 |
|
|
)
|
1578 |
|
|
return t_addr_cmd
|
1579 |
|
|
is
|
1580 |
|
|
variable v_retval : t_addr_cmd;
|
1581 |
|
|
begin
|
1582 |
|
|
|
1583 |
|
|
v_retval.cas_n := false;
|
1584 |
|
|
v_retval.ras_n := false;
|
1585 |
|
|
v_retval.we_n := true;
|
1586 |
|
|
v_retval.cke := (2 ** config_rec.num_ranks) -1;
|
1587 |
|
|
v_retval.cs_n := (2 ** config_rec.num_ranks) -1 - rank;
|
1588 |
|
|
v_retval.rst_n := false;
|
1589 |
|
|
|
1590 |
|
|
v_retval.addr := 1024; -- set bit 10
|
1591 |
|
|
v_retval.ba := 0;
|
1592 |
|
|
v_retval.odt := 0;
|
1593 |
|
|
return v_retval;
|
1594 |
|
|
|
1595 |
|
|
end function;
|
1596 |
|
|
|
1597 |
|
|
|
1598 |
|
|
-- -------------------------------------------------------------
|
1599 |
|
|
-- functions acting on all clock cycles from whatever rate
|
1600 |
|
|
-- in halfrate clock domain issues 1 command per clock
|
1601 |
|
|
-- in quarter rate issues 1 command per clock
|
1602 |
|
|
-- In the above cases they will be correctly aligned using the
|
1603 |
|
|
-- ALTMEMPHY 2T and 4T SDC
|
1604 |
|
|
-- -------------------------------------------------------------
|
1605 |
|
|
|
1606 |
|
|
-- -------------------------------------------------------------
|
1607 |
|
|
-- defaults the bus no JEDEC abbreviated name
|
1608 |
|
|
-- -------------------------------------------------------------
|
1609 |
|
|
function defaults (config_rec : in t_addr_cmd_config_rec
|
1610 |
|
|
) return t_addr_cmd_vector
|
1611 |
|
|
is
|
1612 |
|
|
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
|
1613 |
|
|
begin
|
1614 |
|
|
|
1615 |
|
|
v_retval := (others => defaults(config_rec));
|
1616 |
|
|
|
1617 |
|
|
return v_retval;
|
1618 |
|
|
|
1619 |
|
|
end function;
|
1620 |
|
|
|
1621 |
|
|
-- -------------------------------------------------------------
|
1622 |
|
|
-- resets the addr/cmd signal (same as default with cke 0)
|
1623 |
|
|
-- -------------------------------------------------------------
|
1624 |
|
|
function reset (config_rec : in t_addr_cmd_config_rec
|
1625 |
|
|
) return t_addr_cmd_vector
|
1626 |
|
|
is
|
1627 |
|
|
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
|
1628 |
|
|
begin
|
1629 |
|
|
|
1630 |
|
|
v_retval := (others => reset(config_rec));
|
1631 |
|
|
|
1632 |
|
|
return v_retval;
|
1633 |
|
|
|
1634 |
|
|
end function;
|
1635 |
|
|
|
1636 |
|
|
function int_pup_reset (config_rec : in t_addr_cmd_config_rec
|
1637 |
|
|
) return t_addr_cmd_vector
|
1638 |
|
|
is
|
1639 |
|
|
variable v_addr_cmd_config_rst : t_addr_cmd_config_rec;
|
1640 |
|
|
begin
|
1641 |
|
|
|
1642 |
|
|
v_addr_cmd_config_rst := config_rec;
|
1643 |
|
|
v_addr_cmd_config_rst.num_ranks := c_max_ranks;
|
1644 |
|
|
|
1645 |
|
|
return reset(v_addr_cmd_config_rst);
|
1646 |
|
|
|
1647 |
|
|
end function;
|
1648 |
|
|
|
1649 |
|
|
-- -------------------------------------------------------------
|
1650 |
|
|
-- issues a deselect command JEDEC abbreviated name: DES
|
1651 |
|
|
-- -------------------------------------------------------------
|
1652 |
|
|
function deselect ( config_rec : in t_addr_cmd_config_rec;
|
1653 |
|
|
previous : in t_addr_cmd_vector
|
1654 |
|
|
) return t_addr_cmd_vector
|
1655 |
|
|
is
|
1656 |
|
|
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
|
1657 |
|
|
variable v_retval : t_addr_cmd_vector(a_previous'range);
|
1658 |
|
|
begin
|
1659 |
|
|
|
1660 |
|
|
for rate in a_previous'range loop
|
1661 |
|
|
v_retval(rate) := deselect(config_rec, a_previous(a_previous'high));
|
1662 |
|
|
end loop;
|
1663 |
|
|
|
1664 |
|
|
return v_retval;
|
1665 |
|
|
|
1666 |
|
|
end function;
|
1667 |
|
|
|
1668 |
|
|
-- -------------------------------------------------------------
|
1669 |
|
|
-- issues a precharge all command JEDEC abbreviated name: PREA
|
1670 |
|
|
-- -------------------------------------------------------------
|
1671 |
|
|
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
|
1672 |
|
|
previous : in t_addr_cmd_vector;
|
1673 |
|
|
ranks : in natural range 0 to 2**c_max_ranks -1
|
1674 |
|
|
) return t_addr_cmd_vector
|
1675 |
|
|
is
|
1676 |
|
|
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
|
1677 |
|
|
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
|
1678 |
|
|
begin
|
1679 |
|
|
|
1680 |
|
|
for rate in a_previous'range loop
|
1681 |
|
|
|
1682 |
|
|
v_retval(rate) := precharge_all(config_rec, previous(a_previous'high), ranks);
|
1683 |
|
|
|
1684 |
|
|
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
|
1685 |
|
|
if rate /= config_rec.cmds_per_clk/2 then
|
1686 |
|
|
v_retval(rate).cs_n := (2 ** config_rec.num_ranks) -1;
|
1687 |
|
|
end if;
|
1688 |
|
|
|
1689 |
|
|
end loop;
|
1690 |
|
|
|
1691 |
|
|
return v_retval;
|
1692 |
|
|
|
1693 |
|
|
end function;
|
1694 |
|
|
|
1695 |
|
|
-- -------------------------------------------------------------
|
1696 |
|
|
-- precharge (close) a bank JEDEC abbreviated name: PRE
|
1697 |
|
|
-- -------------------------------------------------------------
|
1698 |
|
|
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
|
1699 |
|
|
previous : in t_addr_cmd_vector;
|
1700 |
|
|
ranks : in natural range 0 to 2**c_max_ranks -1;
|
1701 |
|
|
bank : in natural range 0 to 2**c_max_ba_bits -1
|
1702 |
|
|
) return t_addr_cmd_vector
|
1703 |
|
|
is
|
1704 |
|
|
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
|
1705 |
|
|
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
|
1706 |
|
|
begin
|
1707 |
|
|
|
1708 |
|
|
for rate in a_previous'range loop
|
1709 |
|
|
|
1710 |
|
|
v_retval(rate) := precharge_bank(config_rec, previous(a_previous'high), ranks, bank);
|
1711 |
|
|
|
1712 |
|
|
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
|
1713 |
|
|
if rate /= config_rec.cmds_per_clk/2 then
|
1714 |
|
|
v_retval(rate).cs_n := (2 ** config_rec.num_ranks) -1;
|
1715 |
|
|
end if;
|
1716 |
|
|
|
1717 |
|
|
end loop;
|
1718 |
|
|
|
1719 |
|
|
return v_retval;
|
1720 |
|
|
|
1721 |
|
|
end function;
|
1722 |
|
|
|
1723 |
|
|
-- -------------------------------------------------------------
|
1724 |
|
|
-- issues a activate (open row) JEDEC abbreviated name: ACT
|
1725 |
|
|
-- -------------------------------------------------------------
|
1726 |
|
|
function activate ( config_rec : in t_addr_cmd_config_rec;
|
1727 |
|
|
previous : in t_addr_cmd_vector;
|
1728 |
|
|
bank : in natural range 0 to 2**c_max_ba_bits -1;
|
1729 |
|
|
row : in natural range 0 to 2**c_max_addr_bits -1;
|
1730 |
|
|
ranks : in natural range 0 to 2**c_max_ranks - 1
|
1731 |
|
|
) return t_addr_cmd_vector
|
1732 |
|
|
is
|
1733 |
|
|
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
|
1734 |
|
|
begin
|
1735 |
|
|
|
1736 |
|
|
for rate in previous'range loop
|
1737 |
|
|
v_retval(rate) := activate(config_rec, previous(previous'high), bank, row, ranks);
|
1738 |
|
|
|
1739 |
|
|
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
|
1740 |
|
|
if rate /= config_rec.cmds_per_clk/2 then
|
1741 |
|
|
v_retval(rate).cs_n := (2 ** config_rec.num_ranks) -1;
|
1742 |
|
|
end if;
|
1743 |
|
|
|
1744 |
|
|
end loop;
|
1745 |
|
|
|
1746 |
|
|
return v_retval;
|
1747 |
|
|
|
1748 |
|
|
end function;
|
1749 |
|
|
|
1750 |
|
|
-- -------------------------------------------------------------
|
1751 |
|
|
-- issues a write command JEDEC abbreviated name:WR, WRA
|
1752 |
|
|
-- WRS4, WRAS4
|
1753 |
|
|
-- WRS8, WRAS8
|
1754 |
|
|
--
|
1755 |
|
|
-- has the ability to support:
|
1756 |
|
|
-- DDR3:
|
1757 |
|
|
-- BL4, BL8, fixed BL
|
1758 |
|
|
-- Auto Precharge (AP)
|
1759 |
|
|
-- DDR2, DDR:
|
1760 |
|
|
-- fixed BL
|
1761 |
|
|
-- Auto Precharge (AP)
|
1762 |
|
|
-- -------------------------------------------------------------
|
1763 |
|
|
function write ( config_rec : in t_addr_cmd_config_rec;
|
1764 |
|
|
previous : in t_addr_cmd_vector;
|
1765 |
|
|
bank : in natural range 0 to 2**c_max_ba_bits -1;
|
1766 |
|
|
col : in natural range 0 to 2**c_max_addr_bits -1;
|
1767 |
|
|
ranks : in natural range 0 to 2**c_max_ranks - 1;
|
1768 |
|
|
op_length : in natural range 1 to 8;
|
1769 |
|
|
auto_prech : in boolean
|
1770 |
|
|
) return t_addr_cmd_vector
|
1771 |
|
|
is
|
1772 |
|
|
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
|
1773 |
|
|
begin
|
1774 |
|
|
|
1775 |
|
|
for rate in previous'range loop
|
1776 |
|
|
v_retval(rate) := write(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
|
1777 |
|
|
|
1778 |
|
|
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
|
1779 |
|
|
if rate /= config_rec.cmds_per_clk/2 then
|
1780 |
|
|
v_retval(rate).cs_n := (2 ** config_rec.num_ranks) -1;
|
1781 |
|
|
end if;
|
1782 |
|
|
|
1783 |
|
|
end loop;
|
1784 |
|
|
|
1785 |
|
|
return v_retval;
|
1786 |
|
|
|
1787 |
|
|
end function;
|
1788 |
|
|
|
1789 |
|
|
-- -------------------------------------------------------------
|
1790 |
|
|
-- issues a read command JEDEC abbreviated name: RD, RDA
|
1791 |
|
|
-- RDS4, RDAS4
|
1792 |
|
|
-- RDS8, RDAS8
|
1793 |
|
|
-- has the ability to support:
|
1794 |
|
|
-- DDR3:
|
1795 |
|
|
-- BL4, BL8, fixed BL
|
1796 |
|
|
-- Auto Precharge (AP)
|
1797 |
|
|
-- DDR2, DDR:
|
1798 |
|
|
-- fixed BL, Auto Precharge (AP)
|
1799 |
|
|
-- -------------------------------------------------------------
|
1800 |
|
|
function read ( config_rec : in t_addr_cmd_config_rec;
|
1801 |
|
|
previous : in t_addr_cmd_vector;
|
1802 |
|
|
bank : in natural range 0 to 2**c_max_ba_bits -1;
|
1803 |
|
|
col : in natural range 0 to 2**c_max_addr_bits -1;
|
1804 |
|
|
ranks : in natural range 0 to 2**c_max_ranks - 1;
|
1805 |
|
|
op_length : in natural range 1 to 8;
|
1806 |
|
|
auto_prech : in boolean
|
1807 |
|
|
) return t_addr_cmd_vector
|
1808 |
|
|
is
|
1809 |
|
|
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
|
1810 |
|
|
begin
|
1811 |
|
|
|
1812 |
|
|
for rate in previous'range loop
|
1813 |
|
|
v_retval(rate) := read(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
|
1814 |
|
|
|
1815 |
|
|
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
|
1816 |
|
|
if rate /= config_rec.cmds_per_clk/2 then
|
1817 |
|
|
v_retval(rate).cs_n := (2 ** config_rec.num_ranks) -1;
|
1818 |
|
|
end if;
|
1819 |
|
|
|
1820 |
|
|
end loop;
|
1821 |
|
|
|
1822 |
|
|
return v_retval;
|
1823 |
|
|
|
1824 |
|
|
end function;
|
1825 |
|
|
|
1826 |
|
|
-- -------------------------------------------------------------
|
1827 |
|
|
-- issues a refresh command JEDEC abbreviated name: REF
|
1828 |
|
|
-- -------------------------------------------------------------
|
1829 |
|
|
function refresh (config_rec : in t_addr_cmd_config_rec;
|
1830 |
|
|
previous : in t_addr_cmd_vector;
|
1831 |
|
|
ranks : in natural range 0 to 2**c_max_ranks -1
|
1832 |
|
|
)return t_addr_cmd_vector
|
1833 |
|
|
is
|
1834 |
|
|
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
|
1835 |
|
|
begin
|
1836 |
|
|
|
1837 |
|
|
for rate in previous'range loop
|
1838 |
|
|
v_retval(rate) := refresh(config_rec, previous(previous'high), ranks);
|
1839 |
|
|
|
1840 |
|
|
if rate /= config_rec.cmds_per_clk/2 then
|
1841 |
|
|
v_retval(rate).cs_n := (2 ** config_rec.num_ranks) -1;
|
1842 |
|
|
end if;
|
1843 |
|
|
|
1844 |
|
|
end loop;
|
1845 |
|
|
|
1846 |
|
|
return v_retval;
|
1847 |
|
|
|
1848 |
|
|
end function;
|
1849 |
|
|
|
1850 |
|
|
|
1851 |
|
|
-- -------------------------------------------------------------
|
1852 |
|
|
-- issues a self_refresh_entry command JEDEC abbreviated name: SRE
|
1853 |
|
|
-- -------------------------------------------------------------
|
1854 |
|
|
function self_refresh_entry (config_rec : in t_addr_cmd_config_rec;
|
1855 |
|
|
previous : in t_addr_cmd_vector;
|
1856 |
|
|
ranks : in natural range 0 to 2**c_max_ranks -1
|
1857 |
|
|
)return t_addr_cmd_vector
|
1858 |
|
|
is
|
1859 |
|
|
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
|
1860 |
|
|
begin
|
1861 |
|
|
v_retval := enter_sr_pd_mode(config_rec, refresh(config_rec, previous, ranks), ranks);
|
1862 |
|
|
return v_retval;
|
1863 |
|
|
end function;
|
1864 |
|
|
|
1865 |
|
|
|
1866 |
|
|
|
1867 |
|
|
-- -------------------------------------------------------------
|
1868 |
|
|
-- issues a self_refresh exit or power_down exit command
|
1869 |
|
|
-- JEDEC abbreviated names: SRX, PDX
|
1870 |
|
|
-- -------------------------------------------------------------
|
1871 |
|
|
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
|
1872 |
|
|
previous : in t_addr_cmd_vector;
|
1873 |
|
|
ranks : in natural range 0 to 2**c_max_ranks -1
|
1874 |
|
|
) return t_addr_cmd_vector
|
1875 |
|
|
is
|
1876 |
|
|
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
|
1877 |
|
|
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
|
1878 |
|
|
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
|
1879 |
|
|
begin
|
1880 |
|
|
|
1881 |
|
|
v_retval := maintain_pd_or_sr(config_rec, previous, ranks);
|
1882 |
|
|
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
|
1883 |
|
|
|
1884 |
|
|
for rate in 0 to config_rec.cmds_per_clk - 1 loop
|
1885 |
|
|
|
1886 |
|
|
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
|
1887 |
|
|
|
1888 |
|
|
for i in v_mask_workings_b'range loop
|
1889 |
|
|
v_mask_workings(i) := v_mask_workings(i) or v_mask_workings_b(i);
|
1890 |
|
|
end loop;
|
1891 |
|
|
|
1892 |
|
|
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
|
1893 |
|
|
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
|
1894 |
|
|
end if;
|
1895 |
|
|
end loop;
|
1896 |
|
|
|
1897 |
|
|
return v_retval;
|
1898 |
|
|
|
1899 |
|
|
end function;
|
1900 |
|
|
|
1901 |
|
|
|
1902 |
|
|
-- -------------------------------------------------------------
|
1903 |
|
|
-- cause the selected ranks to enter Self-refresh or Powerdown mode
|
1904 |
|
|
-- JEDEC abbreviated names: PDE,
|
1905 |
|
|
-- SRE (if a refresh is concurrently issued to the same ranks)
|
1906 |
|
|
-- -------------------------------------------------------------
|
1907 |
|
|
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
|
1908 |
|
|
previous : in t_addr_cmd_vector;
|
1909 |
|
|
ranks : in natural range 0 to 2**c_max_ranks -1
|
1910 |
|
|
) return t_addr_cmd_vector
|
1911 |
|
|
is
|
1912 |
|
|
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
|
1913 |
|
|
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
|
1914 |
|
|
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
|
1915 |
|
|
begin
|
1916 |
|
|
|
1917 |
|
|
v_retval := previous;
|
1918 |
|
|
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
|
1919 |
|
|
|
1920 |
|
|
for rate in 0 to config_rec.cmds_per_clk - 1 loop
|
1921 |
|
|
|
1922 |
|
|
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
|
1923 |
|
|
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
|
1924 |
|
|
|
1925 |
|
|
for i in v_mask_workings_b'range loop
|
1926 |
|
|
v_mask_workings(i) := v_mask_workings(i) and not v_mask_workings_b(i);
|
1927 |
|
|
end loop;
|
1928 |
|
|
|
1929 |
|
|
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
|
1930 |
|
|
|
1931 |
|
|
end if;
|
1932 |
|
|
|
1933 |
|
|
end loop;
|
1934 |
|
|
|
1935 |
|
|
return v_retval;
|
1936 |
|
|
|
1937 |
|
|
end function;
|
1938 |
|
|
|
1939 |
|
|
|
1940 |
|
|
-- -------------------------------------------------------------
|
1941 |
|
|
-- Issues a mode register set command JEDEC abbreviated name: MRS
|
1942 |
|
|
-- -------------------------------------------------------------
|
1943 |
|
|
function load_mode ( config_rec : in t_addr_cmd_config_rec;
|
1944 |
|
|
mode_register_num : in natural range 0 to 3;
|
1945 |
|
|
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
|
1946 |
|
|
ranks : in natural range 0 to 2**c_max_ranks -1;
|
1947 |
|
|
remap_addr_and_ba : in boolean
|
1948 |
|
|
) return t_addr_cmd_vector
|
1949 |
|
|
is
|
1950 |
|
|
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
|
1951 |
|
|
begin
|
1952 |
|
|
|
1953 |
|
|
v_retval := (others => load_mode(config_rec, mode_register_num, mode_reg_value, ranks, remap_addr_and_ba));
|
1954 |
|
|
|
1955 |
|
|
for rate in v_retval'range loop
|
1956 |
|
|
if rate /= config_rec.cmds_per_clk/2 then
|
1957 |
|
|
v_retval(rate).cs_n := (2 ** config_rec.num_ranks) -1;
|
1958 |
|
|
end if;
|
1959 |
|
|
end loop;
|
1960 |
|
|
|
1961 |
|
|
return v_retval;
|
1962 |
|
|
|
1963 |
|
|
end function;
|
1964 |
|
|
|
1965 |
|
|
|
1966 |
|
|
-- -------------------------------------------------------------
|
1967 |
|
|
-- maintains SR or PD mode on slected ranks.
|
1968 |
|
|
-- NOTE: does not affect previous command
|
1969 |
|
|
-- -------------------------------------------------------------
|
1970 |
|
|
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
|
1971 |
|
|
previous : in t_addr_cmd_vector;
|
1972 |
|
|
ranks : in natural range 0 to 2**c_max_ranks -1
|
1973 |
|
|
) return t_addr_cmd_vector
|
1974 |
|
|
is
|
1975 |
|
|
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
|
1976 |
|
|
begin
|
1977 |
|
|
|
1978 |
|
|
for command in v_retval'range loop
|
1979 |
|
|
v_retval(command) := maintain_pd_or_sr(config_rec, previous(command), ranks);
|
1980 |
|
|
end loop;
|
1981 |
|
|
return v_retval;
|
1982 |
|
|
end function;
|
1983 |
|
|
|
1984 |
|
|
|
1985 |
|
|
-- -------------------------------------------------------------
|
1986 |
|
|
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
|
1987 |
|
|
-- NOTE - can only be issued to a single RANK ata a time.
|
1988 |
|
|
-- -------------------------------------------------------------
|
1989 |
|
|
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
|
1990 |
|
|
rank : in natural range 0 to 2**c_max_ranks -1
|
1991 |
|
|
) return t_addr_cmd_vector
|
1992 |
|
|
is
|
1993 |
|
|
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
|
1994 |
|
|
begin
|
1995 |
|
|
|
1996 |
|
|
for command in v_retval'range loop
|
1997 |
|
|
v_retval(command) := ZQCL(config_rec, rank);
|
1998 |
|
|
if command * 2 /= config_rec.cmds_per_clk then
|
1999 |
|
|
v_retval(command).cs_n := (2 ** config_rec.num_ranks) -1;
|
2000 |
|
|
end if;
|
2001 |
|
|
end loop;
|
2002 |
|
|
|
2003 |
|
|
return v_retval;
|
2004 |
|
|
|
2005 |
|
|
end function;
|
2006 |
|
|
|
2007 |
|
|
-- -------------------------------------------------------------
|
2008 |
|
|
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
|
2009 |
|
|
-- NOTE - can only be issued to a single RANK ata a time.
|
2010 |
|
|
-- -------------------------------------------------------------
|
2011 |
|
|
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
|
2012 |
|
|
rank : in natural range 0 to 2**c_max_ranks -1
|
2013 |
|
|
) return t_addr_cmd_vector
|
2014 |
|
|
is
|
2015 |
|
|
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
|
2016 |
|
|
begin
|
2017 |
|
|
|
2018 |
|
|
for command in v_retval'range loop
|
2019 |
|
|
v_retval(command) := ZQCS(config_rec, rank);
|
2020 |
|
|
if command * 2 /= config_rec.cmds_per_clk then
|
2021 |
|
|
v_retval(command).cs_n := (2 ** config_rec.num_ranks) -1;
|
2022 |
|
|
end if;
|
2023 |
|
|
end loop;
|
2024 |
|
|
|
2025 |
|
|
return v_retval;
|
2026 |
|
|
|
2027 |
|
|
end function;
|
2028 |
|
|
|
2029 |
|
|
|
2030 |
|
|
-- ----------------------
|
2031 |
|
|
-- Additional Rank manipulation functions (main use DDR3)
|
2032 |
|
|
-- -------------
|
2033 |
|
|
|
2034 |
|
|
-- -----------------------------------
|
2035 |
|
|
-- set the chip select for a group of ranks
|
2036 |
|
|
-- -----------------------------------
|
2037 |
|
|
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
|
2038 |
|
|
record_to_mask : in t_addr_cmd;
|
2039 |
|
|
mem_ac_swapped_ranks : in std_logic_vector
|
2040 |
|
|
) return t_addr_cmd
|
2041 |
|
|
is
|
2042 |
|
|
variable v_retval : t_addr_cmd;
|
2043 |
|
|
variable v_mask_workings : std_logic_vector(mem_ac_swapped_ranks'range);
|
2044 |
|
|
begin
|
2045 |
|
|
v_retval := record_to_mask;
|
2046 |
|
|
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, mem_ac_swapped_ranks'length));
|
2047 |
|
|
|
2048 |
|
|
for i in v_mask_workings'range loop
|
2049 |
|
|
v_mask_workings(i):= v_mask_workings(i) or not mem_ac_swapped_ranks(i);
|
2050 |
|
|
end loop;
|
2051 |
|
|
|
2052 |
|
|
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
|
2053 |
|
|
return v_retval;
|
2054 |
|
|
end function;
|
2055 |
|
|
|
2056 |
|
|
-- -----------------------------------
|
2057 |
|
|
-- inverse of the above
|
2058 |
|
|
-- -----------------------------------
|
2059 |
|
|
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
|
2060 |
|
|
record_to_mask : in t_addr_cmd;
|
2061 |
|
|
mem_ac_swapped_ranks : in std_logic_vector
|
2062 |
|
|
) return t_addr_cmd
|
2063 |
|
|
is
|
2064 |
|
|
variable v_retval : t_addr_cmd;
|
2065 |
|
|
variable v_mask_workings : std_logic_vector(mem_ac_swapped_ranks'range);
|
2066 |
|
|
begin
|
2067 |
|
|
v_retval := record_to_mask;
|
2068 |
|
|
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, mem_ac_swapped_ranks'length));
|
2069 |
|
|
|
2070 |
|
|
for i in v_mask_workings'range loop
|
2071 |
|
|
v_mask_workings(i):= v_mask_workings(i) or mem_ac_swapped_ranks(i);
|
2072 |
|
|
end loop;
|
2073 |
|
|
|
2074 |
|
|
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
|
2075 |
|
|
return v_retval;
|
2076 |
|
|
end function;
|
2077 |
|
|
|
2078 |
|
|
-- -----------------------------------
|
2079 |
|
|
-- set the chip select for a group of ranks in a way which handles diffrent rates
|
2080 |
|
|
-- -----------------------------------
|
2081 |
|
|
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
|
2082 |
|
|
record_to_mask : in t_addr_cmd_vector;
|
2083 |
|
|
mem_ac_swapped_ranks : in std_logic_vector
|
2084 |
|
|
) return t_addr_cmd_vector
|
2085 |
|
|
is
|
2086 |
|
|
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
|
2087 |
|
|
begin
|
2088 |
|
|
|
2089 |
|
|
for command in record_to_mask'range loop
|
2090 |
|
|
v_retval(command) := all_unreversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
|
2091 |
|
|
end loop;
|
2092 |
|
|
|
2093 |
|
|
return v_retval;
|
2094 |
|
|
|
2095 |
|
|
end function;
|
2096 |
|
|
|
2097 |
|
|
-- -----------------------------------
|
2098 |
|
|
-- inverse of the above handling ranks
|
2099 |
|
|
-- -----------------------------------
|
2100 |
|
|
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
|
2101 |
|
|
record_to_mask : in t_addr_cmd_vector;
|
2102 |
|
|
mem_ac_swapped_ranks : in std_logic_vector
|
2103 |
|
|
) return t_addr_cmd_vector
|
2104 |
|
|
is
|
2105 |
|
|
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
|
2106 |
|
|
begin
|
2107 |
|
|
|
2108 |
|
|
for command in record_to_mask'range loop
|
2109 |
|
|
v_retval(command) := all_reversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
|
2110 |
|
|
end loop;
|
2111 |
|
|
|
2112 |
|
|
return v_retval;
|
2113 |
|
|
|
2114 |
|
|
end function;
|
2115 |
|
|
|
2116 |
|
|
-- --------------------------------------------------
|
2117 |
|
|
-- overloaded functions, to simplify use, or provide simplified functionality
|
2118 |
|
|
-- --------------------------------------------------
|
2119 |
|
|
|
2120 |
|
|
-- ----------------------------------------------------
|
2121 |
|
|
-- Precharge all, defaulting all bits.
|
2122 |
|
|
-- ----------------------------------------------------
|
2123 |
|
|
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
|
2124 |
|
|
ranks : in natural range 0 to 2**c_max_ranks -1
|
2125 |
|
|
) return t_addr_cmd_vector
|
2126 |
|
|
is
|
2127 |
|
|
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
|
2128 |
|
|
begin
|
2129 |
|
|
|
2130 |
|
|
v_retval := precharge_all(config_rec, v_retval, ranks);
|
2131 |
|
|
|
2132 |
|
|
return v_retval;
|
2133 |
|
|
|
2134 |
|
|
end function;
|
2135 |
|
|
|
2136 |
|
|
|
2137 |
|
|
-- ----------------------------------------------------
|
2138 |
|
|
-- perform DLL reset through mode registers
|
2139 |
|
|
-- ----------------------------------------------------
|
2140 |
|
|
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
|
2141 |
|
|
mode_reg_val : in std_logic_vector;
|
2142 |
|
|
rank_num : in natural range 0 to 2**c_max_ranks - 1;
|
2143 |
|
|
reorder_addr_bits : in boolean
|
2144 |
|
|
) return t_addr_cmd_vector is
|
2145 |
|
|
variable int_mode_reg : std_logic_vector(mode_reg_val'range);
|
2146 |
|
|
variable output : t_addr_cmd_vector(0 to config_rec.cmds_per_clk - 1);
|
2147 |
|
|
begin
|
2148 |
|
|
int_mode_reg := mode_reg_val;
|
2149 |
|
|
int_mode_reg(8) := '1'; -- set DLL reset bit.
|
2150 |
|
|
output := load_mode(config_rec, 0, int_mode_reg, rank_num, reorder_addr_bits);
|
2151 |
|
|
return output;
|
2152 |
|
|
end function;
|
2153 |
|
|
|
2154 |
|
|
|
2155 |
|
|
-- -------------------------------------------------------------
|
2156 |
|
|
-- package configuration functions
|
2157 |
|
|
-- -------------------------------------------------------------
|
2158 |
|
|
|
2159 |
|
|
-- -------------------------------------------------------------
|
2160 |
|
|
-- the following function sets up the odt settings
|
2161 |
|
|
-- NOTES: supports DDR/DDR2/DDR3 SDRAM memories
|
2162 |
|
|
-- -------------------------------------------------------------
|
2163 |
|
|
function set_odt_values (ranks : natural;
|
2164 |
|
|
ranks_per_slot : natural;
|
2165 |
|
|
mem_type : in string
|
2166 |
|
|
) return t_odt_array is
|
2167 |
|
|
|
2168 |
|
|
variable v_num_slots : natural;
|
2169 |
|
|
variable v_cs : natural range 0 to ranks-1;
|
2170 |
|
|
variable v_odt_values : t_odt_array(0 to ranks-1);
|
2171 |
|
|
variable v_cs_addr : unsigned(ranks-1 downto 0);
|
2172 |
|
|
|
2173 |
|
|
begin
|
2174 |
|
|
|
2175 |
|
|
if mem_type = "DDR" then
|
2176 |
|
|
|
2177 |
|
|
-- ODT not supported for DDR memory so set default off
|
2178 |
|
|
for v_cs in 0 to ranks-1 loop
|
2179 |
|
|
v_odt_values(v_cs).write := 0;
|
2180 |
|
|
v_odt_values(v_cs).read := 0;
|
2181 |
|
|
end loop;
|
2182 |
|
|
|
2183 |
|
|
elsif mem_type = "DDR2" then
|
2184 |
|
|
|
2185 |
|
|
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
|
2186 |
|
|
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
|
2187 |
|
|
v_num_slots := ranks/ranks_per_slot;
|
2188 |
|
|
|
2189 |
|
|
if v_num_slots = 1 then
|
2190 |
|
|
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
|
2191 |
|
|
-- set odt on one chip for writes and no odt for reads
|
2192 |
|
|
for v_cs in 0 to ranks-1 loop
|
2193 |
|
|
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
|
2194 |
|
|
v_odt_values(v_cs).read := 0;
|
2195 |
|
|
end loop;
|
2196 |
|
|
else
|
2197 |
|
|
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
|
2198 |
|
|
-- as an example consider the below for 4 slots with 2 ranks per slot
|
2199 |
|
|
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
|
2200 |
|
|
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
|
2201 |
|
|
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
|
2202 |
|
|
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
|
2203 |
|
|
|
2204 |
|
|
-- the logic below implements the above for varying ranks and ranks_per slot
|
2205 |
|
|
-- under the condition that ranks/ranks_per_slot is integer
|
2206 |
|
|
for v_cs in 0 to ranks-1 loop
|
2207 |
|
|
v_cs_addr := to_unsigned(v_cs, ranks);
|
2208 |
|
|
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
|
2209 |
|
|
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr);
|
2210 |
|
|
v_odt_values(v_cs).read := v_odt_values(v_cs).write;
|
2211 |
|
|
end loop;
|
2212 |
|
|
|
2213 |
|
|
end if;
|
2214 |
|
|
|
2215 |
|
|
elsif mem_type = "DDR3" then
|
2216 |
|
|
|
2217 |
|
|
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
|
2218 |
|
|
v_num_slots := ranks/ranks_per_slot;
|
2219 |
|
|
|
2220 |
|
|
if v_num_slots = 1 then
|
2221 |
|
|
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
|
2222 |
|
|
-- set odt on one chip for writes and no odt for reads
|
2223 |
|
|
for v_cs in 0 to ranks-1 loop
|
2224 |
|
|
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
|
2225 |
|
|
v_odt_values(v_cs).read := 0;
|
2226 |
|
|
end loop;
|
2227 |
|
|
else
|
2228 |
|
|
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
|
2229 |
|
|
-- as an example consider the below for 4 slots with 2 ranks per slot
|
2230 |
|
|
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
|
2231 |
|
|
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
|
2232 |
|
|
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
|
2233 |
|
|
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
|
2234 |
|
|
|
2235 |
|
|
-- the logic below implements the above for varying ranks and ranks_per slot
|
2236 |
|
|
-- under the condition that ranks/ranks_per_slot is integer
|
2237 |
|
|
for v_cs in 0 to ranks-1 loop
|
2238 |
|
|
v_cs_addr := to_unsigned(v_cs, ranks);
|
2239 |
|
|
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
|
2240 |
|
|
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr) + 2**(v_cs); -- turn on a neighbouring slots cs and current rank being written to
|
2241 |
|
|
v_odt_values(v_cs).read := 2**to_integer(v_cs_addr);
|
2242 |
|
|
end loop;
|
2243 |
|
|
|
2244 |
|
|
end if;
|
2245 |
|
|
|
2246 |
|
|
else
|
2247 |
|
|
report ac_report_prefix & "unknown mem_type specified in the set_odt_values function in addr_cmd_pkg package" severity failure;
|
2248 |
|
|
end if;
|
2249 |
|
|
|
2250 |
|
|
return v_odt_values;
|
2251 |
|
|
|
2252 |
|
|
end function;
|
2253 |
|
|
|
2254 |
|
|
|
2255 |
|
|
|
2256 |
|
|
-- -----------------------------------------------------------
|
2257 |
|
|
-- set constant values to config_rec
|
2258 |
|
|
-- ----------------------------------------------------------
|
2259 |
|
|
function set_config_rec ( num_addr_bits : in natural;
|
2260 |
|
|
num_ba_bits : in natural;
|
2261 |
|
|
num_ranks : in natural;
|
2262 |
|
|
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
|
2263 |
|
|
mem_type : in string
|
2264 |
|
|
) return t_addr_cmd_config_rec
|
2265 |
|
|
is
|
2266 |
|
|
variable v_config_rec : t_addr_cmd_config_rec;
|
2267 |
|
|
begin
|
2268 |
|
|
|
2269 |
|
|
v_config_rec.num_addr_bits := num_addr_bits;
|
2270 |
|
|
v_config_rec.num_ba_bits := num_ba_bits;
|
2271 |
|
|
v_config_rec.num_ranks := num_ranks;
|
2272 |
|
|
v_config_rec.cmds_per_clk := dwidth_ratio/2;
|
2273 |
|
|
|
2274 |
|
|
if mem_type = "DDR" then
|
2275 |
|
|
v_config_rec.mem_type := DDR;
|
2276 |
|
|
elsif mem_type = "DDR2" then
|
2277 |
|
|
v_config_rec.mem_type := DDR2;
|
2278 |
|
|
elsif mem_type = "DDR3" then
|
2279 |
|
|
v_config_rec.mem_type := DDR3;
|
2280 |
|
|
else
|
2281 |
|
|
report ac_report_prefix & "unknown mem_type specified in the set_config_rec function in addr_cmd_pkg package" severity failure;
|
2282 |
|
|
end if;
|
2283 |
|
|
|
2284 |
|
|
return v_config_rec;
|
2285 |
|
|
|
2286 |
|
|
end function;
|
2287 |
|
|
|
2288 |
|
|
|
2289 |
|
|
-- -----------------------------------------------------------
|
2290 |
|
|
-- unpack and pack address and command signals from and to t_addr_cmd_vector
|
2291 |
|
|
-- -----------------------------------------------------------
|
2292 |
|
|
|
2293 |
|
|
-- -------------------------------------------------------------
|
2294 |
|
|
-- convert from t_addr_cmd_vector to expanded addr/cmd signals
|
2295 |
|
|
-- -------------------------------------------------------------
|
2296 |
|
|
|
2297 |
|
|
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
|
2298 |
|
|
config_rec : in t_addr_cmd_config_rec;
|
2299 |
|
|
addr : out std_logic_vector;
|
2300 |
|
|
ba : out std_logic_vector;
|
2301 |
|
|
cas_n : out std_logic_vector;
|
2302 |
|
|
ras_n : out std_logic_vector;
|
2303 |
|
|
we_n : out std_logic_vector;
|
2304 |
|
|
cke : out std_logic_vector;
|
2305 |
|
|
cs_n : out std_logic_vector;
|
2306 |
|
|
odt : out std_logic_vector;
|
2307 |
|
|
rst_n : out std_logic_vector
|
2308 |
|
|
)
|
2309 |
|
|
is
|
2310 |
|
|
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
|
2311 |
|
|
variable v_vec_len : natural range 1 to 4;
|
2312 |
|
|
|
2313 |
|
|
variable v_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
|
2314 |
|
|
variable v_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
|
2315 |
|
|
variable v_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
|
2316 |
|
|
variable v_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
|
2317 |
|
|
variable v_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
|
2318 |
|
|
variable v_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
|
2319 |
|
|
variable v_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
|
2320 |
|
|
variable v_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
|
2321 |
|
|
variable v_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
|
2322 |
|
|
|
2323 |
|
|
begin
|
2324 |
|
|
|
2325 |
|
|
v_vec_len := config_rec.cmds_per_clk;
|
2326 |
|
|
v_mem_if_ranks := config_rec.num_ranks;
|
2327 |
|
|
|
2328 |
|
|
for v_i in 0 to v_vec_len-1 loop
|
2329 |
|
|
|
2330 |
|
|
assert addr_cmd_vector(v_i).addr < 2**config_rec.num_addr_bits report ac_report_prefix &
|
2331 |
|
|
"value of addr exceeds range of number of address bits in unpack_addr_cmd_vector procedure" severity failure;
|
2332 |
|
|
assert addr_cmd_vector(v_i).ba < 2**config_rec.num_ba_bits report ac_report_prefix &
|
2333 |
|
|
"value of ba exceeds range of number of bank address bits in unpack_addr_cmd_vector procedure" severity failure;
|
2334 |
|
|
assert addr_cmd_vector(v_i).odt < 2**v_mem_if_ranks report ac_report_prefix &
|
2335 |
|
|
"value of odt exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
|
2336 |
|
|
assert addr_cmd_vector(v_i).cs_n < 2**v_mem_if_ranks report ac_report_prefix &
|
2337 |
|
|
"value of cs_n exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
|
2338 |
|
|
assert addr_cmd_vector(v_i).cke < 2**v_mem_if_ranks report ac_report_prefix &
|
2339 |
|
|
"value of cke exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
|
2340 |
|
|
|
2341 |
|
|
v_addr((v_i+1)*config_rec.num_addr_bits - 1 downto v_i*config_rec.num_addr_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).addr,config_rec.num_addr_bits));
|
2342 |
|
|
v_ba((v_i+1)*config_rec.num_ba_bits - 1 downto v_i*config_rec.num_ba_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).ba,config_rec.num_ba_bits));
|
2343 |
|
|
v_cke((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cke,v_mem_if_ranks));
|
2344 |
|
|
v_cs_n((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cs_n,v_mem_if_ranks));
|
2345 |
|
|
v_odt((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).odt,v_mem_if_ranks));
|
2346 |
|
|
|
2347 |
|
|
if (addr_cmd_vector(v_i).cas_n) then v_cas_n(v_i) := '0'; else v_cas_n(v_i) := '1'; end if;
|
2348 |
|
|
if (addr_cmd_vector(v_i).ras_n) then v_ras_n(v_i) := '0'; else v_ras_n(v_i) := '1'; end if;
|
2349 |
|
|
if (addr_cmd_vector(v_i).we_n) then v_we_n(v_i) := '0'; else v_we_n(v_i) := '1'; end if;
|
2350 |
|
|
if (addr_cmd_vector(v_i).rst_n) then v_rst_n(v_i) := '0'; else v_rst_n(v_i) := '1'; end if;
|
2351 |
|
|
|
2352 |
|
|
end loop;
|
2353 |
|
|
|
2354 |
|
|
addr := v_addr;
|
2355 |
|
|
ba := v_ba;
|
2356 |
|
|
cke := v_cke;
|
2357 |
|
|
cs_n := v_cs_n;
|
2358 |
|
|
odt := v_odt;
|
2359 |
|
|
cas_n := v_cas_n;
|
2360 |
|
|
ras_n := v_ras_n;
|
2361 |
|
|
we_n := v_we_n;
|
2362 |
|
|
rst_n := v_rst_n;
|
2363 |
|
|
|
2364 |
|
|
end procedure;
|
2365 |
|
|
|
2366 |
|
|
|
2367 |
|
|
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
|
2368 |
|
|
addr_cmd_vector : in t_addr_cmd_vector;
|
2369 |
|
|
signal addr : out std_logic_vector;
|
2370 |
|
|
signal ba : out std_logic_vector;
|
2371 |
|
|
signal cas_n : out std_logic_vector;
|
2372 |
|
|
signal ras_n : out std_logic_vector;
|
2373 |
|
|
signal we_n : out std_logic_vector;
|
2374 |
|
|
signal cke : out std_logic_vector;
|
2375 |
|
|
signal cs_n : out std_logic_vector;
|
2376 |
|
|
signal odt : out std_logic_vector;
|
2377 |
|
|
signal rst_n : out std_logic_vector
|
2378 |
|
|
)
|
2379 |
|
|
is
|
2380 |
|
|
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
|
2381 |
|
|
variable v_vec_len : natural range 1 to 4;
|
2382 |
|
|
variable v_seq_ac_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
|
2383 |
|
|
variable v_seq_ac_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
|
2384 |
|
|
variable v_seq_ac_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
|
2385 |
|
|
variable v_seq_ac_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
|
2386 |
|
|
variable v_seq_ac_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
|
2387 |
|
|
variable v_seq_ac_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
|
2388 |
|
|
variable v_seq_ac_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
|
2389 |
|
|
variable v_seq_ac_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
|
2390 |
|
|
variable v_seq_ac_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
|
2391 |
|
|
|
2392 |
|
|
begin
|
2393 |
|
|
|
2394 |
|
|
unpack_addr_cmd_vector (
|
2395 |
|
|
addr_cmd_vector,
|
2396 |
|
|
config_rec,
|
2397 |
|
|
v_seq_ac_addr,
|
2398 |
|
|
v_seq_ac_ba,
|
2399 |
|
|
v_seq_ac_cas_n,
|
2400 |
|
|
v_seq_ac_ras_n,
|
2401 |
|
|
v_seq_ac_we_n,
|
2402 |
|
|
v_seq_ac_cke,
|
2403 |
|
|
v_seq_ac_cs_n,
|
2404 |
|
|
v_seq_ac_odt,
|
2405 |
|
|
v_seq_ac_rst_n);
|
2406 |
|
|
|
2407 |
|
|
addr <= v_seq_ac_addr;
|
2408 |
|
|
ba <= v_seq_ac_ba;
|
2409 |
|
|
cas_n <= v_seq_ac_cas_n;
|
2410 |
|
|
ras_n <= v_seq_ac_ras_n;
|
2411 |
|
|
we_n <= v_seq_ac_we_n;
|
2412 |
|
|
cke <= v_seq_ac_cke;
|
2413 |
|
|
cs_n <= v_seq_ac_cs_n;
|
2414 |
|
|
odt <= v_seq_ac_odt;
|
2415 |
|
|
rst_n <= v_seq_ac_rst_n;
|
2416 |
|
|
|
2417 |
|
|
end procedure;
|
2418 |
|
|
|
2419 |
|
|
-- -----------------------------------------------------------
|
2420 |
|
|
-- function to mask each bit of signal signal_name in addr_cmd_
|
2421 |
|
|
-- -----------------------------------------------------------
|
2422 |
|
|
-- -----------------------------------------------------------
|
2423 |
|
|
-- function to mask each bit of signal signal_name in addr_cmd_vector with mask_value
|
2424 |
|
|
-- -----------------------------------------------------------
|
2425 |
|
|
function mask ( config_rec : in t_addr_cmd_config_rec;
|
2426 |
|
|
addr_cmd_vector : in t_addr_cmd_vector;
|
2427 |
|
|
signal_name : in t_addr_cmd_signals;
|
2428 |
|
|
mask_value : in std_logic
|
2429 |
|
|
) return t_addr_cmd_vector
|
2430 |
|
|
is
|
2431 |
|
|
variable v_i : integer;
|
2432 |
|
|
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
|
2433 |
|
|
begin
|
2434 |
|
|
|
2435 |
|
|
v_addr_cmd_vector := addr_cmd_vector;
|
2436 |
|
|
|
2437 |
|
|
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
|
2438 |
|
|
|
2439 |
|
|
case signal_name is
|
2440 |
|
|
|
2441 |
|
|
when addr => if (mask_value = '0') then v_addr_cmd_vector(v_i).addr := 0; else v_addr_cmd_vector(v_i).addr := (2 ** config_rec.num_addr_bits) - 1; end if;
|
2442 |
|
|
when ba => if (mask_value = '0') then v_addr_cmd_vector(v_i).ba := 0; else v_addr_cmd_vector(v_i).ba := (2 ** config_rec.num_ba_bits) - 1; end if;
|
2443 |
|
|
when cas_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cas_n := true; else v_addr_cmd_vector(v_i).cas_n := false; end if;
|
2444 |
|
|
when ras_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).ras_n := true; else v_addr_cmd_vector(v_i).ras_n := false; end if;
|
2445 |
|
|
when we_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).we_n := true; else v_addr_cmd_vector(v_i).we_n := false; end if;
|
2446 |
|
|
when cke => if (mask_value = '0') then v_addr_cmd_vector(v_i).cke := 0; else v_addr_cmd_vector(v_i).cke := (2**config_rec.num_ranks) -1; end if;
|
2447 |
|
|
when cs_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cs_n := 0; else v_addr_cmd_vector(v_i).cs_n := (2**config_rec.num_ranks) -1; end if;
|
2448 |
|
|
when odt => if (mask_value = '0') then v_addr_cmd_vector(v_i).odt := 0; else v_addr_cmd_vector(v_i).odt := (2**config_rec.num_ranks) -1; end if;
|
2449 |
|
|
when rst_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).rst_n := true; else v_addr_cmd_vector(v_i).rst_n := false; end if;
|
2450 |
|
|
|
2451 |
|
|
when others => report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
|
2452 |
|
|
|
2453 |
|
|
end case;
|
2454 |
|
|
|
2455 |
|
|
end loop;
|
2456 |
|
|
|
2457 |
|
|
return v_addr_cmd_vector;
|
2458 |
|
|
|
2459 |
|
|
end function;
|
2460 |
|
|
|
2461 |
|
|
-- -----------------------------------------------------------
|
2462 |
|
|
-- procedure to mask each bit of signal signal_name in addr_cmd_vector with mask_value
|
2463 |
|
|
-- -----------------------------------------------------------
|
2464 |
|
|
procedure mask( config_rec : in t_addr_cmd_config_rec;
|
2465 |
|
|
signal addr_cmd_vector : inout t_addr_cmd_vector;
|
2466 |
|
|
signal_name : in t_addr_cmd_signals;
|
2467 |
|
|
mask_value : in std_logic
|
2468 |
|
|
)
|
2469 |
|
|
is
|
2470 |
|
|
variable v_i : integer;
|
2471 |
|
|
begin
|
2472 |
|
|
|
2473 |
|
|
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
|
2474 |
|
|
|
2475 |
|
|
case signal_name is
|
2476 |
|
|
|
2477 |
|
|
when addr => if (mask_value = '0') then addr_cmd_vector(v_i).addr <= 0; else addr_cmd_vector(v_i).addr <= (2 ** config_rec.num_addr_bits) - 1; end if;
|
2478 |
|
|
when ba => if (mask_value = '0') then addr_cmd_vector(v_i).ba <= 0; else addr_cmd_vector(v_i).ba <= (2 ** config_rec.num_ba_bits) - 1; end if;
|
2479 |
|
|
when cas_n => if (mask_value = '0') then addr_cmd_vector(v_i).cas_n <= true; else addr_cmd_vector(v_i).cas_n <= false; end if;
|
2480 |
|
|
when ras_n => if (mask_value = '0') then addr_cmd_vector(v_i).ras_n <= true; else addr_cmd_vector(v_i).ras_n <= false; end if;
|
2481 |
|
|
when we_n => if (mask_value = '0') then addr_cmd_vector(v_i).we_n <= true; else addr_cmd_vector(v_i).we_n <= false; end if;
|
2482 |
|
|
when cke => if (mask_value = '0') then addr_cmd_vector(v_i).cke <= 0; else addr_cmd_vector(v_i).cke <= (2**config_rec.num_ranks) -1; end if;
|
2483 |
|
|
when cs_n => if (mask_value = '0') then addr_cmd_vector(v_i).cs_n <= 0; else addr_cmd_vector(v_i).cs_n <= (2**config_rec.num_ranks) -1; end if;
|
2484 |
|
|
when odt => if (mask_value = '0') then addr_cmd_vector(v_i).odt <= 0; else addr_cmd_vector(v_i).odt <= (2**config_rec.num_ranks) -1; end if;
|
2485 |
|
|
when rst_n => if (mask_value = '0') then addr_cmd_vector(v_i).rst_n <= true; else addr_cmd_vector(v_i).rst_n <= false; end if;
|
2486 |
|
|
|
2487 |
|
|
when others => report ac_report_prefix & "masking not supported for the given signal name" severity failure;
|
2488 |
|
|
|
2489 |
|
|
end case;
|
2490 |
|
|
|
2491 |
|
|
end loop;
|
2492 |
|
|
|
2493 |
|
|
end procedure;
|
2494 |
|
|
|
2495 |
|
|
|
2496 |
|
|
-- -----------------------------------------------------------
|
2497 |
|
|
-- function to mask a given bit (mask_bit) of signal signal_name in addr_cmd_vector with mask_value
|
2498 |
|
|
-- -----------------------------------------------------------
|
2499 |
|
|
function mask ( config_rec : in t_addr_cmd_config_rec;
|
2500 |
|
|
addr_cmd_vector : in t_addr_cmd_vector;
|
2501 |
|
|
signal_name : in t_addr_cmd_signals;
|
2502 |
|
|
mask_value : in std_logic;
|
2503 |
|
|
mask_bit : in natural
|
2504 |
|
|
) return t_addr_cmd_vector
|
2505 |
|
|
is
|
2506 |
|
|
variable v_i : integer;
|
2507 |
|
|
variable v_addr : std_logic_vector(config_rec.num_addr_bits-1 downto 0); -- v_addr is bit vector of address
|
2508 |
|
|
variable v_ba : std_logic_vector(config_rec.num_ba_bits-1 downto 0); -- v_addr is bit vector of bank address
|
2509 |
|
|
variable v_vec_len : natural range 0 to 4;
|
2510 |
|
|
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
|
2511 |
|
|
begin
|
2512 |
|
|
|
2513 |
|
|
v_addr_cmd_vector := addr_cmd_vector;
|
2514 |
|
|
v_vec_len := config_rec.cmds_per_clk;
|
2515 |
|
|
|
2516 |
|
|
for v_i in 0 to v_vec_len-1 loop
|
2517 |
|
|
|
2518 |
|
|
case signal_name is
|
2519 |
|
|
|
2520 |
|
|
when addr =>
|
2521 |
|
|
v_addr := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).addr,v_addr'length));
|
2522 |
|
|
v_addr(mask_bit) := mask_value;
|
2523 |
|
|
v_addr_cmd_vector(v_i).addr := to_integer(unsigned(v_addr));
|
2524 |
|
|
|
2525 |
|
|
when ba =>
|
2526 |
|
|
v_ba := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).ba,v_ba'length));
|
2527 |
|
|
v_ba(mask_bit) := mask_value;
|
2528 |
|
|
v_addr_cmd_vector(v_i).ba := to_integer(unsigned(v_ba));
|
2529 |
|
|
|
2530 |
|
|
when others =>
|
2531 |
|
|
report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
|
2532 |
|
|
|
2533 |
|
|
end case;
|
2534 |
|
|
|
2535 |
|
|
end loop;
|
2536 |
|
|
|
2537 |
|
|
return v_addr_cmd_vector;
|
2538 |
|
|
|
2539 |
|
|
end function;
|
2540 |
|
|
|
2541 |
|
|
--
|
2542 |
|
|
end altera_ddr_phy_alt_mem_phy_addr_cmd_pkg;
|
2543 |
|
|
|
2544 |
|
|
--
|
2545 |
|
|
|
2546 |
|
|
-- -----------------------------------------------------------------------------
|
2547 |
|
|
-- Abstract : iram addressing package for the non-levelling AFI PHY sequencer
|
2548 |
|
|
-- The iram address package (alt_mem_phy_iram_addr_pkg) is
|
2549 |
|
|
-- used to define the base addresses used for iram writes
|
2550 |
|
|
-- during calibration.
|
2551 |
|
|
-- -----------------------------------------------------------------------------
|
2552 |
|
|
|
2553 |
|
|
library ieee;
|
2554 |
|
|
use ieee.std_logic_1164.all;
|
2555 |
|
|
use ieee.numeric_std.all;
|
2556 |
|
|
|
2557 |
|
|
--
|
2558 |
|
|
package altera_ddr_phy_alt_mem_phy_iram_addr_pkg IS
|
2559 |
|
|
|
2560 |
|
|
constant c_ihi_size : natural := 8;
|
2561 |
|
|
|
2562 |
|
|
type t_base_hdr_addresses is record
|
2563 |
|
|
base_hdr : natural;
|
2564 |
|
|
rrp : natural;
|
2565 |
|
|
safe_dummy : natural;
|
2566 |
|
|
required_addr_bits : natural;
|
2567 |
|
|
end record;
|
2568 |
|
|
|
2569 |
|
|
function defaults return t_base_hdr_addresses;
|
2570 |
|
|
|
2571 |
|
|
function rrp_pll_phase_mult (dwidth_ratio : in natural;
|
2572 |
|
|
dqs_capture : in natural
|
2573 |
|
|
)
|
2574 |
|
|
return natural;
|
2575 |
|
|
|
2576 |
|
|
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
|
2577 |
|
|
pll_phases : in natural;
|
2578 |
|
|
dq_pins : in natural;
|
2579 |
|
|
dqs_capture : in natural
|
2580 |
|
|
)
|
2581 |
|
|
return natural;
|
2582 |
|
|
|
2583 |
|
|
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
|
2584 |
|
|
pll_phases : in natural;
|
2585 |
|
|
dq_pins : in natural;
|
2586 |
|
|
dqs_capture : in natural
|
2587 |
|
|
)
|
2588 |
|
|
return natural;
|
2589 |
|
|
|
2590 |
|
|
function calc_iram_addresses ( dwidth_ratio : in natural;
|
2591 |
|
|
pll_phases : in natural;
|
2592 |
|
|
dq_pins : in natural;
|
2593 |
|
|
num_ranks : in natural;
|
2594 |
|
|
dqs_capture : in natural
|
2595 |
|
|
)
|
2596 |
|
|
return t_base_hdr_addresses;
|
2597 |
|
|
|
2598 |
|
|
--
|
2599 |
|
|
end altera_ddr_phy_alt_mem_phy_iram_addr_pkg;
|
2600 |
|
|
|
2601 |
|
|
--
|
2602 |
|
|
package body altera_ddr_phy_alt_mem_phy_iram_addr_pkg IS
|
2603 |
|
|
|
2604 |
|
|
-- set some safe default values
|
2605 |
|
|
function defaults return t_base_hdr_addresses is
|
2606 |
|
|
variable temp : t_base_hdr_addresses;
|
2607 |
|
|
begin
|
2608 |
|
|
temp.base_hdr := 0;
|
2609 |
|
|
temp.rrp := 0;
|
2610 |
|
|
temp.safe_dummy := 0;
|
2611 |
|
|
temp.required_addr_bits := 1;
|
2612 |
|
|
return temp;
|
2613 |
|
|
end function;
|
2614 |
|
|
|
2615 |
|
|
-- this function determines now many times the PLL phases are swept through per pin
|
2616 |
|
|
-- i.e. an n * 360 degree phase sweep
|
2617 |
|
|
function rrp_pll_phase_mult (dwidth_ratio : in natural;
|
2618 |
|
|
dqs_capture : in natural
|
2619 |
|
|
)
|
2620 |
|
|
return natural
|
2621 |
|
|
is
|
2622 |
|
|
variable v_output : natural;
|
2623 |
|
|
begin
|
2624 |
|
|
|
2625 |
|
|
if dwidth_ratio = 2 and dqs_capture = 1 then
|
2626 |
|
|
|
2627 |
|
|
v_output := 2; -- if dqs_capture then a 720 degree sweep needed in FR
|
2628 |
|
|
|
2629 |
|
|
else
|
2630 |
|
|
|
2631 |
|
|
v_output := (dwidth_ratio/2);
|
2632 |
|
|
|
2633 |
|
|
end if;
|
2634 |
|
|
|
2635 |
|
|
return v_output;
|
2636 |
|
|
|
2637 |
|
|
end function;
|
2638 |
|
|
|
2639 |
|
|
-- function to calculate how many words are required for a rrp sweep over all pins
|
2640 |
|
|
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
|
2641 |
|
|
pll_phases : in natural;
|
2642 |
|
|
dq_pins : in natural;
|
2643 |
|
|
dqs_capture : in natural
|
2644 |
|
|
)
|
2645 |
|
|
return natural
|
2646 |
|
|
is
|
2647 |
|
|
variable v_output : natural;
|
2648 |
|
|
variable v_phase_mul : natural;
|
2649 |
|
|
begin
|
2650 |
|
|
-- determine the n * 360 degrees of sweep required
|
2651 |
|
|
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
|
2652 |
|
|
|
2653 |
|
|
-- calculate output size
|
2654 |
|
|
v_output := dq_pins * (((v_phase_mul * pll_phases) + 31) / 32);
|
2655 |
|
|
|
2656 |
|
|
return v_output;
|
2657 |
|
|
|
2658 |
|
|
end function;
|
2659 |
|
|
|
2660 |
|
|
-- function to calculate how many words are required for a rrp sweep over all pins
|
2661 |
|
|
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
|
2662 |
|
|
pll_phases : in natural;
|
2663 |
|
|
dq_pins : in natural;
|
2664 |
|
|
dqs_capture : in natural
|
2665 |
|
|
)
|
2666 |
|
|
return natural
|
2667 |
|
|
is
|
2668 |
|
|
variable v_output : natural;
|
2669 |
|
|
variable v_phase_mul : natural;
|
2670 |
|
|
begin
|
2671 |
|
|
-- determine the n * 360 degrees of sweep required
|
2672 |
|
|
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
|
2673 |
|
|
|
2674 |
|
|
-- calculate output size
|
2675 |
|
|
v_output := ((v_phase_mul * pll_phases) + 31) / 32;
|
2676 |
|
|
|
2677 |
|
|
return v_output;
|
2678 |
|
|
|
2679 |
|
|
end function;
|
2680 |
|
|
|
2681 |
|
|
-- return iram addresses
|
2682 |
|
|
function calc_iram_addresses ( dwidth_ratio : in natural;
|
2683 |
|
|
pll_phases : in natural;
|
2684 |
|
|
dq_pins : in natural;
|
2685 |
|
|
num_ranks : in natural;
|
2686 |
|
|
dqs_capture : in natural
|
2687 |
|
|
)
|
2688 |
|
|
return t_base_hdr_addresses
|
2689 |
|
|
is
|
2690 |
|
|
variable working : t_base_hdr_addresses;
|
2691 |
|
|
variable temp : natural;
|
2692 |
|
|
|
2693 |
|
|
variable v_required_words : natural;
|
2694 |
|
|
|
2695 |
|
|
begin
|
2696 |
|
|
|
2697 |
|
|
working.base_hdr := 0;
|
2698 |
|
|
working.rrp := working.base_hdr + c_ihi_size;
|
2699 |
|
|
|
2700 |
|
|
-- work out required number of address bits
|
2701 |
|
|
|
2702 |
|
|
-- + for 1 full rrp calibration
|
2703 |
|
|
v_required_words := iram_wd_for_full_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2; -- +2 for header + footer
|
2704 |
|
|
|
2705 |
|
|
-- * loop per cs
|
2706 |
|
|
v_required_words := v_required_words * num_ranks;
|
2707 |
|
|
|
2708 |
|
|
-- + for 1 rrp_seek result
|
2709 |
|
|
v_required_words := v_required_words + 3; -- 1 header, 1 word result, 1 footer
|
2710 |
|
|
|
2711 |
|
|
-- + 2 mtp_almt passes
|
2712 |
|
|
v_required_words := v_required_words + 2 * (iram_wd_for_one_pin_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2);
|
2713 |
|
|
|
2714 |
|
|
-- + for 2 read_mtp result calculation
|
2715 |
|
|
v_required_words := v_required_words + 3*2; -- 1 header, 1 word result, 1 footer
|
2716 |
|
|
|
2717 |
|
|
-- * possible dwidth_ratio/2 iterations for different ac_nt settings
|
2718 |
|
|
v_required_words := v_required_words * (dwidth_ratio / 2);
|
2719 |
|
|
|
2720 |
|
|
working.safe_dummy := working.rrp + v_required_words;
|
2721 |
|
|
|
2722 |
|
|
temp := working.safe_dummy;
|
2723 |
|
|
working.required_addr_bits := 0;
|
2724 |
|
|
|
2725 |
|
|
while (temp >= 1) loop
|
2726 |
|
|
working.required_addr_bits := working.required_addr_bits + 1;
|
2727 |
|
|
temp := temp /2;
|
2728 |
|
|
end loop;
|
2729 |
|
|
|
2730 |
|
|
return working;
|
2731 |
|
|
|
2732 |
|
|
end function calc_iram_addresses;
|
2733 |
|
|
|
2734 |
|
|
--
|
2735 |
|
|
END altera_ddr_phy_alt_mem_phy_iram_addr_pkg;
|
2736 |
|
|
--
|
2737 |
|
|
|
2738 |
|
|
-- -----------------------------------------------------------------------------
|
2739 |
|
|
-- Abstract : register package for the non-levelling AFI PHY sequencer
|
2740 |
|
|
-- The registers package (alt_mem_phy_regs_pkg) is used to
|
2741 |
|
|
-- combine the definition of the registers for the mmi status
|
2742 |
|
|
-- registers and functions/procedures applied to the registers
|
2743 |
|
|
-- -----------------------------------------------------------------------------
|
2744 |
|
|
|
2745 |
|
|
library ieee;
|
2746 |
|
|
use ieee.std_logic_1164.all;
|
2747 |
|
|
use ieee.numeric_std.all;
|
2748 |
|
|
|
2749 |
|
|
library work;
|
2750 |
|
|
|
2751 |
|
|
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
|
2752 |
|
|
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
|
2753 |
|
|
-- for the stages of DRAM memory calibration.
|
2754 |
|
|
--
|
2755 |
|
|
use work.altera_ddr_phy_alt_mem_phy_record_pkg.all;
|
2756 |
|
|
|
2757 |
|
|
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
|
2758 |
|
|
-- thoughout the sequencer and will not change (for constants which may change between sequencer
|
2759 |
|
|
-- instances generics are used)
|
2760 |
|
|
--
|
2761 |
|
|
use work.altera_ddr_phy_alt_mem_phy_constants_pkg.all;
|
2762 |
|
|
|
2763 |
|
|
--
|
2764 |
|
|
package altera_ddr_phy_alt_mem_phy_regs_pkg is
|
2765 |
|
|
|
2766 |
|
|
-- a prefix for all report signals to identify phy and sequencer block
|
2767 |
|
|
--
|
2768 |
|
|
constant regs_report_prefix : string := "altera_ddr_phy_alt_mem_phy_seq (register package) : ";
|
2769 |
|
|
|
2770 |
|
|
-- ---------------------------------------------------------------
|
2771 |
|
|
-- register declarations with associated functions of:
|
2772 |
|
|
-- default - assign default values
|
2773 |
|
|
-- write - write data into the reg (from avalon i/f)
|
2774 |
|
|
-- read - read data from the reg (sent to the avalon i/f)
|
2775 |
|
|
-- write_clear - clear reg to all zeros
|
2776 |
|
|
-- ---------------------------------------------------------------
|
2777 |
|
|
|
2778 |
|
|
-- TYPE DECLARATIONS
|
2779 |
|
|
|
2780 |
|
|
-- >>>>>>>>>>>>>>>>>>>>>>>>
|
2781 |
|
|
-- Read Only Registers
|
2782 |
|
|
-- >>>>>>>>>>>>>>>>>>>>>>>>
|
2783 |
|
|
|
2784 |
|
|
-- cal_status
|
2785 |
|
|
type t_cal_status is record
|
2786 |
|
|
iram_addr_width : std_logic_vector(3 downto 0);
|
2787 |
|
|
out_of_mem : std_logic;
|
2788 |
|
|
contested_access : std_logic;
|
2789 |
|
|
cal_fail : std_logic;
|
2790 |
|
|
cal_success : std_logic;
|
2791 |
|
|
ctrl_err_code : std_logic_vector(7 downto 0);
|
2792 |
|
|
trefi_failure : std_logic;
|
2793 |
|
|
int_ac_1t : std_logic;
|
2794 |
|
|
dqs_capture : std_logic;
|
2795 |
|
|
iram_present : std_logic;
|
2796 |
|
|
active_block : std_logic_vector(3 downto 0);
|
2797 |
|
|
current_stage : std_logic_vector(7 downto 0);
|
2798 |
|
|
end record;
|
2799 |
|
|
|
2800 |
|
|
-- codvw status
|
2801 |
|
|
type t_codvw_status is record
|
2802 |
|
|
cal_codvw_phase : std_logic_vector(7 downto 0);
|
2803 |
|
|
cal_codvw_size : std_logic_vector(7 downto 0);
|
2804 |
|
|
codvw_trk_shift : std_logic_vector(11 downto 0);
|
2805 |
|
|
codvw_grt_one_dvw : std_logic;
|
2806 |
|
|
end record t_codvw_status;
|
2807 |
|
|
|
2808 |
|
|
-- test status report
|
2809 |
|
|
type t_test_status is record
|
2810 |
|
|
ack_seen : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
|
2811 |
|
|
pll_mmi_err : std_logic_vector(1 downto 0);
|
2812 |
|
|
pll_busy : std_logic;
|
2813 |
|
|
end record;
|
2814 |
|
|
|
2815 |
|
|
-- define all the read only registers :
|
2816 |
|
|
type t_ro_regs is record
|
2817 |
|
|
cal_status : t_cal_status;
|
2818 |
|
|
codvw_status : t_codvw_status;
|
2819 |
|
|
test_status : t_test_status;
|
2820 |
|
|
end record;
|
2821 |
|
|
|
2822 |
|
|
-- >>>>>>>>>>>>>>>>>>>>>>>>
|
2823 |
|
|
-- Read / Write Registers
|
2824 |
|
|
-- >>>>>>>>>>>>>>>>>>>>>>>>
|
2825 |
|
|
|
2826 |
|
|
-- Calibration control register
|
2827 |
|
|
type t_hl_css is record
|
2828 |
|
|
hl_css : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
|
2829 |
|
|
cal_start : std_logic;
|
2830 |
|
|
end record t_hl_css;
|
2831 |
|
|
|
2832 |
|
|
-- Mode register A
|
2833 |
|
|
type t_mr_register_a is record
|
2834 |
|
|
mr0 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
|
2835 |
|
|
mr1 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
|
2836 |
|
|
end record t_mr_register_a;
|
2837 |
|
|
|
2838 |
|
|
-- Mode register B
|
2839 |
|
|
type t_mr_register_b is record
|
2840 |
|
|
mr2 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
|
2841 |
|
|
mr3 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
|
2842 |
|
|
end record t_mr_register_b;
|
2843 |
|
|
|
2844 |
|
|
-- algorithm parameterisation register
|
2845 |
|
|
type t_parameterisation_reg_a is record
|
2846 |
|
|
nominal_poa_phase_lead : std_logic_vector(3 downto 0);
|
2847 |
|
|
maximum_poa_delay : std_logic_vector(3 downto 0);
|
2848 |
|
|
num_phases_per_tck_pll : std_logic_vector(3 downto 0);
|
2849 |
|
|
pll_360_sweeps : std_logic_vector(3 downto 0);
|
2850 |
|
|
nominal_dqs_delay : std_logic_vector(2 downto 0);
|
2851 |
|
|
extend_octrt_by : std_logic_vector(3 downto 0);
|
2852 |
|
|
delay_octrt_by : std_logic_vector(3 downto 0);
|
2853 |
|
|
end record;
|
2854 |
|
|
|
2855 |
|
|
-- test signal register
|
2856 |
|
|
type t_if_test_reg is record
|
2857 |
|
|
pll_phs_shft_phase_sel : natural range 0 to 15;
|
2858 |
|
|
pll_phs_shft_up_wc : std_logic;
|
2859 |
|
|
pll_phs_shft_dn_wc : std_logic;
|
2860 |
|
|
ac_1t_toggle : std_logic; -- unused
|
2861 |
|
|
tracking_period_ms : std_logic_vector(7 downto 0); -- 0 = as fast as possible approx in ms
|
2862 |
|
|
tracking_units_are_10us : std_logic;
|
2863 |
|
|
end record;
|
2864 |
|
|
|
2865 |
|
|
-- define all the read/write registers
|
2866 |
|
|
type t_rw_regs is record
|
2867 |
|
|
mr_reg_a : t_mr_register_a;
|
2868 |
|
|
mr_reg_b : t_mr_register_b;
|
2869 |
|
|
rw_hl_css : t_hl_css;
|
2870 |
|
|
rw_param_reg : t_parameterisation_reg_a;
|
2871 |
|
|
rw_if_test : t_if_test_reg;
|
2872 |
|
|
end record;
|
2873 |
|
|
|
2874 |
|
|
-- >>>>>>>>>>>>>>>>>>>>>>>
|
2875 |
|
|
-- Group all registers
|
2876 |
|
|
-- >>>>>>>>>>>>>>>>>>>>>>>
|
2877 |
|
|
|
2878 |
|
|
type t_mmi_regs is record
|
2879 |
|
|
rw_regs : t_rw_regs;
|
2880 |
|
|
ro_regs : t_ro_regs;
|
2881 |
|
|
enable_writes : std_logic;
|
2882 |
|
|
end record;
|
2883 |
|
|
|
2884 |
|
|
|
2885 |
|
|
-- FUNCTION DECLARATIONS
|
2886 |
|
|
|
2887 |
|
|
-- >>>>>>>>>>>>>>>>>>>>>>>>
|
2888 |
|
|
-- Read Only Registers
|
2889 |
|
|
-- >>>>>>>>>>>>>>>>>>>>>>>>
|
2890 |
|
|
|
2891 |
|
|
-- cal_status
|
2892 |
|
|
function defaults return t_cal_status;
|
2893 |
|
|
function defaults ( ctrl_mmi : in t_ctrl_mmi;
|
2894 |
|
|
USE_IRAM : in std_logic;
|
2895 |
|
|
dqs_capture : in natural;
|
2896 |
|
|
int_ac_1t : in std_logic;
|
2897 |
|
|
trefi_failure : in std_logic;
|
2898 |
|
|
iram_status : in t_iram_stat;
|
2899 |
|
|
IRAM_AWIDTH : in natural
|
2900 |
|
|
) return t_cal_status;
|
2901 |
|
|
|
2902 |
|
|
function read (reg : t_cal_status) return std_logic_vector;
|
2903 |
|
|
|
2904 |
|
|
-- codvw status
|
2905 |
|
|
function defaults return t_codvw_status;
|
2906 |
|
|
function defaults ( dgrb_mmi : t_dgrb_mmi
|
2907 |
|
|
) return t_codvw_status;
|
2908 |
|
|
|
2909 |
|
|
function read (reg : in t_codvw_status) return std_logic_vector;
|
2910 |
|
|
|
2911 |
|
|
|
2912 |
|
|
-- test status report
|
2913 |
|
|
|
2914 |
|
|
function defaults return t_test_status;
|
2915 |
|
|
|
2916 |
|
|
function defaults ( ctrl_mmi : in t_ctrl_mmi;
|
2917 |
|
|
pll_mmi : in t_pll_mmi;
|
2918 |
|
|
rw_if_test : t_if_test_reg
|
2919 |
|
|
) return t_test_status;
|
2920 |
|
|
|
2921 |
|
|
function read (reg : t_test_status) return std_logic_vector;
|
2922 |
|
|
|
2923 |
|
|
-- define all the read only registers
|
2924 |
|
|
|
2925 |
|
|
function defaults return t_ro_regs;
|
2926 |
|
|
|
2927 |
|
|
function defaults (dgrb_mmi : t_dgrb_mmi;
|
2928 |
|
|
ctrl_mmi : t_ctrl_mmi;
|
2929 |
|
|
pll_mmi : t_pll_mmi;
|
2930 |
|
|
rw_if_test : t_if_test_reg;
|
2931 |
|
|
USE_IRAM : std_logic;
|
2932 |
|
|
dqs_capture : natural;
|
2933 |
|
|
int_ac_1t : std_logic;
|
2934 |
|
|
trefi_failure : std_logic;
|
2935 |
|
|
iram_status : t_iram_stat;
|
2936 |
|
|
IRAM_AWIDTH : natural
|
2937 |
|
|
) return t_ro_regs;
|
2938 |
|
|
|
2939 |
|
|
-- >>>>>>>>>>>>>>>>>>>>>>>>
|
2940 |
|
|
-- Read / Write Registers
|
2941 |
|
|
-- >>>>>>>>>>>>>>>>>>>>>>>>
|
2942 |
|
|
|
2943 |
|
|
-- Calibration control register
|
2944 |
|
|
-- high level calibration stage set register comprises a bit vector for
|
2945 |
|
|
-- the calibration stage coding and the 1 control bit.
|
2946 |
|
|
|
2947 |
|
|
function defaults return t_hl_css;
|
2948 |
|
|
function write (wdata_in : std_logic_vector(31 downto 0)) return t_hl_css;
|
2949 |
|
|
function read (reg : in t_hl_css) return std_logic_vector;
|
2950 |
|
|
|
2951 |
|
|
-- Mode register A
|
2952 |
|
|
-- mode registers 0 and 1 (mr and emr1)
|
2953 |
|
|
|
2954 |
|
|
function defaults return t_mr_register_a;
|
2955 |
|
|
function defaults ( mr0 : in std_logic_vector;
|
2956 |
|
|
mr1 : in std_logic_vector
|
2957 |
|
|
) return t_mr_register_a;
|
2958 |
|
|
|
2959 |
|
|
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a;
|
2960 |
|
|
function read (reg : in t_mr_register_a) return std_logic_vector;
|
2961 |
|
|
|
2962 |
|
|
-- Mode register B
|
2963 |
|
|
-- mode registers 2 and 3 (emr2 and emr3) - not present in ddr DRAM
|
2964 |
|
|
|
2965 |
|
|
function defaults return t_mr_register_b;
|
2966 |
|
|
function defaults ( mr2 : in std_logic_vector;
|
2967 |
|
|
mr3 : in std_logic_vector
|
2968 |
|
|
) return t_mr_register_b;
|
2969 |
|
|
|
2970 |
|
|
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b;
|
2971 |
|
|
function read (reg : in t_mr_register_b) return std_logic_vector;
|
2972 |
|
|
|
2973 |
|
|
-- algorithm parameterisation register
|
2974 |
|
|
|
2975 |
|
|
function defaults return t_parameterisation_reg_a;
|
2976 |
|
|
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
|
2977 |
|
|
PLL_STEPS_PER_CYCLE : in natural;
|
2978 |
|
|
pll_360_sweeps : in natural
|
2979 |
|
|
) return t_parameterisation_reg_a;
|
2980 |
|
|
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector;
|
2981 |
|
|
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a;
|
2982 |
|
|
|
2983 |
|
|
-- test signal register
|
2984 |
|
|
|
2985 |
|
|
function defaults return t_if_test_reg;
|
2986 |
|
|
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
|
2987 |
|
|
) return t_if_test_reg;
|
2988 |
|
|
function read ( reg : in t_if_test_reg) return std_logic_vector;
|
2989 |
|
|
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg;
|
2990 |
|
|
procedure write_clear (signal reg : inout t_if_test_reg);
|
2991 |
|
|
|
2992 |
|
|
|
2993 |
|
|
-- define all the read/write registers
|
2994 |
|
|
|
2995 |
|
|
function defaults return t_rw_regs;
|
2996 |
|
|
|
2997 |
|
|
function defaults(
|
2998 |
|
|
mr0 : in std_logic_vector;
|
2999 |
|
|
mr1 : in std_logic_vector;
|
3000 |
|
|
mr2 : in std_logic_vector;
|
3001 |
|
|
mr3 : in std_logic_vector;
|
3002 |
|
|
NOM_DQS_PHASE_SETTING : in natural;
|
3003 |
|
|
PLL_STEPS_PER_CYCLE : in natural;
|
3004 |
|
|
pll_360_sweeps : in natural;
|
3005 |
|
|
TRACKING_INTERVAL_IN_MS : in natural;
|
3006 |
|
|
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
|
3007 |
|
|
)return t_rw_regs;
|
3008 |
|
|
|
3009 |
|
|
procedure write_clear (signal regs : inout t_rw_regs);
|
3010 |
|
|
|
3011 |
|
|
-- >>>>>>>>>>>>>>>>>>>>>>>
|
3012 |
|
|
-- Group all registers
|
3013 |
|
|
-- >>>>>>>>>>>>>>>>>>>>>>>
|
3014 |
|
|
|
3015 |
|
|
function defaults return t_mmi_regs;
|
3016 |
|
|
|
3017 |
|
|
function v_read (mmi_regs : in t_mmi_regs;
|
3018 |
|
|
address : in natural
|
3019 |
|
|
) return std_logic_vector;
|
3020 |
|
|
|
3021 |
|
|
function read (signal mmi_regs : in t_mmi_regs;
|
3022 |
|
|
address : in natural
|
3023 |
|
|
) return std_logic_vector;
|
3024 |
|
|
|
3025 |
|
|
procedure write (mmi_regs : inout t_mmi_regs;
|
3026 |
|
|
address : in natural;
|
3027 |
|
|
wdata : in std_logic_vector(31 downto 0));
|
3028 |
|
|
|
3029 |
|
|
-- >>>>>>>>>>>>>>>>>>>>>>>
|
3030 |
|
|
-- functions to communicate register settings to other sequencer blocks
|
3031 |
|
|
-- >>>>>>>>>>>>>>>>>>>>>>>
|
3032 |
|
|
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig;
|
3033 |
|
|
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl;
|
3034 |
|
|
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl;
|
3035 |
|
|
|
3036 |
|
|
function pack_record ( ip_regs : t_rw_regs) return t_algm_paramaterisation;
|
3037 |
|
|
|
3038 |
|
|
|
3039 |
|
|
-- >>>>>>>>>>>>>>>>>>>>>>>
|
3040 |
|
|
-- helper functions
|
3041 |
|
|
-- >>>>>>>>>>>>>>>>>>>>>>>
|
3042 |
|
|
|
3043 |
|
|
function to_t_hl_css_reg (hl_css : t_hl_css ) return t_hl_css_reg;
|
3044 |
|
|
|
3045 |
|
|
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
|
3046 |
|
|
) return std_logic_vector;
|
3047 |
|
|
|
3048 |
|
|
-- encoding of stage and active block for register setting
|
3049 |
|
|
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id) return std_logic_vector;
|
3050 |
|
|
function encode_active_block (active_block : t_ctrl_active_block) return std_logic_vector;
|
3051 |
|
|
|
3052 |
|
|
--
|
3053 |
|
|
end altera_ddr_phy_alt_mem_phy_regs_pkg;
|
3054 |
|
|
|
3055 |
|
|
--
|
3056 |
|
|
package body altera_ddr_phy_alt_mem_phy_regs_pkg is
|
3057 |
|
|
|
3058 |
|
|
-- >>>>>>>>>>>>>>>>>>>>
|
3059 |
|
|
-- Read Only Registers
|
3060 |
|
|
-- >>>>>>>>>>>>>>>>>>>
|
3061 |
|
|
|
3062 |
|
|
-- ---------------------------------------------------------------
|
3063 |
|
|
-- CODVW status report
|
3064 |
|
|
-- ---------------------------------------------------------------
|
3065 |
|
|
|
3066 |
|
|
function defaults return t_codvw_status is
|
3067 |
|
|
variable temp: t_codvw_status;
|
3068 |
|
|
begin
|
3069 |
|
|
temp.cal_codvw_phase := (others => '0');
|
3070 |
|
|
temp.cal_codvw_size := (others => '0');
|
3071 |
|
|
temp.codvw_trk_shift := (others => '0');
|
3072 |
|
|
temp.codvw_grt_one_dvw := '0';
|
3073 |
|
|
return temp;
|
3074 |
|
|
end function;
|
3075 |
|
|
|
3076 |
|
|
function defaults ( dgrb_mmi : t_dgrb_mmi
|
3077 |
|
|
) return t_codvw_status is
|
3078 |
|
|
variable temp: t_codvw_status;
|
3079 |
|
|
begin
|
3080 |
|
|
temp := defaults;
|
3081 |
|
|
temp.cal_codvw_phase := dgrb_mmi.cal_codvw_phase;
|
3082 |
|
|
temp.cal_codvw_size := dgrb_mmi.cal_codvw_size;
|
3083 |
|
|
temp.codvw_trk_shift := dgrb_mmi.codvw_trk_shift;
|
3084 |
|
|
temp.codvw_grt_one_dvw := dgrb_mmi.codvw_grt_one_dvw;
|
3085 |
|
|
return temp;
|
3086 |
|
|
end function;
|
3087 |
|
|
|
3088 |
|
|
function read (reg : in t_codvw_status) return std_logic_vector is
|
3089 |
|
|
variable temp : std_logic_vector(31 downto 0);
|
3090 |
|
|
begin
|
3091 |
|
|
temp := (others => '0');
|
3092 |
|
|
temp(31 downto 24) := reg.cal_codvw_phase;
|
3093 |
|
|
temp(23 downto 16) := reg.cal_codvw_size;
|
3094 |
|
|
temp(15 downto 4) := reg.codvw_trk_shift;
|
3095 |
|
|
temp(0) := reg.codvw_grt_one_dvw;
|
3096 |
|
|
return temp;
|
3097 |
|
|
end function;
|
3098 |
|
|
|
3099 |
|
|
-- ---------------------------------------------------------------
|
3100 |
|
|
-- Calibration status report
|
3101 |
|
|
-- ---------------------------------------------------------------
|
3102 |
|
|
|
3103 |
|
|
function defaults return t_cal_status is
|
3104 |
|
|
variable temp: t_cal_status;
|
3105 |
|
|
begin
|
3106 |
|
|
temp.iram_addr_width := (others => '0');
|
3107 |
|
|
temp.out_of_mem := '0';
|
3108 |
|
|
temp.contested_access := '0';
|
3109 |
|
|
temp.cal_fail := '0';
|
3110 |
|
|
temp.cal_success := '0';
|
3111 |
|
|
temp.ctrl_err_code := (others => '0');
|
3112 |
|
|
temp.trefi_failure := '0';
|
3113 |
|
|
temp.int_ac_1t := '0';
|
3114 |
|
|
temp.dqs_capture := '0';
|
3115 |
|
|
temp.iram_present := '0';
|
3116 |
|
|
temp.active_block := (others => '0');
|
3117 |
|
|
temp.current_stage := (others => '0');
|
3118 |
|
|
return temp;
|
3119 |
|
|
end function;
|
3120 |
|
|
|
3121 |
|
|
function defaults ( ctrl_mmi : in t_ctrl_mmi;
|
3122 |
|
|
USE_IRAM : in std_logic;
|
3123 |
|
|
dqs_capture : in natural;
|
3124 |
|
|
int_ac_1t : in std_logic;
|
3125 |
|
|
trefi_failure : in std_logic;
|
3126 |
|
|
iram_status : in t_iram_stat;
|
3127 |
|
|
IRAM_AWIDTH : in natural
|
3128 |
|
|
) return t_cal_status is
|
3129 |
|
|
variable temp : t_cal_status;
|
3130 |
|
|
begin
|
3131 |
|
|
temp := defaults;
|
3132 |
|
|
temp.iram_addr_width := std_logic_vector(to_unsigned(IRAM_AWIDTH, temp.iram_addr_width'length));
|
3133 |
|
|
temp.out_of_mem := iram_status.out_of_mem;
|
3134 |
|
|
temp.contested_access := iram_status.contested_access;
|
3135 |
|
|
temp.cal_fail := ctrl_mmi.ctrl_calibration_fail;
|
3136 |
|
|
temp.cal_success := ctrl_mmi.ctrl_calibration_success;
|
3137 |
|
|
temp.ctrl_err_code := ctrl_mmi.ctrl_err_code;
|
3138 |
|
|
temp.trefi_failure := trefi_failure;
|
3139 |
|
|
temp.int_ac_1t := int_ac_1t;
|
3140 |
|
|
|
3141 |
|
|
if dqs_capture = 1 then
|
3142 |
|
|
temp.dqs_capture := '1';
|
3143 |
|
|
elsif dqs_capture = 0 then
|
3144 |
|
|
temp.dqs_capture := '0';
|
3145 |
|
|
else
|
3146 |
|
|
report regs_report_prefix & " invalid value for dqs_capture constant of " & integer'image(dqs_capture) severity failure;
|
3147 |
|
|
end if;
|
3148 |
|
|
|
3149 |
|
|
temp.iram_present := USE_IRAM;
|
3150 |
|
|
temp.active_block := encode_active_block(ctrl_mmi.ctrl_current_active_block);
|
3151 |
|
|
temp.current_stage := encode_current_stage(ctrl_mmi.ctrl_current_stage);
|
3152 |
|
|
return temp;
|
3153 |
|
|
end function;
|
3154 |
|
|
|
3155 |
|
|
-- read for mmi status register
|
3156 |
|
|
function read ( reg : t_cal_status
|
3157 |
|
|
) return std_logic_vector is
|
3158 |
|
|
variable output : std_logic_vector(31 downto 0);
|
3159 |
|
|
begin
|
3160 |
|
|
|
3161 |
|
|
output := (others => '0');
|
3162 |
|
|
output( 7 downto 0) := reg.current_stage;
|
3163 |
|
|
output(11 downto 8) := reg.active_block;
|
3164 |
|
|
output(12) := reg.iram_present;
|
3165 |
|
|
output(13) := reg.dqs_capture;
|
3166 |
|
|
output(14) := reg.int_ac_1t;
|
3167 |
|
|
output(15) := reg.trefi_failure;
|
3168 |
|
|
output(23 downto 16) := reg.ctrl_err_code;
|
3169 |
|
|
output(24) := reg.cal_success;
|
3170 |
|
|
output(25) := reg.cal_fail;
|
3171 |
|
|
output(26) := reg.contested_access;
|
3172 |
|
|
output(27) := reg.out_of_mem;
|
3173 |
|
|
output(31 downto 28) := reg.iram_addr_width;
|
3174 |
|
|
|
3175 |
|
|
return output;
|
3176 |
|
|
end function;
|
3177 |
|
|
|
3178 |
|
|
-- ---------------------------------------------------------------
|
3179 |
|
|
-- Test status report
|
3180 |
|
|
-- ---------------------------------------------------------------
|
3181 |
|
|
|
3182 |
|
|
function defaults return t_test_status is
|
3183 |
|
|
variable temp: t_test_status;
|
3184 |
|
|
begin
|
3185 |
|
|
temp.ack_seen := (others => '0');
|
3186 |
|
|
temp.pll_mmi_err := (others => '0');
|
3187 |
|
|
temp.pll_busy := '0';
|
3188 |
|
|
return temp;
|
3189 |
|
|
end function;
|
3190 |
|
|
|
3191 |
|
|
function defaults ( ctrl_mmi : in t_ctrl_mmi;
|
3192 |
|
|
pll_mmi : in t_pll_mmi;
|
3193 |
|
|
rw_if_test : t_if_test_reg
|
3194 |
|
|
) return t_test_status is
|
3195 |
|
|
variable temp : t_test_status;
|
3196 |
|
|
begin
|
3197 |
|
|
temp := defaults;
|
3198 |
|
|
temp.ack_seen := pack_ack_seen(ctrl_mmi.ctrl_cal_stage_ack_seen);
|
3199 |
|
|
temp.pll_mmi_err := pll_mmi.err;
|
3200 |
|
|
temp.pll_busy := pll_mmi.pll_busy or rw_if_test.pll_phs_shft_up_wc or rw_if_test.pll_phs_shft_dn_wc;
|
3201 |
|
|
return temp;
|
3202 |
|
|
end function;
|
3203 |
|
|
|
3204 |
|
|
-- read for mmi status register
|
3205 |
|
|
function read ( reg : t_test_status
|
3206 |
|
|
) return std_logic_vector is
|
3207 |
|
|
variable output : std_logic_vector(31 downto 0);
|
3208 |
|
|
begin
|
3209 |
|
|
|
3210 |
|
|
output := (others => '0');
|
3211 |
|
|
output(31 downto 32-c_hl_ccs_num_stages) := reg.ack_seen;
|
3212 |
|
|
output( 5 downto 4) := reg.pll_mmi_err;
|
3213 |
|
|
output(0) := reg.pll_busy;
|
3214 |
|
|
|
3215 |
|
|
return output;
|
3216 |
|
|
end function;
|
3217 |
|
|
|
3218 |
|
|
-------------------------------------------------
|
3219 |
|
|
-- FOR ALL RO REGS:
|
3220 |
|
|
-------------------------------------------------
|
3221 |
|
|
|
3222 |
|
|
function defaults return t_ro_regs is
|
3223 |
|
|
variable temp: t_ro_regs;
|
3224 |
|
|
begin
|
3225 |
|
|
temp.cal_status := defaults;
|
3226 |
|
|
temp.codvw_status := defaults;
|
3227 |
|
|
return temp;
|
3228 |
|
|
end function;
|
3229 |
|
|
|
3230 |
|
|
function defaults (dgrb_mmi : t_dgrb_mmi;
|
3231 |
|
|
ctrl_mmi : t_ctrl_mmi;
|
3232 |
|
|
pll_mmi : t_pll_mmi;
|
3233 |
|
|
rw_if_test : t_if_test_reg;
|
3234 |
|
|
USE_IRAM : std_logic;
|
3235 |
|
|
dqs_capture : natural;
|
3236 |
|
|
int_ac_1t : std_logic;
|
3237 |
|
|
trefi_failure : std_logic;
|
3238 |
|
|
iram_status : t_iram_stat;
|
3239 |
|
|
IRAM_AWIDTH : natural
|
3240 |
|
|
) return t_ro_regs is
|
3241 |
|
|
variable output : t_ro_regs;
|
3242 |
|
|
begin
|
3243 |
|
|
output := defaults;
|
3244 |
|
|
output.cal_status := defaults(ctrl_mmi, USE_IRAM, dqs_capture, int_ac_1t, trefi_failure, iram_status, IRAM_AWIDTH);
|
3245 |
|
|
output.codvw_status := defaults(dgrb_mmi);
|
3246 |
|
|
output.test_status := defaults(ctrl_mmi, pll_mmi, rw_if_test);
|
3247 |
|
|
return output;
|
3248 |
|
|
end function;
|
3249 |
|
|
|
3250 |
|
|
|
3251 |
|
|
-- >>>>>>>>>>>>>>>>>>>>>>>>
|
3252 |
|
|
-- Read / Write registers
|
3253 |
|
|
-- >>>>>>>>>>>>>>>>>>>>>>>>
|
3254 |
|
|
|
3255 |
|
|
-- ---------------------------------------------------------------
|
3256 |
|
|
-- mode register set A
|
3257 |
|
|
-- ---------------------------------------------------------------
|
3258 |
|
|
function defaults return t_mr_register_a is
|
3259 |
|
|
variable temp :t_mr_register_a;
|
3260 |
|
|
begin
|
3261 |
|
|
temp.mr0 := (others => '0');
|
3262 |
|
|
temp.mr1 := (others => '0');
|
3263 |
|
|
return temp;
|
3264 |
|
|
end function;
|
3265 |
|
|
|
3266 |
|
|
-- apply default mode register settings to register
|
3267 |
|
|
function defaults ( mr0 : in std_logic_vector;
|
3268 |
|
|
mr1 : in std_logic_vector
|
3269 |
|
|
) return t_mr_register_a is
|
3270 |
|
|
variable temp :t_mr_register_a;
|
3271 |
|
|
begin
|
3272 |
|
|
temp := defaults;
|
3273 |
|
|
temp.mr0 := mr0(temp.mr0'range);
|
3274 |
|
|
temp.mr1 := mr1(temp.mr1'range);
|
3275 |
|
|
return temp;
|
3276 |
|
|
end function;
|
3277 |
|
|
|
3278 |
|
|
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a is
|
3279 |
|
|
variable temp :t_mr_register_a;
|
3280 |
|
|
begin
|
3281 |
|
|
temp.mr0 := wdata_in(c_max_mode_reg_index -1 downto 0);
|
3282 |
|
|
temp.mr1 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
|
3283 |
|
|
return temp;
|
3284 |
|
|
end function;
|
3285 |
|
|
|
3286 |
|
|
function read (reg : in t_mr_register_a) return std_logic_vector is
|
3287 |
|
|
variable temp : std_logic_vector(31 downto 0) := (others => '0');
|
3288 |
|
|
begin
|
3289 |
|
|
temp(c_max_mode_reg_index -1 downto 0) := reg.mr0;
|
3290 |
|
|
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr1;
|
3291 |
|
|
return temp;
|
3292 |
|
|
end function;
|
3293 |
|
|
|
3294 |
|
|
-- ---------------------------------------------------------------
|
3295 |
|
|
-- mode register set B
|
3296 |
|
|
-- ---------------------------------------------------------------
|
3297 |
|
|
function defaults return t_mr_register_b is
|
3298 |
|
|
variable temp :t_mr_register_b;
|
3299 |
|
|
begin
|
3300 |
|
|
temp.mr2 := (others => '0');
|
3301 |
|
|
temp.mr3 := (others => '0');
|
3302 |
|
|
return temp;
|
3303 |
|
|
end function;
|
3304 |
|
|
|
3305 |
|
|
-- apply default mode register settings to register
|
3306 |
|
|
function defaults ( mr2 : in std_logic_vector;
|
3307 |
|
|
mr3 : in std_logic_vector
|
3308 |
|
|
) return t_mr_register_b is
|
3309 |
|
|
variable temp :t_mr_register_b;
|
3310 |
|
|
begin
|
3311 |
|
|
temp := defaults;
|
3312 |
|
|
temp.mr2 := mr2(temp.mr2'range);
|
3313 |
|
|
temp.mr3 := mr3(temp.mr3'range);
|
3314 |
|
|
return temp;
|
3315 |
|
|
end function;
|
3316 |
|
|
|
3317 |
|
|
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b is
|
3318 |
|
|
variable temp :t_mr_register_b;
|
3319 |
|
|
begin
|
3320 |
|
|
temp.mr2 := wdata_in(c_max_mode_reg_index -1 downto 0);
|
3321 |
|
|
temp.mr3 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
|
3322 |
|
|
return temp;
|
3323 |
|
|
end function;
|
3324 |
|
|
|
3325 |
|
|
function read (reg : in t_mr_register_b) return std_logic_vector is
|
3326 |
|
|
variable temp : std_logic_vector(31 downto 0) := (others => '0');
|
3327 |
|
|
begin
|
3328 |
|
|
temp(c_max_mode_reg_index -1 downto 0) := reg.mr2;
|
3329 |
|
|
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr3;
|
3330 |
|
|
return temp;
|
3331 |
|
|
end function;
|
3332 |
|
|
|
3333 |
|
|
|
3334 |
|
|
-- ---------------------------------------------------------------
|
3335 |
|
|
-- HL CSS (high level calibration state status)
|
3336 |
|
|
-- ---------------------------------------------------------------
|
3337 |
|
|
function defaults return t_hl_css is
|
3338 |
|
|
variable temp : t_hl_css;
|
3339 |
|
|
begin
|
3340 |
|
|
temp.hl_css := (others => '0');
|
3341 |
|
|
temp.cal_start := '0';
|
3342 |
|
|
return temp;
|
3343 |
|
|
end function;
|
3344 |
|
|
|
3345 |
|
|
function defaults ( C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
|
3346 |
|
|
) return t_hl_css is
|
3347 |
|
|
variable temp: t_hl_css;
|
3348 |
|
|
begin
|
3349 |
|
|
temp := defaults;
|
3350 |
|
|
temp.hl_css := temp.hl_css OR C_HL_STAGE_ENABLE;
|
3351 |
|
|
return temp;
|
3352 |
|
|
end function;
|
3353 |
|
|
|
3354 |
|
|
function read ( reg : in t_hl_css) return std_logic_vector is
|
3355 |
|
|
variable temp : std_logic_vector (31 downto 0) := (others => '0');
|
3356 |
|
|
begin
|
3357 |
|
|
temp(30 downto 30-c_hl_ccs_num_stages+1) := reg.hl_css;
|
3358 |
|
|
temp(0) := reg.cal_start;
|
3359 |
|
|
return temp;
|
3360 |
|
|
end function;
|
3361 |
|
|
|
3362 |
|
|
function write (wdata_in : std_logic_vector(31 downto 0) )return t_hl_css is
|
3363 |
|
|
variable reg : t_hl_css;
|
3364 |
|
|
begin
|
3365 |
|
|
reg.hl_css := wdata_in(30 downto 30-c_hl_ccs_num_stages+1);
|
3366 |
|
|
reg.cal_start := wdata_in(0);
|
3367 |
|
|
return reg;
|
3368 |
|
|
end function;
|
3369 |
|
|
|
3370 |
|
|
-- ---------------------------------------------------------------
|
3371 |
|
|
-- paramaterisation of sequencer through Avalon interface
|
3372 |
|
|
-- ---------------------------------------------------------------
|
3373 |
|
|
function defaults return t_parameterisation_reg_a is
|
3374 |
|
|
variable temp : t_parameterisation_reg_a;
|
3375 |
|
|
begin
|
3376 |
|
|
temp.nominal_poa_phase_lead := (others => '0');
|
3377 |
|
|
temp.maximum_poa_delay := (others => '0');
|
3378 |
|
|
temp.pll_360_sweeps := "0000";
|
3379 |
|
|
temp.num_phases_per_tck_pll := "0011";
|
3380 |
|
|
temp.nominal_dqs_delay := (others => '0');
|
3381 |
|
|
temp.extend_octrt_by := "0100";
|
3382 |
|
|
temp.delay_octrt_by := "0000";
|
3383 |
|
|
return temp;
|
3384 |
|
|
end function;
|
3385 |
|
|
|
3386 |
|
|
-- reset the paramterisation reg to given values
|
3387 |
|
|
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
|
3388 |
|
|
PLL_STEPS_PER_CYCLE : in natural;
|
3389 |
|
|
pll_360_sweeps : in natural
|
3390 |
|
|
) return t_parameterisation_reg_a is
|
3391 |
|
|
variable temp: t_parameterisation_reg_a;
|
3392 |
|
|
begin
|
3393 |
|
|
temp := defaults;
|
3394 |
|
|
temp.num_phases_per_tck_pll := std_logic_vector(to_unsigned(PLL_STEPS_PER_CYCLE /8 , temp.num_phases_per_tck_pll'high + 1 ));
|
3395 |
|
|
temp.pll_360_sweeps := std_logic_vector(to_unsigned(pll_360_sweeps , temp.pll_360_sweeps'high + 1 ));
|
3396 |
|
|
temp.nominal_dqs_delay := std_logic_vector(to_unsigned(NOM_DQS_PHASE_SETTING , temp.nominal_dqs_delay'high + 1 ));
|
3397 |
|
|
temp.extend_octrt_by := std_logic_vector(to_unsigned(5 , temp.extend_octrt_by'high + 1 ));
|
3398 |
|
|
temp.delay_octrt_by := std_logic_vector(to_unsigned(6 , temp.delay_octrt_by'high + 1 ));
|
3399 |
|
|
return temp;
|
3400 |
|
|
end function;
|
3401 |
|
|
|
3402 |
|
|
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector is
|
3403 |
|
|
variable temp : std_logic_vector (31 downto 0) := (others => '0');
|
3404 |
|
|
begin
|
3405 |
|
|
temp( 3 downto 0) := reg.pll_360_sweeps;
|
3406 |
|
|
temp( 7 downto 4) := reg.num_phases_per_tck_pll;
|
3407 |
|
|
temp(10 downto 8) := reg.nominal_dqs_delay;
|
3408 |
|
|
temp(19 downto 16) := reg.nominal_poa_phase_lead;
|
3409 |
|
|
temp(23 downto 20) := reg.maximum_poa_delay;
|
3410 |
|
|
temp(27 downto 24) := reg.extend_octrt_by;
|
3411 |
|
|
temp(31 downto 28) := reg.delay_octrt_by;
|
3412 |
|
|
return temp;
|
3413 |
|
|
end function;
|
3414 |
|
|
|
3415 |
|
|
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a is
|
3416 |
|
|
variable reg : t_parameterisation_reg_a;
|
3417 |
|
|
begin
|
3418 |
|
|
reg.pll_360_sweeps := wdata_in( 3 downto 0);
|
3419 |
|
|
reg.num_phases_per_tck_pll := wdata_in( 7 downto 4);
|
3420 |
|
|
reg.nominal_dqs_delay := wdata_in(10 downto 8);
|
3421 |
|
|
reg.nominal_poa_phase_lead := wdata_in(19 downto 16);
|
3422 |
|
|
reg.maximum_poa_delay := wdata_in(23 downto 20);
|
3423 |
|
|
reg.extend_octrt_by := wdata_in(27 downto 24);
|
3424 |
|
|
reg.delay_octrt_by := wdata_in(31 downto 28);
|
3425 |
|
|
return reg;
|
3426 |
|
|
end function;
|
3427 |
|
|
|
3428 |
|
|
-- ---------------------------------------------------------------
|
3429 |
|
|
-- t_if_test_reg - additional test support register
|
3430 |
|
|
-- ---------------------------------------------------------------
|
3431 |
|
|
function defaults return t_if_test_reg is
|
3432 |
|
|
variable temp : t_if_test_reg;
|
3433 |
|
|
begin
|
3434 |
|
|
temp.pll_phs_shft_phase_sel := 0;
|
3435 |
|
|
temp.pll_phs_shft_up_wc := '0';
|
3436 |
|
|
temp.pll_phs_shft_dn_wc := '0';
|
3437 |
|
|
temp.ac_1t_toggle := '0';
|
3438 |
|
|
temp.tracking_period_ms := "10000000"; -- 127 ms interval
|
3439 |
|
|
temp.tracking_units_are_10us := '0';
|
3440 |
|
|
return temp;
|
3441 |
|
|
end function;
|
3442 |
|
|
|
3443 |
|
|
-- reset the paramterisation reg to given values
|
3444 |
|
|
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
|
3445 |
|
|
) return t_if_test_reg is
|
3446 |
|
|
variable temp: t_if_test_reg;
|
3447 |
|
|
begin
|
3448 |
|
|
temp := defaults;
|
3449 |
|
|
temp.tracking_period_ms := std_logic_vector(to_unsigned(TRACKING_INTERVAL_IN_MS, temp.tracking_period_ms'length));
|
3450 |
|
|
return temp;
|
3451 |
|
|
end function;
|
3452 |
|
|
|
3453 |
|
|
function read ( reg : in t_if_test_reg) return std_logic_vector is
|
3454 |
|
|
variable temp : std_logic_vector (31 downto 0) := (others => '0');
|
3455 |
|
|
begin
|
3456 |
|
|
temp( 3 downto 0) := std_logic_vector(to_unsigned(reg.pll_phs_shft_phase_sel,4));
|
3457 |
|
|
temp(4) := reg.pll_phs_shft_up_wc;
|
3458 |
|
|
temp(5) := reg.pll_phs_shft_dn_wc;
|
3459 |
|
|
temp(16) := reg.ac_1t_toggle;
|
3460 |
|
|
temp(15 downto 8) := reg.tracking_period_ms;
|
3461 |
|
|
temp(20) := reg.tracking_units_are_10us;
|
3462 |
|
|
return temp;
|
3463 |
|
|
end function;
|
3464 |
|
|
|
3465 |
|
|
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg is
|
3466 |
|
|
variable reg : t_if_test_reg;
|
3467 |
|
|
begin
|
3468 |
|
|
reg.pll_phs_shft_phase_sel := to_integer(unsigned(wdata_in( 3 downto 0)));
|
3469 |
|
|
reg.pll_phs_shft_up_wc := wdata_in(4);
|
3470 |
|
|
reg.pll_phs_shft_dn_wc := wdata_in(5);
|
3471 |
|
|
reg.ac_1t_toggle := wdata_in(16);
|
3472 |
|
|
reg.tracking_period_ms := wdata_in(15 downto 8);
|
3473 |
|
|
reg.tracking_units_are_10us := wdata_in(20);
|
3474 |
|
|
return reg;
|
3475 |
|
|
end function;
|
3476 |
|
|
|
3477 |
|
|
procedure write_clear (signal reg : inout t_if_test_reg) is
|
3478 |
|
|
begin
|
3479 |
|
|
reg.ac_1t_toggle <= '0';
|
3480 |
|
|
reg.pll_phs_shft_up_wc <= '0';
|
3481 |
|
|
reg.pll_phs_shft_dn_wc <= '0';
|
3482 |
|
|
end procedure;
|
3483 |
|
|
|
3484 |
|
|
-- ---------------------------------------------------------------
|
3485 |
|
|
-- RW Regs, record of read/write register records (to simplify handling)
|
3486 |
|
|
-- ---------------------------------------------------------------
|
3487 |
|
|
function defaults return t_rw_regs is
|
3488 |
|
|
variable temp : t_rw_regs;
|
3489 |
|
|
begin
|
3490 |
|
|
temp.mr_reg_a := defaults;
|
3491 |
|
|
temp.mr_reg_b := defaults;
|
3492 |
|
|
temp.rw_hl_css := defaults;
|
3493 |
|
|
temp.rw_param_reg := defaults;
|
3494 |
|
|
temp.rw_if_test := defaults;
|
3495 |
|
|
return temp;
|
3496 |
|
|
end function;
|
3497 |
|
|
|
3498 |
|
|
function defaults(
|
3499 |
|
|
mr0 : in std_logic_vector;
|
3500 |
|
|
mr1 : in std_logic_vector;
|
3501 |
|
|
mr2 : in std_logic_vector;
|
3502 |
|
|
mr3 : in std_logic_vector;
|
3503 |
|
|
NOM_DQS_PHASE_SETTING : in natural;
|
3504 |
|
|
PLL_STEPS_PER_CYCLE : in natural;
|
3505 |
|
|
pll_360_sweeps : in natural;
|
3506 |
|
|
TRACKING_INTERVAL_IN_MS : in natural;
|
3507 |
|
|
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
|
3508 |
|
|
)return t_rw_regs is
|
3509 |
|
|
variable temp : t_rw_regs;
|
3510 |
|
|
begin
|
3511 |
|
|
temp := defaults;
|
3512 |
|
|
temp.mr_reg_a := defaults(mr0, mr1);
|
3513 |
|
|
temp.mr_reg_b := defaults(mr2, mr3);
|
3514 |
|
|
temp.rw_param_reg := defaults(NOM_DQS_PHASE_SETTING,
|
3515 |
|
|
PLL_STEPS_PER_CYCLE,
|
3516 |
|
|
pll_360_sweeps);
|
3517 |
|
|
temp.rw_if_test := defaults(TRACKING_INTERVAL_IN_MS);
|
3518 |
|
|
temp.rw_hl_css := defaults(C_HL_STAGE_ENABLE);
|
3519 |
|
|
return temp;
|
3520 |
|
|
end function;
|
3521 |
|
|
|
3522 |
|
|
procedure write_clear (signal regs : inout t_rw_regs) is
|
3523 |
|
|
begin
|
3524 |
|
|
write_clear(regs.rw_if_test);
|
3525 |
|
|
end procedure;
|
3526 |
|
|
|
3527 |
|
|
|
3528 |
|
|
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
|
3529 |
|
|
-- All mmi registers:
|
3530 |
|
|
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
|
3531 |
|
|
|
3532 |
|
|
function defaults return t_mmi_regs is
|
3533 |
|
|
variable v_mmi_regs : t_mmi_regs;
|
3534 |
|
|
begin
|
3535 |
|
|
v_mmi_regs.rw_regs := defaults;
|
3536 |
|
|
v_mmi_regs.ro_regs := defaults;
|
3537 |
|
|
v_mmi_regs.enable_writes := '0';
|
3538 |
|
|
return v_mmi_regs;
|
3539 |
|
|
end function;
|
3540 |
|
|
|
3541 |
|
|
function v_read (mmi_regs : in t_mmi_regs;
|
3542 |
|
|
address : in natural
|
3543 |
|
|
) return std_logic_vector is
|
3544 |
|
|
variable output : std_logic_vector(31 downto 0);
|
3545 |
|
|
begin
|
3546 |
|
|
|
3547 |
|
|
output := (others => '0');
|
3548 |
|
|
|
3549 |
|
|
case address is
|
3550 |
|
|
|
3551 |
|
|
-- status register
|
3552 |
|
|
when c_regofst_cal_status => output := read (mmi_regs.ro_regs.cal_status);
|
3553 |
|
|
|
3554 |
|
|
-- debug access register
|
3555 |
|
|
when c_regofst_debug_access =>
|
3556 |
|
|
if (mmi_regs.enable_writes = '1') then
|
3557 |
|
|
output := c_mmi_access_codeword;
|
3558 |
|
|
else
|
3559 |
|
|
output := (others => '0');
|
3560 |
|
|
end if;
|
3561 |
|
|
|
3562 |
|
|
-- test i/f to check which stages have acknowledged a command and pll checks
|
3563 |
|
|
when c_regofst_test_status => output := read(mmi_regs.ro_regs.test_status);
|
3564 |
|
|
|
3565 |
|
|
-- mode registers
|
3566 |
|
|
when c_regofst_mr_register_a => output := read(mmi_regs.rw_regs.mr_reg_a);
|
3567 |
|
|
when c_regofst_mr_register_b => output := read(mmi_regs.rw_regs.mr_reg_b);
|
3568 |
|
|
|
3569 |
|
|
-- codvw r/o status register
|
3570 |
|
|
when c_regofst_codvw_status => output := read(mmi_regs.ro_regs.codvw_status);
|
3571 |
|
|
|
3572 |
|
|
-- read/write registers
|
3573 |
|
|
when c_regofst_hl_css => output := read(mmi_regs.rw_regs.rw_hl_css);
|
3574 |
|
|
when c_regofst_if_param => output := read(mmi_regs.rw_regs.rw_param_reg);
|
3575 |
|
|
when c_regofst_if_test => output := read(mmi_regs.rw_regs.rw_if_test);
|
3576 |
|
|
|
3577 |
|
|
when others => report regs_report_prefix & "MMI registers detected an attempt to read to non-existant register location" severity warning;
|
3578 |
|
|
-- set illegal addr interrupt.
|
3579 |
|
|
end case;
|
3580 |
|
|
|
3581 |
|
|
return output;
|
3582 |
|
|
|
3583 |
|
|
end function;
|
3584 |
|
|
|
3585 |
|
|
|
3586 |
|
|
function read (signal mmi_regs : in t_mmi_regs;
|
3587 |
|
|
address : in natural
|
3588 |
|
|
) return std_logic_vector is
|
3589 |
|
|
variable output : std_logic_vector(31 downto 0);
|
3590 |
|
|
variable v_mmi_regs : t_mmi_regs;
|
3591 |
|
|
begin
|
3592 |
|
|
v_mmi_regs := mmi_regs;
|
3593 |
|
|
output := v_read(v_mmi_regs, address);
|
3594 |
|
|
return output;
|
3595 |
|
|
end function;
|
3596 |
|
|
|
3597 |
|
|
procedure write (mmi_regs : inout t_mmi_regs;
|
3598 |
|
|
address : in natural;
|
3599 |
|
|
wdata : in std_logic_vector(31 downto 0)) is
|
3600 |
|
|
|
3601 |
|
|
begin
|
3602 |
|
|
|
3603 |
|
|
-- intercept writes to codeword
|
3604 |
|
|
-- only service the writes normally if the codeword has been written sucsessfully:
|
3605 |
|
|
if address = c_regofst_debug_access then
|
3606 |
|
|
if wdata = c_mmi_access_codeword then
|
3607 |
|
|
mmi_regs.enable_writes := '1';
|
3608 |
|
|
else
|
3609 |
|
|
mmi_regs.enable_writes := '0';
|
3610 |
|
|
end if;
|
3611 |
|
|
|
3612 |
|
|
elsif mmi_regs.enable_writes = '1' then
|
3613 |
|
|
|
3614 |
|
|
case address is
|
3615 |
|
|
|
3616 |
|
|
-- read only registers
|
3617 |
|
|
when c_regofst_cal_status |
|
3618 |
|
|
c_regofst_codvw_status |
|
3619 |
|
|
c_regofst_test_status =>
|
3620 |
|
|
|
3621 |
|
|
report regs_report_prefix & "MMI registers detected an attempt to write to read only register number" & integer'image(address) severity failure;
|
3622 |
|
|
|
3623 |
|
|
-- debug access register
|
3624 |
|
|
when c_regofst_debug_access =>
|
3625 |
|
|
|
3626 |
|
|
null; -- already serviced
|
3627 |
|
|
|
3628 |
|
|
-- read/write registers
|
3629 |
|
|
when c_regofst_mr_register_a => mmi_regs.rw_regs.mr_reg_a := write(wdata);
|
3630 |
|
|
when c_regofst_mr_register_b => mmi_regs.rw_regs.mr_reg_b := write(wdata);
|
3631 |
|
|
when c_regofst_hl_css => mmi_regs.rw_regs.rw_hl_css := write(wdata);
|
3632 |
|
|
when c_regofst_if_param => mmi_regs.rw_regs.rw_param_reg := write(wdata);
|
3633 |
|
|
when c_regofst_if_test => mmi_regs.rw_regs.rw_if_test := write(wdata);
|
3634 |
|
|
|
3635 |
|
|
when others => -- set illegal addr interrupt.
|
3636 |
|
|
|
3637 |
|
|
report regs_report_prefix & "MMI registers detected an attempt to write to non existant register, with expected number" & integer'image(address) severity failure;
|
3638 |
|
|
|
3639 |
|
|
end case;
|
3640 |
|
|
|
3641 |
|
|
end if;
|
3642 |
|
|
|
3643 |
|
|
end procedure;
|
3644 |
|
|
|
3645 |
|
|
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
|
3646 |
|
|
-- the following functions enable register data to be communicated to other sequencer blocks
|
3647 |
|
|
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
|
3648 |
|
|
|
3649 |
|
|
function pack_record ( ip_regs : t_rw_regs
|
3650 |
|
|
) return t_algm_paramaterisation is
|
3651 |
|
|
variable output : t_algm_paramaterisation;
|
3652 |
|
|
begin
|
3653 |
|
|
-- default assignments
|
3654 |
|
|
output.num_phases_per_tck_pll := 16;
|
3655 |
|
|
output.pll_360_sweeps := 1;
|
3656 |
|
|
output.nominal_dqs_delay := 2;
|
3657 |
|
|
output.nominal_poa_phase_lead := 1;
|
3658 |
|
|
output.maximum_poa_delay := 5;
|
3659 |
|
|
output.odt_enabled := false;
|
3660 |
|
|
|
3661 |
|
|
output.num_phases_per_tck_pll := to_integer(unsigned(ip_regs.rw_param_reg.num_phases_per_tck_pll)) * 8;
|
3662 |
|
|
|
3663 |
|
|
case ip_regs.rw_param_reg.nominal_dqs_delay is
|
3664 |
|
|
when "010" => output.nominal_dqs_delay := 2;
|
3665 |
|
|
when "001" => output.nominal_dqs_delay := 1;
|
3666 |
|
|
when "000" => output.nominal_dqs_delay := 0;
|
3667 |
|
|
when "011" => output.nominal_dqs_delay := 3;
|
3668 |
|
|
when others => report regs_report_prefix &
|
3669 |
|
|
"there is a unsupported number of DQS taps (" &
|
3670 |
|
|
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_dqs_delay))) &
|
3671 |
|
|
") being advertised as the standard value" severity error;
|
3672 |
|
|
end case;
|
3673 |
|
|
|
3674 |
|
|
case ip_regs.rw_param_reg.nominal_poa_phase_lead is
|
3675 |
|
|
when "0001" => output.nominal_poa_phase_lead := 1;
|
3676 |
|
|
when "0010" => output.nominal_poa_phase_lead := 2;
|
3677 |
|
|
when "0011" => output.nominal_poa_phase_lead := 3;
|
3678 |
|
|
when "0000" => output.nominal_poa_phase_lead := 0;
|
3679 |
|
|
when others => report regs_report_prefix &
|
3680 |
|
|
"there is an unsupported nominal postamble phase lead paramater set (" &
|
3681 |
|
|
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_poa_phase_lead))) &
|
3682 |
|
|
")" severity error;
|
3683 |
|
|
end case;
|
3684 |
|
|
|
3685 |
|
|
if ( (ip_regs.mr_reg_a.mr1(2) = '1')
|
3686 |
|
|
or (ip_regs.mr_reg_a.mr1(6) = '1')
|
3687 |
|
|
or (ip_regs.mr_reg_a.mr1(9) = '1')
|
3688 |
|
|
) then
|
3689 |
|
|
output.odt_enabled := true;
|
3690 |
|
|
end if;
|
3691 |
|
|
|
3692 |
|
|
output.pll_360_sweeps := to_integer(unsigned(ip_regs.rw_param_reg.pll_360_sweeps));
|
3693 |
|
|
output.maximum_poa_delay := to_integer(unsigned(ip_regs.rw_param_reg.maximum_poa_delay));
|
3694 |
|
|
output.extend_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.extend_octrt_by));
|
3695 |
|
|
output.delay_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.delay_octrt_by));
|
3696 |
|
|
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
|
3697 |
|
|
return output;
|
3698 |
|
|
end function;
|
3699 |
|
|
|
3700 |
|
|
|
3701 |
|
|
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig is
|
3702 |
|
|
variable output : t_mmi_pll_reconfig;
|
3703 |
|
|
begin
|
3704 |
|
|
output.pll_phs_shft_phase_sel := ip_regs.rw_if_test.pll_phs_shft_phase_sel;
|
3705 |
|
|
output.pll_phs_shft_up_wc := ip_regs.rw_if_test.pll_phs_shft_up_wc;
|
3706 |
|
|
output.pll_phs_shft_dn_wc := ip_regs.rw_if_test.pll_phs_shft_dn_wc;
|
3707 |
|
|
return output;
|
3708 |
|
|
end function;
|
3709 |
|
|
|
3710 |
|
|
|
3711 |
|
|
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl is
|
3712 |
|
|
variable output : t_admin_ctrl := defaults;
|
3713 |
|
|
begin
|
3714 |
|
|
output.mr0 := ip_regs.mr_reg_a.mr0;
|
3715 |
|
|
output.mr1 := ip_regs.mr_reg_a.mr1;
|
3716 |
|
|
output.mr2 := ip_regs.mr_reg_b.mr2;
|
3717 |
|
|
output.mr3 := ip_regs.mr_reg_b.mr3;
|
3718 |
|
|
return output;
|
3719 |
|
|
end function;
|
3720 |
|
|
|
3721 |
|
|
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl is
|
3722 |
|
|
variable output : t_mmi_ctrl := defaults;
|
3723 |
|
|
begin
|
3724 |
|
|
output.hl_css := to_t_hl_css_reg (ip_regs.rw_hl_css);
|
3725 |
|
|
output.calibration_start := ip_regs.rw_hl_css.cal_start;
|
3726 |
|
|
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
|
3727 |
|
|
output.tracking_orvd_to_10ms := ip_regs.rw_if_test.tracking_units_are_10us;
|
3728 |
|
|
return output;
|
3729 |
|
|
end function;
|
3730 |
|
|
|
3731 |
|
|
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
|
3732 |
|
|
-- Helper functions :
|
3733 |
|
|
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
|
3734 |
|
|
|
3735 |
|
|
function to_t_hl_css_reg (hl_css : t_hl_css
|
3736 |
|
|
) return t_hl_css_reg is
|
3737 |
|
|
variable output : t_hl_css_reg := defaults;
|
3738 |
|
|
begin
|
3739 |
|
|
|
3740 |
|
|
output.phy_initialise_dis := hl_css.hl_css(c_hl_css_reg_phy_initialise_dis_bit);
|
3741 |
|
|
output.init_dram_dis := hl_css.hl_css(c_hl_css_reg_init_dram_dis_bit);
|
3742 |
|
|
output.write_ihi_dis := hl_css.hl_css(c_hl_css_reg_write_ihi_dis_bit);
|
3743 |
|
|
output.cal_dis := hl_css.hl_css(c_hl_css_reg_cal_dis_bit);
|
3744 |
|
|
output.write_btp_dis := hl_css.hl_css(c_hl_css_reg_write_btp_dis_bit);
|
3745 |
|
|
output.write_mtp_dis := hl_css.hl_css(c_hl_css_reg_write_mtp_dis_bit);
|
3746 |
|
|
output.read_mtp_dis := hl_css.hl_css(c_hl_css_reg_read_mtp_dis_bit);
|
3747 |
|
|
output.rrp_reset_dis := hl_css.hl_css(c_hl_css_reg_rrp_reset_dis_bit);
|
3748 |
|
|
output.rrp_sweep_dis := hl_css.hl_css(c_hl_css_reg_rrp_sweep_dis_bit);
|
3749 |
|
|
output.rrp_seek_dis := hl_css.hl_css(c_hl_css_reg_rrp_seek_dis_bit);
|
3750 |
|
|
output.rdv_dis := hl_css.hl_css(c_hl_css_reg_rdv_dis_bit);
|
3751 |
|
|
output.poa_dis := hl_css.hl_css(c_hl_css_reg_poa_dis_bit);
|
3752 |
|
|
output.was_dis := hl_css.hl_css(c_hl_css_reg_was_dis_bit);
|
3753 |
|
|
output.adv_rd_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_rd_lat_dis_bit);
|
3754 |
|
|
output.adv_wr_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_wr_lat_dis_bit);
|
3755 |
|
|
output.prep_customer_mr_setup_dis := hl_css.hl_css(c_hl_css_reg_prep_customer_mr_setup_dis_bit);
|
3756 |
|
|
output.tracking_dis := hl_css.hl_css(c_hl_css_reg_tracking_dis_bit);
|
3757 |
|
|
return output;
|
3758 |
|
|
end function;
|
3759 |
|
|
|
3760 |
|
|
-- pack the ack seen record element into a std_logic_vector
|
3761 |
|
|
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
|
3762 |
|
|
) return std_logic_vector is
|
3763 |
|
|
variable v_output: std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
|
3764 |
|
|
variable v_start : natural range 0 to c_hl_ccs_num_stages-1;
|
3765 |
|
|
begin
|
3766 |
|
|
v_output := (others => '0');
|
3767 |
|
|
|
3768 |
|
|
v_output(c_hl_css_reg_cal_dis_bit ) := cal_stage_ack_seen.cal;
|
3769 |
|
|
v_output(c_hl_css_reg_phy_initialise_dis_bit ) := cal_stage_ack_seen.phy_initialise;
|
3770 |
|
|
v_output(c_hl_css_reg_init_dram_dis_bit ) := cal_stage_ack_seen.init_dram;
|
3771 |
|
|
v_output(c_hl_css_reg_write_ihi_dis_bit ) := cal_stage_ack_seen.write_ihi;
|
3772 |
|
|
v_output(c_hl_css_reg_write_btp_dis_bit ) := cal_stage_ack_seen.write_btp;
|
3773 |
|
|
v_output(c_hl_css_reg_write_mtp_dis_bit ) := cal_stage_ack_seen.write_mtp;
|
3774 |
|
|
v_output(c_hl_css_reg_read_mtp_dis_bit ) := cal_stage_ack_seen.read_mtp;
|
3775 |
|
|
v_output(c_hl_css_reg_rrp_reset_dis_bit ) := cal_stage_ack_seen.rrp_reset;
|
3776 |
|
|
v_output(c_hl_css_reg_rrp_sweep_dis_bit ) := cal_stage_ack_seen.rrp_sweep;
|
3777 |
|
|
v_output(c_hl_css_reg_rrp_seek_dis_bit ) := cal_stage_ack_seen.rrp_seek;
|
3778 |
|
|
v_output(c_hl_css_reg_rdv_dis_bit ) := cal_stage_ack_seen.rdv;
|
3779 |
|
|
v_output(c_hl_css_reg_poa_dis_bit ) := cal_stage_ack_seen.poa;
|
3780 |
|
|
v_output(c_hl_css_reg_was_dis_bit ) := cal_stage_ack_seen.was;
|
3781 |
|
|
v_output(c_hl_css_reg_adv_rd_lat_dis_bit ) := cal_stage_ack_seen.adv_rd_lat;
|
3782 |
|
|
v_output(c_hl_css_reg_adv_wr_lat_dis_bit ) := cal_stage_ack_seen.adv_wr_lat;
|
3783 |
|
|
v_output(c_hl_css_reg_prep_customer_mr_setup_dis_bit) := cal_stage_ack_seen.prep_customer_mr_setup;
|
3784 |
|
|
v_output(c_hl_css_reg_tracking_dis_bit ) := cal_stage_ack_seen.tracking_setup;
|
3785 |
|
|
|
3786 |
|
|
return v_output;
|
3787 |
|
|
|
3788 |
|
|
end function;
|
3789 |
|
|
|
3790 |
|
|
-- reg encoding of current stage
|
3791 |
|
|
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id
|
3792 |
|
|
) return std_logic_vector is
|
3793 |
|
|
variable output : std_logic_vector(7 downto 0);
|
3794 |
|
|
begin
|
3795 |
|
|
|
3796 |
|
|
case ctrl_cmd_id is
|
3797 |
|
|
|
3798 |
|
|
when cmd_idle => output := X"00";
|
3799 |
|
|
when cmd_phy_initialise => output := X"01";
|
3800 |
|
|
when cmd_init_dram => output := X"02";
|
3801 |
|
|
when cmd_write_ihi => output := X"03";
|
3802 |
|
|
when cmd_write_btp => output := X"04";
|
3803 |
|
|
when cmd_write_mtp => output := X"05";
|
3804 |
|
|
when cmd_read_mtp => output := X"06";
|
3805 |
|
|
when cmd_rrp_reset => output := X"07";
|
3806 |
|
|
when cmd_rrp_sweep => output := X"08";
|
3807 |
|
|
when cmd_rrp_seek => output := X"09";
|
3808 |
|
|
when cmd_rdv => output := X"0A";
|
3809 |
|
|
when cmd_poa => output := X"0B";
|
3810 |
|
|
when cmd_was => output := X"0C";
|
3811 |
|
|
when cmd_prep_adv_rd_lat => output := X"0D";
|
3812 |
|
|
when cmd_prep_adv_wr_lat => output := X"0E";
|
3813 |
|
|
when cmd_prep_customer_mr_setup => output := X"0F";
|
3814 |
|
|
when cmd_tr_due => output := X"10";
|
3815 |
|
|
|
3816 |
|
|
when others =>
|
3817 |
|
|
null;
|
3818 |
|
|
report regs_report_prefix & "unknown cal command (" & t_ctrl_cmd_id'image(ctrl_cmd_id) & ") seen in encode_current_stage function" severity failure;
|
3819 |
|
|
|
3820 |
|
|
end case;
|
3821 |
|
|
|
3822 |
|
|
return output;
|
3823 |
|
|
|
3824 |
|
|
end function;
|
3825 |
|
|
|
3826 |
|
|
-- reg encoding of current active block
|
3827 |
|
|
function encode_active_block (active_block : t_ctrl_active_block
|
3828 |
|
|
) return std_logic_vector is
|
3829 |
|
|
variable output : std_logic_vector(3 downto 0);
|
3830 |
|
|
begin
|
3831 |
|
|
|
3832 |
|
|
case active_block is
|
3833 |
|
|
|
3834 |
|
|
when idle => output := X"0";
|
3835 |
|
|
when admin => output := X"1";
|
3836 |
|
|
when dgwb => output := X"2";
|
3837 |
|
|
when dgrb => output := X"3";
|
3838 |
|
|
when proc => output := X"4";
|
3839 |
|
|
when setup => output := X"5";
|
3840 |
|
|
when iram => output := X"6";
|
3841 |
|
|
|
3842 |
|
|
when others =>
|
3843 |
|
|
output := X"7";
|
3844 |
|
|
report regs_report_prefix & "unknown active_block seen in encode_active_block function" severity failure;
|
3845 |
|
|
|
3846 |
|
|
end case;
|
3847 |
|
|
|
3848 |
|
|
return output;
|
3849 |
|
|
|
3850 |
|
|
end function;
|
3851 |
|
|
|
3852 |
|
|
--
|
3853 |
|
|
end altera_ddr_phy_alt_mem_phy_regs_pkg;
|
3854 |
|
|
--
|
3855 |
|
|
|
3856 |
|
|
-- -----------------------------------------------------------------------------
|
3857 |
|
|
-- Abstract : mmi block for the non-levelling AFI PHY sequencer
|
3858 |
|
|
-- This is an optional block with an Avalon interface and status
|
3859 |
|
|
-- register instantiations to enhance the debug capabilities of
|
3860 |
|
|
-- the sequencer. The format of the block is:
|
3861 |
|
|
-- a) an Avalon interface which supports different avalon and
|
3862 |
|
|
-- sequencer clock sources
|
3863 |
|
|
-- b) mmi status registers (which hold information about the
|
3864 |
|
|
-- successof the calibration)
|
3865 |
|
|
-- c) a read interface to the iram to enable debug through the
|
3866 |
|
|
-- avalon interface.
|
3867 |
|
|
-- -----------------------------------------------------------------------------
|
3868 |
|
|
|
3869 |
|
|
library ieee;
|
3870 |
|
|
use ieee.std_logic_1164.all;
|
3871 |
|
|
use ieee.numeric_std.all;
|
3872 |
|
|
|
3873 |
|
|
library work;
|
3874 |
|
|
|
3875 |
|
|
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
|
3876 |
|
|
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
|
3877 |
|
|
-- for the stages of DRAM memory calibration.
|
3878 |
|
|
--
|
3879 |
|
|
use work.altera_ddr_phy_alt_mem_phy_record_pkg.all;
|
3880 |
|
|
|
3881 |
|
|
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
|
3882 |
|
|
-- registers for the mmi status registers and functions/procedures applied to the registers
|
3883 |
|
|
--
|
3884 |
|
|
use work.altera_ddr_phy_alt_mem_phy_regs_pkg.all;
|
3885 |
|
|
|
3886 |
|
|
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
|
3887 |
|
|
-- for iram writes during calibration
|
3888 |
|
|
--
|
3889 |
|
|
use work.altera_ddr_phy_alt_mem_phy_iram_addr_pkg.all;
|
3890 |
|
|
|
3891 |
|
|
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
|
3892 |
|
|
-- thoughout the sequencer and will not change (for constants which may change between sequencer
|
3893 |
|
|
-- instances generics are used)
|
3894 |
|
|
--
|
3895 |
|
|
use work.altera_ddr_phy_alt_mem_phy_constants_pkg.all;
|
3896 |
|
|
|
3897 |
|
|
--
|
3898 |
|
|
entity altera_ddr_phy_alt_mem_phy_mmi is
|
3899 |
|
|
generic (
|
3900 |
|
|
-- physical interface width definitions
|
3901 |
|
|
MEM_IF_DQS_WIDTH : natural := 9;
|
3902 |
|
|
MEM_IF_DWIDTH : natural := 72;
|
3903 |
|
|
MEM_IF_DM_WIDTH : natural := 9;
|
3904 |
|
|
MEM_IF_DQ_PER_DQS : natural := 8;
|
3905 |
|
|
MEM_IF_DQS_CAPTURE : natural := 1;
|
3906 |
|
|
DWIDTH_RATIO : natural := 4;
|
3907 |
|
|
CLOCK_INDEX_WIDTH : natural := 4;
|
3908 |
|
|
MEM_IF_CLK_PAIR_COUNT : natural := 3;
|
3909 |
|
|
MEM_IF_ADDR_WIDTH : natural := 13;
|
3910 |
|
|
MEM_IF_BANKADDR_WIDTH : natural := 3;
|
3911 |
|
|
MEM_IF_NUM_RANKS : natural := 1;
|
3912 |
|
|
ADV_LAT_WIDTH : natural := 5;
|
3913 |
|
|
RESYNCHRONISE_AVALON_DBG : natural := 0;
|
3914 |
|
|
AV_IF_ADDR_WIDTH : natural := 13;
|
3915 |
|
|
MEM_IF_MEMTYPE : string := "DDR2";
|
3916 |
|
|
|
3917 |
|
|
-- setup / algorithm information
|
3918 |
|
|
NOM_DQS_PHASE_SETTING : natural := 2;
|
3919 |
|
|
SCAN_CLK_DIVIDE_BY : natural := 2;
|
3920 |
|
|
RDP_ADDR_WIDTH : natural := 4;
|
3921 |
|
|
PLL_STEPS_PER_CYCLE : natural := 16;
|
3922 |
|
|
IOE_PHASES_PER_TCK : natural := 8;
|
3923 |
|
|
IOE_DELAYS_PER_PHS : natural := 5;
|
3924 |
|
|
MEM_IF_CLK_PS : natural := 2500;
|
3925 |
|
|
|
3926 |
|
|
-- initial mode register settings
|
3927 |
|
|
PHY_DEF_MR_1ST : std_logic_vector(15 downto 0) := "0000000000000000";
|
3928 |
|
|
PHY_DEF_MR_2ND : std_logic_vector(15 downto 0) := "0000000000000000";
|
3929 |
|
|
PHY_DEF_MR_3RD : std_logic_vector(15 downto 0) := "0000000000000000";
|
3930 |
|
|
PHY_DEF_MR_4TH : std_logic_vector(15 downto 0) := "0000000000000000";
|
3931 |
|
|
|
3932 |
|
|
SNOOP_MRS : natural := 0; -- observe customer mode register settings
|
3933 |
|
|
PRESET_RLAT : natural := 0; -- read latency preset value
|
3934 |
|
|
CAPABILITIES : natural := 0; -- sequencer capabilities flags
|
3935 |
|
|
|
3936 |
|
|
USE_IRAM : std_logic := '1'; -- RFU : default '1'
|
3937 |
|
|
|
3938 |
|
|
IRAM_AWIDTH : natural := 2;
|
3939 |
|
|
TRACKING_INTERVAL_IN_MS : natural := 128;
|
3940 |
|
|
|
3941 |
|
|
READ_LAT_WIDTH : natural := 6
|
3942 |
|
|
);
|
3943 |
|
|
port (
|
3944 |
|
|
-- clk / reset
|
3945 |
|
|
clk : in std_logic;
|
3946 |
|
|
rst_n : in std_logic;
|
3947 |
|
|
|
3948 |
|
|
--synchronous Avalon debug interface (internally re-synchronised to input clock)
|
3949 |
|
|
dbg_seq_clk : in std_logic;
|
3950 |
|
|
dbg_seq_rst_n : in std_logic;
|
3951 |
|
|
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH -1 downto 0);
|
3952 |
|
|
dbg_seq_wr : in std_logic;
|
3953 |
|
|
dbg_seq_rd : in std_logic;
|
3954 |
|
|
dbg_seq_cs : in std_logic;
|
3955 |
|
|
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
|
3956 |
|
|
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
|
3957 |
|
|
seq_dbg_waitrequest : out std_logic;
|
3958 |
|
|
|
3959 |
|
|
-- mmi to admin interface
|
3960 |
|
|
regs_admin_ctrl : out t_admin_ctrl;
|
3961 |
|
|
admin_regs_status : in t_admin_stat;
|
3962 |
|
|
trefi_failure : in std_logic;
|
3963 |
|
|
|
3964 |
|
|
-- mmi to scan chain interface (unused)
|
3965 |
|
|
regs_sc_ctrl : out t_sc_ctrl_if;
|
3966 |
|
|
sc_regs_status : in t_sc_stat;
|
3967 |
|
|
|
3968 |
|
|
-- mmi to iram interface
|
3969 |
|
|
mmi_iram : out t_iram_ctrl;
|
3970 |
|
|
mmi_iram_enable_writes : out std_logic;
|
3971 |
|
|
|
3972 |
|
|
iram_status : in t_iram_stat;
|
3973 |
|
|
|
3974 |
|
|
-- mmi to control interface
|
3975 |
|
|
mmi_ctrl : out t_mmi_ctrl;
|
3976 |
|
|
ctrl_mmi : in t_ctrl_mmi;
|
3977 |
|
|
int_ac_1t : in std_logic;
|
3978 |
|
|
invert_ac_1t : out std_logic;
|
3979 |
|
|
|
3980 |
|
|
-- global parameterisation record
|
3981 |
|
|
parameterisation_rec : out t_algm_paramaterisation;
|
3982 |
|
|
|
3983 |
|
|
-- mmi pll interface
|
3984 |
|
|
pll_mmi : in t_pll_mmi;
|
3985 |
|
|
mmi_pll : out t_mmi_pll_reconfig;
|
3986 |
|
|
|
3987 |
|
|
-- codvw status signals
|
3988 |
|
|
dgrb_mmi : in t_dgrb_mmi
|
3989 |
|
|
);
|
3990 |
|
|
end entity;
|
3991 |
|
|
|
3992 |
|
|
--
|
3993 |
|
|
architecture struct of altera_ddr_phy_alt_mem_phy_mmi IS
|
3994 |
|
|
|
3995 |
|
|
-- maximum function
|
3996 |
|
|
function max (a, b : natural) return natural is
|
3997 |
|
|
begin
|
3998 |
|
|
if a > b then
|
3999 |
|
|
return a;
|
4000 |
|
|
else
|
4001 |
|
|
return b;
|
4002 |
|
|
end if;
|
4003 |
|
|
end function;
|
4004 |
|
|
|
4005 |
|
|
-- -------------------------------------------
|
4006 |
|
|
-- constant definitions
|
4007 |
|
|
-- -------------------------------------------
|
4008 |
|
|
|
4009 |
|
|
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE);
|
4010 |
|
|
|
4011 |
|
|
constant c_response_lat : natural := 6;
|
4012 |
|
|
constant c_codeword : std_logic_vector(31 downto 0) := c_mmi_access_codeword;
|
4013 |
|
|
constant c_int_iram_start_size : natural := max(IRAM_AWIDTH, 4);
|
4014 |
|
|
|
4015 |
|
|
-- enable for ctrl state machine states
|
4016 |
|
|
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(CAPABILITIES, 32));
|
4017 |
|
|
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
|
4018 |
|
|
|
4019 |
|
|
-- a prefix for all report signals to identify phy and sequencer block
|
4020 |
|
|
--
|
4021 |
|
|
constant mmi_report_prefix : string := "altera_ddr_phy_alt_mem_phy_seq (mmi) : ";
|
4022 |
|
|
|
4023 |
|
|
-- --------------------------------------------
|
4024 |
|
|
-- internal signals
|
4025 |
|
|
-- --------------------------------------------
|
4026 |
|
|
|
4027 |
|
|
-- internal clock domain register interface signals
|
4028 |
|
|
signal int_wdata : std_logic_vector(31 downto 0);
|
4029 |
|
|
signal int_rdata : std_logic_vector(31 downto 0);
|
4030 |
|
|
signal int_address : std_logic_vector(AV_IF_ADDR_WIDTH-1 downto 0);
|
4031 |
|
|
signal int_read : std_logic;
|
4032 |
|
|
signal int_cs : std_logic;
|
4033 |
|
|
signal int_write : std_logic;
|
4034 |
|
|
signal waitreq_int : std_logic;
|
4035 |
|
|
|
4036 |
|
|
-- register storage
|
4037 |
|
|
-- contains:
|
4038 |
|
|
-- read only (ro_regs)
|
4039 |
|
|
-- read/write (rw_regs)
|
4040 |
|
|
-- enable_writes flag
|
4041 |
|
|
signal mmi_regs : t_mmi_regs := defaults;
|
4042 |
|
|
signal mmi_rw_regs_initialised : std_logic;
|
4043 |
|
|
|
4044 |
|
|
-- this counter ensures that the mmi waits for c_response_lat clocks before
|
4045 |
|
|
-- responding to a new Avalon request
|
4046 |
|
|
signal waitreq_count : natural range 0 to 15;
|
4047 |
|
|
signal waitreq_count_is_zero : std_logic;
|
4048 |
|
|
|
4049 |
|
|
-- register error signals
|
4050 |
|
|
signal int_ac_1t_r : std_logic;
|
4051 |
|
|
signal trefi_failure_r : std_logic;
|
4052 |
|
|
|
4053 |
|
|
-- iram ready - calibration complete and USE_IRAM high
|
4054 |
|
|
signal iram_ready : std_logic;
|
4055 |
|
|
|
4056 |
|
|
begin -- architecture struct
|
4057 |
|
|
|
4058 |
|
|
-- the following signals are reserved for future use
|
4059 |
|
|
regs_sc_ctrl <= defaults;
|
4060 |
|
|
invert_ac_1t <= '0';
|
4061 |
|
|
|
4062 |
|
|
|
4063 |
|
|
-- --------------------------------------------------------------
|
4064 |
|
|
-- generate for synchronous avalon interface
|
4065 |
|
|
-- --------------------------------------------------------------
|
4066 |
|
|
simply_registered_avalon : if RESYNCHRONISE_AVALON_DBG = 0 generate
|
4067 |
|
|
begin
|
4068 |
|
|
|
4069 |
|
|
process (rst_n, clk)
|
4070 |
|
|
begin
|
4071 |
|
|
if rst_n = '0' then
|
4072 |
|
|
int_wdata <= (others => '0');
|
4073 |
|
|
int_address <= (others => '0');
|
4074 |
|
|
int_read <= '0';
|
4075 |
|
|
int_write <= '0';
|
4076 |
|
|
int_cs <= '0';
|
4077 |
|
|
elsif rising_edge(clk) then
|
4078 |
|
|
int_wdata <= dbg_seq_wr_data;
|
4079 |
|
|
int_address <= dbg_seq_addr;
|
4080 |
|
|
int_read <= dbg_seq_rd;
|
4081 |
|
|
int_write <= dbg_seq_wr;
|
4082 |
|
|
int_cs <= dbg_seq_cs;
|
4083 |
|
|
end if;
|
4084 |
|
|
end process;
|
4085 |
|
|
|
4086 |
|
|
seq_dbg_rd_data <= int_rdata;
|
4087 |
|
|
seq_dbg_waitrequest <= waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
|
4088 |
|
|
|
4089 |
|
|
end generate simply_registered_avalon;
|
4090 |
|
|
|
4091 |
|
|
-- --------------------------------------------------------------
|
4092 |
|
|
-- clock domain crossing for asynchronous mmi interface
|
4093 |
|
|
-- --------------------------------------------------------------
|
4094 |
|
|
re_synchronise_avalon : if RESYNCHRONISE_AVALON_DBG = 1 generate
|
4095 |
|
|
|
4096 |
|
|
--clock domain crossing signals
|
4097 |
|
|
signal ccd_new_cmd : std_logic;
|
4098 |
|
|
signal ccd_new_cmd_ack : std_logic;
|
4099 |
|
|
signal ccd_cmd_done : std_logic;
|
4100 |
|
|
signal ccd_cmd_done_ack : std_logic;
|
4101 |
|
|
signal ccd_rd_data : std_logic_vector(dbg_seq_wr_data'range);
|
4102 |
|
|
|
4103 |
|
|
signal ccd_cmd_done_ack_t : std_logic;
|
4104 |
|
|
signal ccd_cmd_done_ack_2t : std_logic;
|
4105 |
|
|
signal ccd_cmd_done_ack_3t : std_logic;
|
4106 |
|
|
signal ccd_cmd_done_t : std_logic;
|
4107 |
|
|
signal ccd_cmd_done_2t : std_logic;
|
4108 |
|
|
signal ccd_cmd_done_3t : std_logic;
|
4109 |
|
|
|
4110 |
|
|
signal ccd_new_cmd_t : std_logic;
|
4111 |
|
|
signal ccd_new_cmd_2t : std_logic;
|
4112 |
|
|
signal ccd_new_cmd_3t : std_logic;
|
4113 |
|
|
signal ccd_new_cmd_ack_t : std_logic;
|
4114 |
|
|
signal ccd_new_cmd_ack_2t : std_logic;
|
4115 |
|
|
signal ccd_new_cmd_ack_3t : std_logic;
|
4116 |
|
|
|
4117 |
|
|
signal cmd_pending : std_logic;
|
4118 |
|
|
|
4119 |
|
|
signal seq_clk_waitreq_int : std_logic;
|
4120 |
|
|
|
4121 |
|
|
begin
|
4122 |
|
|
|
4123 |
|
|
process (rst_n, clk)
|
4124 |
|
|
begin
|
4125 |
|
|
if rst_n = '0' then
|
4126 |
|
|
int_wdata <= (others => '0');
|
4127 |
|
|
int_address <= (others => '0');
|
4128 |
|
|
int_read <= '0';
|
4129 |
|
|
int_write <= '0';
|
4130 |
|
|
int_cs <= '0';
|
4131 |
|
|
ccd_new_cmd_ack <= '0';
|
4132 |
|
|
ccd_new_cmd_t <= '0';
|
4133 |
|
|
ccd_new_cmd_2t <= '0';
|
4134 |
|
|
ccd_new_cmd_3t <= '0';
|
4135 |
|
|
elsif rising_edge(clk) then
|
4136 |
|
|
|
4137 |
|
|
ccd_new_cmd_t <= ccd_new_cmd;
|
4138 |
|
|
ccd_new_cmd_2t <= ccd_new_cmd_t;
|
4139 |
|
|
ccd_new_cmd_3t <= ccd_new_cmd_2t;
|
4140 |
|
|
|
4141 |
|
|
if ccd_new_cmd_3t = '0' and ccd_new_cmd_2t = '1' then
|
4142 |
|
|
int_wdata <= dbg_seq_wr_data;
|
4143 |
|
|
int_address <= dbg_seq_addr;
|
4144 |
|
|
int_read <= dbg_seq_rd;
|
4145 |
|
|
int_write <= dbg_seq_wr;
|
4146 |
|
|
int_cs <= '1';
|
4147 |
|
|
ccd_new_cmd_ack <= '1';
|
4148 |
|
|
|
4149 |
|
|
elsif ccd_new_cmd_3t = '1' and ccd_new_cmd_2t = '0' then
|
4150 |
|
|
ccd_new_cmd_ack <= '0';
|
4151 |
|
|
end if;
|
4152 |
|
|
|
4153 |
|
|
if int_cs = '1' and waitreq_int= '0' then
|
4154 |
|
|
int_cs <= '0';
|
4155 |
|
|
int_read <= '0';
|
4156 |
|
|
int_write <= '0';
|
4157 |
|
|
end if;
|
4158 |
|
|
end if;
|
4159 |
|
|
|
4160 |
|
|
end process;
|
4161 |
|
|
|
4162 |
|
|
-- process to generate new cmd
|
4163 |
|
|
process (dbg_seq_rst_n, dbg_seq_clk)
|
4164 |
|
|
begin
|
4165 |
|
|
if dbg_seq_rst_n = '0' then
|
4166 |
|
|
ccd_new_cmd <= '0';
|
4167 |
|
|
ccd_new_cmd_ack_t <= '0';
|
4168 |
|
|
ccd_new_cmd_ack_2t <= '0';
|
4169 |
|
|
ccd_new_cmd_ack_3t <= '0';
|
4170 |
|
|
cmd_pending <= '0';
|
4171 |
|
|
elsif rising_edge(dbg_seq_clk) then
|
4172 |
|
|
|
4173 |
|
|
ccd_new_cmd_ack_t <= ccd_new_cmd_ack;
|
4174 |
|
|
ccd_new_cmd_ack_2t <= ccd_new_cmd_ack_t;
|
4175 |
|
|
ccd_new_cmd_ack_3t <= ccd_new_cmd_ack_2t;
|
4176 |
|
|
|
4177 |
|
|
if ccd_new_cmd = '0' and dbg_seq_cs = '1' and cmd_pending = '0' then
|
4178 |
|
|
ccd_new_cmd <= '1';
|
4179 |
|
|
cmd_pending <= '1';
|
4180 |
|
|
elsif ccd_new_cmd_ack_2t = '1' and ccd_new_cmd_ack_3t = '0' then
|
4181 |
|
|
ccd_new_cmd <= '0';
|
4182 |
|
|
end if;
|
4183 |
|
|
|
4184 |
|
|
-- use falling edge of cmd_done
|
4185 |
|
|
if cmd_pending = '1' and ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
|
4186 |
|
|
cmd_pending <= '0';
|
4187 |
|
|
end if;
|
4188 |
|
|
end if;
|
4189 |
|
|
end process;
|
4190 |
|
|
|
4191 |
|
|
|
4192 |
|
|
-- process to take read data back and transfer it across the clock domains
|
4193 |
|
|
process (rst_n, clk)
|
4194 |
|
|
begin
|
4195 |
|
|
if rst_n = '0' then
|
4196 |
|
|
ccd_cmd_done <= '0';
|
4197 |
|
|
ccd_rd_data <= (others => '0');
|
4198 |
|
|
ccd_cmd_done_ack_3t <= '0';
|
4199 |
|
|
ccd_cmd_done_ack_2t <= '0';
|
4200 |
|
|
ccd_cmd_done_ack_t <= '0';
|
4201 |
|
|
|
4202 |
|
|
elsif rising_edge(clk) then
|
4203 |
|
|
|
4204 |
|
|
if ccd_cmd_done_ack_2t = '1' and ccd_cmd_done_ack_3t = '0' then
|
4205 |
|
|
ccd_cmd_done <= '0';
|
4206 |
|
|
elsif waitreq_int = '0' then
|
4207 |
|
|
ccd_cmd_done <= '1';
|
4208 |
|
|
ccd_rd_data <= int_rdata;
|
4209 |
|
|
end if;
|
4210 |
|
|
|
4211 |
|
|
ccd_cmd_done_ack_3t <= ccd_cmd_done_ack_2t;
|
4212 |
|
|
ccd_cmd_done_ack_2t <= ccd_cmd_done_ack_t;
|
4213 |
|
|
ccd_cmd_done_ack_t <= ccd_cmd_done_ack;
|
4214 |
|
|
end if;
|
4215 |
|
|
end process;
|
4216 |
|
|
|
4217 |
|
|
|
4218 |
|
|
process (dbg_seq_rst_n, dbg_seq_clk)
|
4219 |
|
|
begin
|
4220 |
|
|
if dbg_seq_rst_n = '0' then
|
4221 |
|
|
ccd_cmd_done_ack <= '0';
|
4222 |
|
|
ccd_cmd_done_3t <= '0';
|
4223 |
|
|
ccd_cmd_done_2t <= '0';
|
4224 |
|
|
ccd_cmd_done_t <= '0';
|
4225 |
|
|
seq_dbg_rd_data <= (others => '0');
|
4226 |
|
|
seq_clk_waitreq_int <= '1';
|
4227 |
|
|
|
4228 |
|
|
elsif rising_edge(dbg_seq_clk) then
|
4229 |
|
|
seq_clk_waitreq_int <= '1';
|
4230 |
|
|
|
4231 |
|
|
if ccd_cmd_done_2t = '1' and ccd_cmd_done_3t = '0' then
|
4232 |
|
|
seq_clk_waitreq_int <= '0';
|
4233 |
|
|
ccd_cmd_done_ack <= '1';
|
4234 |
|
|
seq_dbg_rd_data <= ccd_rd_data; -- if read
|
4235 |
|
|
elsif ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
|
4236 |
|
|
ccd_cmd_done_ack <= '0';
|
4237 |
|
|
end if;
|
4238 |
|
|
|
4239 |
|
|
ccd_cmd_done_3t <= ccd_cmd_done_2t;
|
4240 |
|
|
ccd_cmd_done_2t <= ccd_cmd_done_t;
|
4241 |
|
|
ccd_cmd_done_t <= ccd_cmd_done;
|
4242 |
|
|
end if;
|
4243 |
|
|
end process;
|
4244 |
|
|
|
4245 |
|
|
seq_dbg_waitrequest <= seq_clk_waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
|
4246 |
|
|
|
4247 |
|
|
end generate re_synchronise_avalon;
|
4248 |
|
|
|
4249 |
|
|
|
4250 |
|
|
-- register some inputs for speed.
|
4251 |
|
|
process (rst_n, clk)
|
4252 |
|
|
begin
|
4253 |
|
|
if rst_n = '0' then
|
4254 |
|
|
int_ac_1t_r <= '0';
|
4255 |
|
|
trefi_failure_r <= '0';
|
4256 |
|
|
elsif rising_edge(clk) then
|
4257 |
|
|
int_ac_1t_r <= int_ac_1t;
|
4258 |
|
|
trefi_failure_r <= trefi_failure;
|
4259 |
|
|
end if;
|
4260 |
|
|
end process;
|
4261 |
|
|
|
4262 |
|
|
-- mmi not able to write to iram in current instance of mmi block
|
4263 |
|
|
mmi_iram_enable_writes <= '0';
|
4264 |
|
|
|
4265 |
|
|
-- check if iram ready
|
4266 |
|
|
process (rst_n, clk)
|
4267 |
|
|
begin
|
4268 |
|
|
if rst_n = '0' then
|
4269 |
|
|
iram_ready <= '0';
|
4270 |
|
|
elsif rising_edge(clk) then
|
4271 |
|
|
if USE_IRAM = '0' then
|
4272 |
|
|
iram_ready <= '0';
|
4273 |
|
|
else
|
4274 |
|
|
if ctrl_mmi.ctrl_calibration_success = '1' or ctrl_mmi.ctrl_calibration_fail = '1' then
|
4275 |
|
|
iram_ready <= '1';
|
4276 |
|
|
else
|
4277 |
|
|
iram_ready <= '0';
|
4278 |
|
|
end if;
|
4279 |
|
|
end if;
|
4280 |
|
|
end if;
|
4281 |
|
|
end process;
|
4282 |
|
|
|
4283 |
|
|
-- --------------------------------------------------------------
|
4284 |
|
|
-- single registered process for mmi access.
|
4285 |
|
|
-- --------------------------------------------------------------
|
4286 |
|
|
process (rst_n, clk)
|
4287 |
|
|
variable v_mmi_regs : t_mmi_regs;
|
4288 |
|
|
begin
|
4289 |
|
|
if rst_n = '0' then
|
4290 |
|
|
|
4291 |
|
|
mmi_regs <= defaults;
|
4292 |
|
|
mmi_rw_regs_initialised <= '0';
|
4293 |
|
|
|
4294 |
|
|
-- this register records whether the c_codeword has been written to address 0x0001
|
4295 |
|
|
-- once it has, then other writes are accepted.
|
4296 |
|
|
mmi_regs.enable_writes <= '0';
|
4297 |
|
|
|
4298 |
|
|
int_rdata <= (others => '0');
|
4299 |
|
|
waitreq_int <= '1';
|
4300 |
|
|
|
4301 |
|
|
-- clear wait request counter
|
4302 |
|
|
waitreq_count <= 0;
|
4303 |
|
|
waitreq_count_is_zero <= '1';
|
4304 |
|
|
|
4305 |
|
|
-- iram interface defaults
|
4306 |
|
|
mmi_iram <= defaults;
|
4307 |
|
|
|
4308 |
|
|
elsif rising_edge(clk) then
|
4309 |
|
|
-- default assignment
|
4310 |
|
|
waitreq_int <= '1';
|
4311 |
|
|
|
4312 |
|
|
write_clear(mmi_regs.rw_regs);
|
4313 |
|
|
|
4314 |
|
|
-- only initialise rw_regs once after hard reset
|
4315 |
|
|
if mmi_rw_regs_initialised = '0' then
|
4316 |
|
|
|
4317 |
|
|
mmi_rw_regs_initialised <= '1';
|
4318 |
|
|
|
4319 |
|
|
--reset all read/write regs and read path ouput registers and apply default MRS Settings.
|
4320 |
|
|
mmi_regs.rw_regs <= defaults(PHY_DEF_MR_1ST,
|
4321 |
|
|
PHY_DEF_MR_2ND,
|
4322 |
|
|
PHY_DEF_MR_3RD,
|
4323 |
|
|
PHY_DEF_MR_4TH,
|
4324 |
|
|
NOM_DQS_PHASE_SETTING,
|
4325 |
|
|
PLL_STEPS_PER_CYCLE,
|
4326 |
|
|
c_pll_360_sweeps, -- number of times 360 degrees is swept
|
4327 |
|
|
TRACKING_INTERVAL_IN_MS,
|
4328 |
|
|
c_hl_stage_enable);
|
4329 |
|
|
|
4330 |
|
|
end if;
|
4331 |
|
|
|
4332 |
|
|
-- bit packing input data structures into the ro_regs structure, for reading
|
4333 |
|
|
mmi_regs.ro_regs <= defaults(dgrb_mmi,
|
4334 |
|
|
ctrl_mmi,
|
4335 |
|
|
pll_mmi,
|
4336 |
|
|
mmi_regs.rw_regs.rw_if_test,
|
4337 |
|
|
USE_IRAM,
|
4338 |
|
|
MEM_IF_DQS_CAPTURE,
|
4339 |
|
|
int_ac_1t_r,
|
4340 |
|
|
trefi_failure_r,
|
4341 |
|
|
iram_status,
|
4342 |
|
|
IRAM_AWIDTH);
|
4343 |
|
|
|
4344 |
|
|
-- write has priority over read
|
4345 |
|
|
if int_write = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
|
4346 |
|
|
|
4347 |
|
|
-- mmi local register write
|
4348 |
|
|
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
|
4349 |
|
|
|
4350 |
|
|
v_mmi_regs := mmi_regs;
|
4351 |
|
|
|
4352 |
|
|
write(v_mmi_regs, to_integer(unsigned(int_address(3 downto 0))), int_wdata);
|
4353 |
|
|
|
4354 |
|
|
if mmi_regs.enable_writes = '1' then
|
4355 |
|
|
v_mmi_regs.rw_regs.rw_hl_css.hl_css := c_hl_stage_enable or v_mmi_regs.rw_regs.rw_hl_css.hl_css;
|
4356 |
|
|
end if;
|
4357 |
|
|
|
4358 |
|
|
mmi_regs <= v_mmi_regs;
|
4359 |
|
|
|
4360 |
|
|
-- handshake for safe transactions
|
4361 |
|
|
waitreq_int <= '0';
|
4362 |
|
|
waitreq_count <= c_response_lat;
|
4363 |
|
|
|
4364 |
|
|
-- iram write just handshake back (no write supported)
|
4365 |
|
|
else
|
4366 |
|
|
|
4367 |
|
|
waitreq_int <= '0';
|
4368 |
|
|
waitreq_count <= c_response_lat;
|
4369 |
|
|
|
4370 |
|
|
end if;
|
4371 |
|
|
|
4372 |
|
|
elsif int_read = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
|
4373 |
|
|
|
4374 |
|
|
-- mmi local register read
|
4375 |
|
|
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
|
4376 |
|
|
|
4377 |
|
|
int_rdata <= read(mmi_regs, to_integer(unsigned(int_address(3 downto 0))));
|
4378 |
|
|
|
4379 |
|
|
waitreq_count <= c_response_lat;
|
4380 |
|
|
waitreq_int <= '0'; -- acknowledge read command regardless.
|
4381 |
|
|
|
4382 |
|
|
|
4383 |
|
|
-- iram being addressed
|
4384 |
|
|
elsif to_integer(unsigned(int_address(int_address'high downto c_int_iram_start_size))) = 1
|
4385 |
|
|
and iram_ready = '1'
|
4386 |
|
|
then
|
4387 |
|
|
mmi_iram.read <= '1';
|
4388 |
|
|
mmi_iram.addr <= to_integer(unsigned(int_address(IRAM_AWIDTH -1 downto 0)));
|
4389 |
|
|
|
4390 |
|
|
if iram_status.done = '1' then
|
4391 |
|
|
waitreq_int <= '0';
|
4392 |
|
|
mmi_iram.read <= '0';
|
4393 |
|
|
waitreq_count <= c_response_lat;
|
4394 |
|
|
int_rdata <= iram_status.rdata;
|
4395 |
|
|
end if;
|
4396 |
|
|
|
4397 |
|
|
else -- respond and keep the interface from hanging
|
4398 |
|
|
int_rdata <= x"DEADBEEF";
|
4399 |
|
|
waitreq_int <= '0';
|
4400 |
|
|
waitreq_count <= c_response_lat;
|
4401 |
|
|
|
4402 |
|
|
end if;
|
4403 |
|
|
|
4404 |
|
|
elsif waitreq_count /= 0 then
|
4405 |
|
|
waitreq_count <= waitreq_count -1;
|
4406 |
|
|
|
4407 |
|
|
-- if performing a write, set back to defaults. If not, default anyway
|
4408 |
|
|
mmi_iram <= defaults;
|
4409 |
|
|
|
4410 |
|
|
end if;
|
4411 |
|
|
|
4412 |
|
|
if waitreq_count = 1 or waitreq_count = 0 then
|
4413 |
|
|
waitreq_count_is_zero <= '1'; -- as it will be next clock cycle
|
4414 |
|
|
else
|
4415 |
|
|
waitreq_count_is_zero <= '0';
|
4416 |
|
|
end if;
|
4417 |
|
|
|
4418 |
|
|
-- supply iram read data when ready
|
4419 |
|
|
if iram_status.done = '1' then
|
4420 |
|
|
int_rdata <= iram_status.rdata;
|
4421 |
|
|
end if;
|
4422 |
|
|
|
4423 |
|
|
end if;
|
4424 |
|
|
|
4425 |
|
|
end process;
|
4426 |
|
|
|
4427 |
|
|
-- pack the registers into the output data structures
|
4428 |
|
|
regs_admin_ctrl <= pack_record(mmi_regs.rw_regs);
|
4429 |
|
|
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
|
4430 |
|
|
mmi_pll <= pack_record(mmi_regs.rw_regs);
|
4431 |
|
|
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
|
4432 |
|
|
|
4433 |
|
|
end architecture struct;
|
4434 |
|
|
--
|
4435 |
|
|
|
4436 |
|
|
-- -----------------------------------------------------------------------------
|
4437 |
|
|
-- Abstract : admin block for the non-levelling AFI PHY sequencer
|
4438 |
|
|
-- The admin block supports the autonomy of the sequencer from
|
4439 |
|
|
-- the memory interface controller. In this task admin handles
|
4440 |
|
|
-- memory initialisation (incl. the setting of mode registers)
|
4441 |
|
|
-- and memory refresh, bank activation and pre-charge commands
|
4442 |
|
|
-- (during memory interface calibration). Once calibration is
|
4443 |
|
|
-- complete admin is 'idle' and control of the memory device is
|
4444 |
|
|
-- passed to the users chosen memory interface controller. The
|
4445 |
|
|
-- supported memory types are exclusively DDR, DDR2 and DDR3.
|
4446 |
|
|
-- -----------------------------------------------------------------------------
|
4447 |
|
|
|
4448 |
|
|
library ieee;
|
4449 |
|
|
use ieee.std_logic_1164.all;
|
4450 |
|
|
use ieee.numeric_std.all;
|
4451 |
|
|
|
4452 |
|
|
library work;
|
4453 |
|
|
|
4454 |
|
|
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
|
4455 |
|
|
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
|
4456 |
|
|
-- for the stages of DRAM memory calibration.
|
4457 |
|
|
--
|
4458 |
|
|
use work.altera_ddr_phy_alt_mem_phy_record_pkg.all;
|
4459 |
|
|
|
4460 |
|
|
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
|
4461 |
|
|
-- thoughout the sequencer and will not change (for constants which may change between sequencer
|
4462 |
|
|
-- instances generics are used)
|
4463 |
|
|
--
|
4464 |
|
|
use work.altera_ddr_phy_alt_mem_phy_constants_pkg.all;
|
4465 |
|
|
|
4466 |
|
|
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
|
4467 |
|
|
-- and command signals in one record and unify the functions operating on this record.
|
4468 |
|
|
--
|
4469 |
|
|
use work.altera_ddr_phy_alt_mem_phy_addr_cmd_pkg.all;
|
4470 |
|
|
|
4471 |
|
|
--
|
4472 |
|
|
entity altera_ddr_phy_alt_mem_phy_admin is
|
4473 |
|
|
generic (
|
4474 |
|
|
-- physical interface width definitions
|
4475 |
|
|
MEM_IF_DQS_WIDTH : natural := 9;
|
4476 |
|
|
MEM_IF_DWIDTH : natural := 72;
|
4477 |
|
|
MEM_IF_DM_WIDTH : natural := 9;
|
4478 |
|
|
MEM_IF_DQ_PER_DQS : natural := 8;
|
4479 |
|
|
DWIDTH_RATIO : natural := 2;
|
4480 |
|
|
CLOCK_INDEX_WIDTH : natural := 4;
|
4481 |
|
|
MEM_IF_CLK_PAIR_COUNT : natural := 3;
|
4482 |
|
|
MEM_IF_ADDR_WIDTH : natural := 13;
|
4483 |
|
|
MEM_IF_BANKADDR_WIDTH : natural := 3;
|
4484 |
|
|
MEM_IF_NUM_RANKS : natural := 1;
|
4485 |
|
|
ADV_LAT_WIDTH : natural := 5;
|
4486 |
|
|
MEM_IF_DQSN_EN : natural := 0;
|
4487 |
|
|
MEM_IF_MEMTYPE : string := "DDR2";
|
4488 |
|
|
|
4489 |
|
|
-- calibration address information
|
4490 |
|
|
MEM_IF_CAL_BANK : natural := 0; -- Bank to which calibration data is written
|
4491 |
|
|
MEM_IF_CAL_BASE_ROW : natural := 0;
|
4492 |
|
|
|
4493 |
|
|
GENERATE_ADDITIONAL_DBG_RTL : natural := 1;
|
4494 |
|
|
NON_OP_EVAL_MD : string := "PIN_FINDER"; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
|
4495 |
|
|
|
4496 |
|
|
-- timing parameters
|
4497 |
|
|
MEM_IF_CLK_PS : natural := 2500;
|
4498 |
|
|
TINIT_TCK : natural := 80000; -- initial delay of 200us
|
4499 |
|
|
TINIT_RST : natural := 100 -- used for DDR3 device support
|
4500 |
|
|
);
|
4501 |
|
|
port (
|
4502 |
|
|
-- clk / reset
|
4503 |
|
|
clk : in std_logic;
|
4504 |
|
|
rst_n : in std_logic;
|
4505 |
|
|
|
4506 |
|
|
-- the 2 signals below are unused for DDR/DDR2 (maintained for equivalent interface to DDR3 deskew sequencer)
|
4507 |
|
|
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
|
4508 |
|
|
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
|
4509 |
|
|
|
4510 |
|
|
-- addr/cmd interface
|
4511 |
|
|
seq_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
|
4512 |
|
|
seq_ac_sel : out std_logic;
|
4513 |
|
|
|
4514 |
|
|
-- determined from MR settings
|
4515 |
|
|
enable_odt : out std_logic;
|
4516 |
|
|
|
4517 |
|
|
-- interface to the mmi block
|
4518 |
|
|
regs_admin_ctrl_rec : in t_admin_ctrl;
|
4519 |
|
|
admin_regs_status_rec : out t_admin_stat;
|
4520 |
|
|
trefi_failure : out std_logic;
|
4521 |
|
|
|
4522 |
|
|
-- interface to the ctrl block
|
4523 |
|
|
ctrl_admin : in t_ctrl_command;
|
4524 |
|
|
admin_ctrl : out t_ctrl_stat;
|
4525 |
|
|
|
4526 |
|
|
-- interface with dgrb/dgwb blocks
|
4527 |
|
|
ac_access_req : in std_logic;
|
4528 |
|
|
ac_access_gnt : out std_logic;
|
4529 |
|
|
|
4530 |
|
|
-- calibration status signals (from ctrl block)
|
4531 |
|
|
cal_fail : in std_logic;
|
4532 |
|
|
cal_success : in std_logic
|
4533 |
|
|
|
4534 |
|
|
);
|
4535 |
|
|
end entity;
|
4536 |
|
|
|
4537 |
|
|
--
|
4538 |
|
|
architecture struct of altera_ddr_phy_alt_mem_phy_admin is
|
4539 |
|
|
|
4540 |
|
|
constant c_max_mode_reg_index : natural := 12;
|
4541 |
|
|
|
4542 |
|
|
-- timing below is safe for range 80-400MHz operation - taken from worst case DDR2 (JEDEC JESD79-2E) / DDR3 (JESD79-3B)
|
4543 |
|
|
constant c_init_prech_delay : natural := 162; -- precharge delay (400ns) (TXPR for DDR3)
|
4544 |
|
|
constant c_trp_in_clks : natural := 8; -- set equal to trp / tck (trp = 15ns)
|
4545 |
|
|
constant c_tmrd_in_clks : natural := 4; -- maximum 4 clock cycles (DDR3)
|
4546 |
|
|
constant c_tmod_in_clks : natural := 8; -- ODT update from MRS command (tmod = 12ns (DDR2))
|
4547 |
|
|
|
4548 |
|
|
constant c_trrd_min_in_clks : natural := 4; -- minimum clk cycles between bank activate cmds (7.5ns)
|
4549 |
|
|
constant c_trcd_min_in_clks : natural := 8; -- minimum bank activate to read/write cmd (15ns)
|
4550 |
|
|
|
4551 |
|
|
-- the 2 constants below are parameterised to MEM_IF_CLK_PS due to the large range of possible clock frequency
|
4552 |
|
|
constant c_trfc_min_in_clks : natural := (350000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) + 2; -- refresh-refresh timing (worst case trfc = 350 ns (DDR3))
|
4553 |
|
|
constant c_trefi_min_in_clks : natural := (3900000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) - 2; -- average refresh interval worst case trefi = 3.9 us (industrial grade devices)
|
4554 |
|
|
|
4555 |
|
|
constant c_max_num_stacked_refreshes : natural := 8; -- max no. of stacked refreshes allowed
|
4556 |
|
|
constant c_max_wait_value : natural := 4; -- delay before moving from s_idle to s_refresh_state
|
4557 |
|
|
|
4558 |
|
|
-- DDR3 specific:
|
4559 |
|
|
constant c_zq_init_duration_clks : natural := 514; -- full rate (worst case) cycle count for tZQCL init
|
4560 |
|
|
constant c_tzqcs : natural := 66; -- number of full rate clock cycles
|
4561 |
|
|
|
4562 |
|
|
-- below is a record which is used to parameterise the address and command signals (addr_cmd) used in this block
|
4563 |
|
|
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
|
4564 |
|
|
|
4565 |
|
|
-- a prefix for all report signals to identify phy and sequencer block
|
4566 |
|
|
--
|
4567 |
|
|
constant admin_report_prefix : string := "altera_ddr_phy_alt_mem_phy_seq (admin) : ";
|
4568 |
|
|
|
4569 |
|
|
-- state type for admin_state (main state machine of admin block)
|
4570 |
|
|
type t_admin_state is
|
4571 |
|
|
(
|
4572 |
|
|
s_reset, -- reset state
|
4573 |
|
|
s_run_init_seq, -- run the initialisation sequence (up to but not including MR setting)
|
4574 |
|
|
s_program_cal_mrs, -- program the mode registers ready for calibration (this is the user settings
|
4575 |
|
|
-- with some overloads and extra init functionality)
|
4576 |
|
|
|
4577 |
|
|
s_idle, -- idle (i.e. maintaining refresh to max)
|
4578 |
|
|
|
4579 |
|
|
s_topup_refresh, -- make sure refreshes are maxed out before going on.
|
4580 |
|
|
s_topup_refresh_done, -- wait for tRFC after refresh command
|
4581 |
|
|
|
4582 |
|
|
s_zq_cal_short, -- ZQCAL short command (issued prior to activate) - DDR3 only
|
4583 |
|
|
|
4584 |
|
|
s_access_act, -- activate
|
4585 |
|
|
s_access, -- dgrb, dgwb accesses,
|
4586 |
|
|
s_access_precharge, -- precharge all memory banks
|
4587 |
|
|
|
4588 |
|
|
s_prog_user_mrs, -- program user mode register settings
|
4589 |
|
|
|
4590 |
|
|
s_dummy_wait, -- wait before going to s_refresh state
|
4591 |
|
|
s_refresh, -- issue a memory refresh command
|
4592 |
|
|
s_refresh_done, -- wait for trfc after refresh command
|
4593 |
|
|
s_non_operational -- special debug state to toggle interface if calibration fails
|
4594 |
|
|
);
|
4595 |
|
|
|
4596 |
|
|
signal state : t_admin_state; -- admin block state machine
|
4597 |
|
|
|
4598 |
|
|
-- state type for ac_state
|
4599 |
|
|
type t_ac_state is
|
4600 |
|
|
( s_0 ,
|
4601 |
|
|
s_1 ,
|
4602 |
|
|
s_2 ,
|
4603 |
|
|
s_3 ,
|
4604 |
|
|
s_4 ,
|
4605 |
|
|
s_5 ,
|
4606 |
|
|
s_6 ,
|
4607 |
|
|
s_7 ,
|
4608 |
|
|
s_8 ,
|
4609 |
|
|
s_9 ,
|
4610 |
|
|
s_10,
|
4611 |
|
|
s_11,
|
4612 |
|
|
s_12,
|
4613 |
|
|
s_13,
|
4614 |
|
|
s_14);
|
4615 |
|
|
|
4616 |
|
|
-- enforce one-hot fsm encoding
|
4617 |
|
|
attribute syn_encoding : string;
|
4618 |
|
|
attribute syn_encoding of t_ac_state : TYPE is "one-hot";
|
4619 |
|
|
|
4620 |
|
|
signal ac_state : t_ac_state; -- state machine for sub-states of t_admin_state states
|
4621 |
|
|
|
4622 |
|
|
signal stage_counter : natural range 0 to 2**18 - 1; -- counter to support memory timing delays
|
4623 |
|
|
signal stage_counter_zero : std_logic;
|
4624 |
|
|
|
4625 |
|
|
signal addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1); -- internal copy of output DRAM addr/cmd signals
|
4626 |
|
|
|
4627 |
|
|
signal mem_init_complete : std_logic; -- signifies memory initialisation is complete
|
4628 |
|
|
signal cal_complete : std_logic; -- calibration complete (equals: cal_success OR cal_fail)
|
4629 |
|
|
|
4630 |
|
|
signal int_mr0 : std_logic_vector(regs_admin_ctrl_rec.mr0'range); -- an internal copy of mode register settings
|
4631 |
|
|
signal int_mr1 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
|
4632 |
|
|
signal int_mr2 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
|
4633 |
|
|
signal int_mr3 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
|
4634 |
|
|
|
4635 |
|
|
signal refresh_count : natural range c_trefi_min_in_clks downto 0; -- determine when refresh is due
|
4636 |
|
|
signal refresh_due : std_logic; -- need to do a refresh now
|
4637 |
|
|
signal refresh_done : std_logic; -- pulse when refresh complete
|
4638 |
|
|
signal num_stacked_refreshes : natural range 0 to c_max_num_stacked_refreshes - 1; -- can stack upto 8 refreshes (for DDR2)
|
4639 |
|
|
signal refreshes_maxed : std_logic; -- signal refreshes are maxed out
|
4640 |
|
|
signal initial_refresh_issued : std_logic; -- to start the refresh counter off
|
4641 |
|
|
|
4642 |
|
|
signal ctrl_rec : t_ctrl_command;
|
4643 |
|
|
-- last state logic
|
4644 |
|
|
signal command_started : std_logic; -- provides a pulse when admin starts processing a command
|
4645 |
|
|
signal command_done : std_logic; -- provides a pulse when admin completes processing a command is completed
|
4646 |
|
|
signal finished_state : std_logic; -- finished current t_admin_state state
|
4647 |
|
|
|
4648 |
|
|
signal admin_req_extended : std_logic; -- keep requests for this block asserted until it is an ack is asserted
|
4649 |
|
|
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1; -- which chip select being programmed at this instance
|
4650 |
|
|
signal per_cs_init_seen : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
|
4651 |
|
|
|
4652 |
|
|
-- some signals to enable non_operational debug (optimised away if GENERATE_ADDITIONAL_DBG_RTL = 0)
|
4653 |
|
|
signal nop_toggle_signal : t_addr_cmd_signals;
|
4654 |
|
|
signal nop_toggle_pin : natural range 0 to MEM_IF_ADDR_WIDTH - 1; -- track which pin in a signal to toggle
|
4655 |
|
|
signal nop_toggle_value : std_logic;
|
4656 |
|
|
|
4657 |
|
|
begin -- architecture struct
|
4658 |
|
|
|
4659 |
|
|
-- concurrent assignment of internal addr_cmd to output port seq_ac
|
4660 |
|
|
process (addr_cmd)
|
4661 |
|
|
begin
|
4662 |
|
|
seq_ac <= addr_cmd;
|
4663 |
|
|
end process;
|
4664 |
|
|
|
4665 |
|
|
-- generate calibration complete signal
|
4666 |
|
|
process (cal_success, cal_fail)
|
4667 |
|
|
begin
|
4668 |
|
|
cal_complete <= cal_success or cal_fail;
|
4669 |
|
|
end process;
|
4670 |
|
|
|
4671 |
|
|
-- register the control command record
|
4672 |
|
|
process (clk, rst_n)
|
4673 |
|
|
begin
|
4674 |
|
|
if rst_n = '0' then
|
4675 |
|
|
ctrl_rec <= defaults;
|
4676 |
|
|
elsif rising_edge(clk) then
|
4677 |
|
|
ctrl_rec <= ctrl_admin;
|
4678 |
|
|
end if;
|
4679 |
|
|
end process;
|
4680 |
|
|
|
4681 |
|
|
-- extend the admin block request until ack is asserted
|
4682 |
|
|
process (clk, rst_n)
|
4683 |
|
|
begin
|
4684 |
|
|
if rst_n = '0' then
|
4685 |
|
|
admin_req_extended <= '0';
|
4686 |
|
|
elsif rising_edge(clk) then
|
4687 |
|
|
if ( (ctrl_rec.command_req = '1') and ( curr_active_block(ctrl_rec.command) = admin) ) then
|
4688 |
|
|
admin_req_extended <= '1';
|
4689 |
|
|
elsif command_started = '1' then -- this is effectively a copy of command_ack generation
|
4690 |
|
|
admin_req_extended <= '0';
|
4691 |
|
|
end if;
|
4692 |
|
|
end if;
|
4693 |
|
|
end process;
|
4694 |
|
|
|
4695 |
|
|
-- generate the current_cs signal to track which cs accessed by PHY at any instance
|
4696 |
|
|
process (clk, rst_n)
|
4697 |
|
|
begin
|
4698 |
|
|
if rst_n = '0' then
|
4699 |
|
|
current_cs <= 0;
|
4700 |
|
|
elsif rising_edge(clk) then
|
4701 |
|
|
if ctrl_rec.command_req = '1' then
|
4702 |
|
|
current_cs <= ctrl_rec.command_op.current_cs;
|
4703 |
|
|
end if;
|
4704 |
|
|
end if;
|
4705 |
|
|
end process;
|
4706 |
|
|
|
4707 |
|
|
|
4708 |
|
|
-- -----------------------------------------------------------------------------
|
4709 |
|
|
-- refresh logic: DDR/DDR2/DDR3 allows upto 8 refreshes to be "stacked" or queued up.
|
4710 |
|
|
-- In the idle state, will ensure refreshes are issued when necessary. Then,
|
4711 |
|
|
-- when an access_request is received, 7 topup refreshes will be done to max out
|
4712 |
|
|
-- the number of queued refreshes. That way, we know we have the maximum time
|
4713 |
|
|
-- available before another refresh is due.
|
4714 |
|
|
-- -----------------------------------------------------------------------------
|
4715 |
|
|
|
4716 |
|
|
-- initial_refresh_issued flag: used to sync refresh_count
|
4717 |
|
|
process (clk, rst_n)
|
4718 |
|
|
begin
|
4719 |
|
|
if rst_n = '0' then
|
4720 |
|
|
initial_refresh_issued <= '0';
|
4721 |
|
|
elsif rising_edge(clk) then
|
4722 |
|
|
if cal_complete = '1' then
|
4723 |
|
|
initial_refresh_issued <= '0';
|
4724 |
|
|
else
|
4725 |
|
|
if state = s_refresh_done or
|
4726 |
|
|
state = s_topup_refresh_done then
|
4727 |
|
|
initial_refresh_issued <= '1';
|
4728 |
|
|
end if;
|
4729 |
|
|
end if;
|
4730 |
|
|
end if;
|
4731 |
|
|
end process;
|
4732 |
|
|
|
4733 |
|
|
-- refresh timer: used to work out when a refresh is due
|
4734 |
|
|
process (clk, rst_n)
|
4735 |
|
|
begin
|
4736 |
|
|
if rst_n = '0' then
|
4737 |
|
|
refresh_count <= c_trefi_min_in_clks;
|
4738 |
|
|
elsif rising_edge(clk) then
|
4739 |
|
|
if cal_complete = '1' then
|
4740 |
|
|
refresh_count <= c_trefi_min_in_clks;
|
4741 |
|
|
else
|
4742 |
|
|
if refresh_count = 0 or
|
4743 |
|
|
initial_refresh_issued = '0' or
|
4744 |
|
|
(refreshes_maxed = '1' and refresh_done = '1') then -- if refresh issued when already maxed
|
4745 |
|
|
refresh_count <= c_trefi_min_in_clks;
|
4746 |
|
|
else
|
4747 |
|
|
refresh_count <= refresh_count - 1;
|
4748 |
|
|
end if;
|
4749 |
|
|
end if;
|
4750 |
|
|
end if;
|
4751 |
|
|
end process;
|
4752 |
|
|
|
4753 |
|
|
-- refresh_due generation: 1 cycle pulse to indicate that c_trefi_min_in_clks has elapsed, and
|
4754 |
|
|
-- therefore a refresh is due
|
4755 |
|
|
process (clk, rst_n)
|
4756 |
|
|
begin
|
4757 |
|
|
if rst_n = '0' then
|
4758 |
|
|
refresh_due <= '0';
|
4759 |
|
|
elsif rising_edge(clk) then
|
4760 |
|
|
if refresh_count = 0 and cal_complete = '0' then
|
4761 |
|
|
refresh_due <= '1';
|
4762 |
|
|
else
|
4763 |
|
|
refresh_due <= '0';
|
4764 |
|
|
end if;
|
4765 |
|
|
end if;
|
4766 |
|
|
end process;
|
4767 |
|
|
|
4768 |
|
|
|
4769 |
|
|
-- counter to keep track of number of refreshes "stacked". NB: Up to 8
|
4770 |
|
|
-- refreshes can be stacked.
|
4771 |
|
|
process (clk, rst_n)
|
4772 |
|
|
begin
|
4773 |
|
|
if rst_n = '0' then
|
4774 |
|
|
num_stacked_refreshes <= 0;
|
4775 |
|
|
trefi_failure <= '0'; -- default no trefi failure
|
4776 |
|
|
|
4777 |
|
|
elsif rising_edge (clk) then
|
4778 |
|
|
|
4779 |
|
|
if state = s_reset then
|
4780 |
|
|
trefi_failure <= '0'; -- default no trefi failure (in restart)
|
4781 |
|
|
end if;
|
4782 |
|
|
|
4783 |
|
|
if cal_complete = '1' then
|
4784 |
|
|
num_stacked_refreshes <= 0;
|
4785 |
|
|
else
|
4786 |
|
|
if refresh_due = '1' and num_stacked_refreshes /= 0 then
|
4787 |
|
|
num_stacked_refreshes <= num_stacked_refreshes - 1;
|
4788 |
|
|
elsif refresh_done = '1' and num_stacked_refreshes /= c_max_num_stacked_refreshes - 1 then
|
4789 |
|
|
num_stacked_refreshes <= num_stacked_refreshes + 1;
|
4790 |
|
|
end if;
|
4791 |
|
|
|
4792 |
|
|
-- debug message if stacked refreshes are depleted and refresh is due
|
4793 |
|
|
if refresh_due = '1' and num_stacked_refreshes = 0 and initial_refresh_issued = '1' then
|
4794 |
|
|
report admin_report_prefix & "error refresh is due and num_stacked_refreshes is zero" severity error;
|
4795 |
|
|
trefi_failure <= '1'; -- persist
|
4796 |
|
|
end if;
|
4797 |
|
|
end if;
|
4798 |
|
|
|
4799 |
|
|
end if;
|
4800 |
|
|
end process;
|
4801 |
|
|
|
4802 |
|
|
-- generate signal to state if refreshes are maxed out
|
4803 |
|
|
process (clk, rst_n)
|
4804 |
|
|
begin
|
4805 |
|
|
if rst_n = '0' then
|
4806 |
|
|
|
4807 |
|
|
refreshes_maxed <= '0';
|
4808 |
|
|
|
4809 |
|
|
elsif rising_edge (clk) then
|
4810 |
|
|
|
4811 |
|
|
if num_stacked_refreshes < c_max_num_stacked_refreshes - 1 then
|
4812 |
|
|
refreshes_maxed <= '0';
|
4813 |
|
|
else
|
4814 |
|
|
refreshes_maxed <= '1';
|
4815 |
|
|
end if;
|
4816 |
|
|
|
4817 |
|
|
end if;
|
4818 |
|
|
|
4819 |
|
|
end process;
|
4820 |
|
|
|
4821 |
|
|
-- ----------------------------------------------------
|
4822 |
|
|
-- Mode register selection
|
4823 |
|
|
-- -----------------------------------------------------
|
4824 |
|
|
|
4825 |
|
|
int_mr0(regs_admin_ctrl_rec.mr0'range) <= regs_admin_ctrl_rec.mr0;
|
4826 |
|
|
int_mr1(regs_admin_ctrl_rec.mr1'range) <= regs_admin_ctrl_rec.mr1;
|
4827 |
|
|
int_mr2(regs_admin_ctrl_rec.mr2'range) <= regs_admin_ctrl_rec.mr2;
|
4828 |
|
|
int_mr3(regs_admin_ctrl_rec.mr3'range) <= regs_admin_ctrl_rec.mr3;
|
4829 |
|
|
|
4830 |
|
|
-- -------------------------------------------------------
|
4831 |
|
|
-- State machine
|
4832 |
|
|
-- -------------------------------------------------------
|
4833 |
|
|
process(rst_n, clk)
|
4834 |
|
|
begin
|
4835 |
|
|
if rst_n = '0' then
|
4836 |
|
|
state <= s_reset;
|
4837 |
|
|
command_done <= '0';
|
4838 |
|
|
command_started <= '0';
|
4839 |
|
|
|
4840 |
|
|
elsif rising_edge(clk) then
|
4841 |
|
|
|
4842 |
|
|
-- Last state logic
|
4843 |
|
|
command_done <= '0';
|
4844 |
|
|
command_started <= '0';
|
4845 |
|
|
|
4846 |
|
|
case state is
|
4847 |
|
|
|
4848 |
|
|
when s_reset |
|
4849 |
|
|
s_non_operational =>
|
4850 |
|
|
|
4851 |
|
|
if ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then
|
4852 |
|
|
state <= s_run_init_seq;
|
4853 |
|
|
command_started <= '1';
|
4854 |
|
|
end if;
|
4855 |
|
|
|
4856 |
|
|
when s_run_init_seq =>
|
4857 |
|
|
|
4858 |
|
|
if finished_state = '1' then
|
4859 |
|
|
state <= s_program_cal_mrs;
|
4860 |
|
|
end if;
|
4861 |
|
|
|
4862 |
|
|
when s_program_cal_mrs =>
|
4863 |
|
|
|
4864 |
|
|
if finished_state = '1' then
|
4865 |
|
|
if refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh if all ranks initialised
|
4866 |
|
|
state <= s_topup_refresh;
|
4867 |
|
|
else
|
4868 |
|
|
state <= s_idle;
|
4869 |
|
|
end if;
|
4870 |
|
|
command_done <= '1';
|
4871 |
|
|
end if;
|
4872 |
|
|
|
4873 |
|
|
when s_idle =>
|
4874 |
|
|
|
4875 |
|
|
if ac_access_req = '1' then
|
4876 |
|
|
state <= s_topup_refresh;
|
4877 |
|
|
elsif ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then
|
4878 |
|
|
state <= s_program_cal_mrs;
|
4879 |
|
|
command_started <= '1';
|
4880 |
|
|
|
4881 |
|
|
-- always enter s_prog_user_mrs via topup refresh
|
4882 |
|
|
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
|
4883 |
|
|
state <= s_topup_refresh;
|
4884 |
|
|
|
4885 |
|
|
elsif refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh once all ranks initialised
|
4886 |
|
|
state <= s_dummy_wait;
|
4887 |
|
|
end if;
|
4888 |
|
|
|
4889 |
|
|
when s_dummy_wait =>
|
4890 |
|
|
|
4891 |
|
|
if finished_state = '1' then
|
4892 |
|
|
state <= s_refresh;
|
4893 |
|
|
end if;
|
4894 |
|
|
|
4895 |
|
|
when s_topup_refresh =>
|
4896 |
|
|
|
4897 |
|
|
if finished_state = '1' then
|
4898 |
|
|
state <= s_topup_refresh_done;
|
4899 |
|
|
end if;
|
4900 |
|
|
|
4901 |
|
|
when s_topup_refresh_done =>
|
4902 |
|
|
|
4903 |
|
|
if finished_state = '1' then -- to ensure trfc is not violated
|
4904 |
|
|
if refreshes_maxed = '0' then
|
4905 |
|
|
state <= s_topup_refresh;
|
4906 |
|
|
|
4907 |
|
|
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
|
4908 |
|
|
state <= s_prog_user_mrs;
|
4909 |
|
|
command_started <= '1';
|
4910 |
|
|
|
4911 |
|
|
elsif ac_access_req = '1' then
|
4912 |
|
|
|
4913 |
|
|
if MEM_IF_MEMTYPE = "DDR3" then
|
4914 |
|
|
state <= s_zq_cal_short;
|
4915 |
|
|
else
|
4916 |
|
|
state <= s_access_act;
|
4917 |
|
|
end if;
|
4918 |
|
|
|
4919 |
|
|
else
|
4920 |
|
|
state <= s_idle;
|
4921 |
|
|
end if;
|
4922 |
|
|
end if;
|
4923 |
|
|
|
4924 |
|
|
when s_zq_cal_short => -- DDR3 only
|
4925 |
|
|
|
4926 |
|
|
if finished_state = '1' then
|
4927 |
|
|
state <= s_access_act;
|
4928 |
|
|
end if;
|
4929 |
|
|
|
4930 |
|
|
when s_access_act =>
|
4931 |
|
|
|
4932 |
|
|
if finished_state = '1' then
|
4933 |
|
|
state <= s_access;
|
4934 |
|
|
end if;
|
4935 |
|
|
|
4936 |
|
|
when s_access =>
|
4937 |
|
|
|
4938 |
|
|
if ac_access_req = '0' then
|
4939 |
|
|
state <= s_access_precharge;
|
4940 |
|
|
end if;
|
4941 |
|
|
|
4942 |
|
|
when s_access_precharge =>
|
4943 |
|
|
|
4944 |
|
|
-- ensure precharge all timer has elapsed.
|
4945 |
|
|
if finished_state = '1' then
|
4946 |
|
|
state <= s_idle;
|
4947 |
|
|
end if;
|
4948 |
|
|
|
4949 |
|
|
when s_prog_user_mrs =>
|
4950 |
|
|
|
4951 |
|
|
if finished_state = '1' then
|
4952 |
|
|
state <= s_idle;
|
4953 |
|
|
command_done <= '1';
|
4954 |
|
|
end if;
|
4955 |
|
|
|
4956 |
|
|
when s_refresh =>
|
4957 |
|
|
|
4958 |
|
|
if finished_state = '1' then
|
4959 |
|
|
state <= s_refresh_done;
|
4960 |
|
|
end if;
|
4961 |
|
|
|
4962 |
|
|
when s_refresh_done =>
|
4963 |
|
|
|
4964 |
|
|
if finished_state = '1' then -- to ensure trfc is not violated
|
4965 |
|
|
if refreshes_maxed = '0' then
|
4966 |
|
|
state <= s_refresh;
|
4967 |
|
|
else
|
4968 |
|
|
state <= s_idle;
|
4969 |
|
|
end if;
|
4970 |
|
|
end if;
|
4971 |
|
|
|
4972 |
|
|
when others =>
|
4973 |
|
|
|
4974 |
|
|
state <= s_reset;
|
4975 |
|
|
|
4976 |
|
|
end case;
|
4977 |
|
|
|
4978 |
|
|
if cal_complete = '1' then
|
4979 |
|
|
state <= s_reset;
|
4980 |
|
|
if GENERATE_ADDITIONAL_DBG_RTL = 1 and cal_success = '0' then
|
4981 |
|
|
state <= s_non_operational; -- if calibration failed and debug enabled then toggle pins in pre-defined pattern
|
4982 |
|
|
end if;
|
4983 |
|
|
end if;
|
4984 |
|
|
end if;
|
4985 |
|
|
end process;
|
4986 |
|
|
|
4987 |
|
|
-- --------------------------------------------------
|
4988 |
|
|
-- process to generate initialisation complete
|
4989 |
|
|
-- --------------------------------------------------
|
4990 |
|
|
process (rst_n, clk)
|
4991 |
|
|
|
4992 |
|
|
begin
|
4993 |
|
|
if rst_n = '0' then
|
4994 |
|
|
|
4995 |
|
|
mem_init_complete <= '0';
|
4996 |
|
|
|
4997 |
|
|
elsif rising_edge(clk) then
|
4998 |
|
|
|
4999 |
|
|
if to_integer(unsigned(per_cs_init_seen)) = 2**MEM_IF_NUM_RANKS - 1 then
|
5000 |
|
|
mem_init_complete <= '1';
|
5001 |
|
|
else
|
5002 |
|
|
mem_init_complete <= '0';
|
5003 |
|
|
end if;
|
5004 |
|
|
|
5005 |
|
|
end if;
|
5006 |
|
|
|
5007 |
|
|
end process;
|
5008 |
|
|
|
5009 |
|
|
-- --------------------------------------------------
|
5010 |
|
|
-- process to generate addr/cmd.
|
5011 |
|
|
-- --------------------------------------------------
|
5012 |
|
|
process(rst_n, clk)
|
5013 |
|
|
|
5014 |
|
|
variable v_mr_overload : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
|
5015 |
|
|
|
5016 |
|
|
-- required for non_operational state only
|
5017 |
|
|
variable v_nop_ac_0 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
|
5018 |
|
|
variable v_nop_ac_1 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
|
5019 |
|
|
|
5020 |
|
|
begin
|
5021 |
|
|
if rst_n = '0' then
|
5022 |
|
|
|
5023 |
|
|
ac_state <= s_0;
|
5024 |
|
|
stage_counter <= 0;
|
5025 |
|
|
stage_counter_zero <= '1';
|
5026 |
|
|
finished_state <= '0';
|
5027 |
|
|
seq_ac_sel <= '1';
|
5028 |
|
|
refresh_done <= '0';
|
5029 |
|
|
per_cs_init_seen <= (others => '0');
|
5030 |
|
|
|
5031 |
|
|
addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
|
5032 |
|
|
|
5033 |
|
|
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
|
5034 |
|
|
nop_toggle_signal <= addr;
|
5035 |
|
|
nop_toggle_pin <= 0;
|
5036 |
|
|
nop_toggle_value <= '0';
|
5037 |
|
|
end if;
|
5038 |
|
|
|
5039 |
|
|
elsif rising_edge(clk) then
|
5040 |
|
|
|
5041 |
|
|
finished_state <= '0';
|
5042 |
|
|
refresh_done <= '0';
|
5043 |
|
|
|
5044 |
|
|
seq_ac_sel <= '1';
|
5045 |
|
|
if cal_complete = '1' then
|
5046 |
|
|
if cal_success = '1' or
|
5047 |
|
|
GENERATE_ADDITIONAL_DBG_RTL = 0 then -- hand over interface if cal successful or no debug enabled
|
5048 |
|
|
|
5049 |
|
|
seq_ac_sel <= '0';
|
5050 |
|
|
|
5051 |
|
|
end if;
|
5052 |
|
|
end if;
|
5053 |
|
|
|
5054 |
|
|
if state = s_reset then
|
5055 |
|
|
|
5056 |
|
|
addr_cmd <= reset(c_seq_addr_cmd_config);
|
5057 |
|
|
stage_counter <= 0;
|
5058 |
|
|
|
5059 |
|
|
elsif state /= s_run_init_seq and
|
5060 |
|
|
state /= s_non_operational then
|
5061 |
|
|
|
5062 |
|
|
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
|
5063 |
|
|
addr_cmd); -- previous value
|
5064 |
|
|
|
5065 |
|
|
end if;
|
5066 |
|
|
|
5067 |
|
|
if (stage_counter = 1 or stage_counter = 0) then
|
5068 |
|
|
stage_counter_zero <= '1';
|
5069 |
|
|
else
|
5070 |
|
|
stage_counter_zero <= '0';
|
5071 |
|
|
end if;
|
5072 |
|
|
|
5073 |
|
|
if stage_counter_zero /= '1' and state /= s_reset then
|
5074 |
|
|
stage_counter <= stage_counter -1;
|
5075 |
|
|
else
|
5076 |
|
|
stage_counter_zero <= '0';
|
5077 |
|
|
case state is
|
5078 |
|
|
|
5079 |
|
|
when s_run_init_seq =>
|
5080 |
|
|
|
5081 |
|
|
per_cs_init_seen <= (others => '0'); -- per cs test
|
5082 |
|
|
|
5083 |
|
|
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
|
5084 |
|
|
|
5085 |
|
|
case ac_state is
|
5086 |
|
|
|
5087 |
|
|
-- JEDEC (JESD79-2E) stage c
|
5088 |
|
|
when s_0 to s_9 =>
|
5089 |
|
|
ac_state <= t_ac_state'succ(ac_state);
|
5090 |
|
|
stage_counter <= (TINIT_TCK/10)+1;
|
5091 |
|
|
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
|
5092 |
|
|
deselect(c_seq_addr_cmd_config, addr_cmd),
|
5093 |
|
|
2**MEM_IF_NUM_RANKS -1);
|
5094 |
|
|
|
5095 |
|
|
-- JEDEC (JESD79-2E) stage d
|
5096 |
|
|
when s_10 =>
|
5097 |
|
|
ac_state <= s_11;
|
5098 |
|
|
stage_counter <= c_init_prech_delay;
|
5099 |
|
|
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
|
5100 |
|
|
addr_cmd); -- previous value
|
5101 |
|
|
|
5102 |
|
|
when s_11 =>
|
5103 |
|
|
ac_state <= s_0;
|
5104 |
|
|
stage_counter <= 1;
|
5105 |
|
|
finished_state <= '1';
|
5106 |
|
|
-- finish sequence by going into s_program_cal_mrs state
|
5107 |
|
|
|
5108 |
|
|
when others =>
|
5109 |
|
|
ac_state <= s_0;
|
5110 |
|
|
end case;
|
5111 |
|
|
|
5112 |
|
|
elsif MEM_IF_MEMTYPE = "DDR3" then -- DDR3 specific initialisation sequence
|
5113 |
|
|
|
5114 |
|
|
case ac_state is
|
5115 |
|
|
|
5116 |
|
|
when s_0 =>
|
5117 |
|
|
ac_state <= s_1;
|
5118 |
|
|
stage_counter <= TINIT_RST + 1;
|
5119 |
|
|
addr_cmd <= reset(c_seq_addr_cmd_config);
|
5120 |
|
|
|
5121 |
|
|
when s_1 to s_10 =>
|
5122 |
|
|
ac_state <= t_ac_state'succ(ac_state);
|
5123 |
|
|
stage_counter <= (TINIT_TCK/10) + 1;
|
5124 |
|
|
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
|
5125 |
|
|
deselect(c_seq_addr_cmd_config, addr_cmd),
|
5126 |
|
|
2**MEM_IF_NUM_RANKS -1);
|
5127 |
|
|
|
5128 |
|
|
when s_11 =>
|
5129 |
|
|
ac_state <= s_12;
|
5130 |
|
|
stage_counter <= c_init_prech_delay;
|
5131 |
|
|
addr_cmd <= deselect(c_seq_addr_cmd_config, addr_cmd);
|
5132 |
|
|
|
5133 |
|
|
when s_12 =>
|
5134 |
|
|
ac_state <= s_0;
|
5135 |
|
|
stage_counter <= 1;
|
5136 |
|
|
finished_state <= '1';
|
5137 |
|
|
-- finish sequence by going into s_program_cal_mrs state
|
5138 |
|
|
|
5139 |
|
|
when others =>
|
5140 |
|
|
ac_state <= s_0;
|
5141 |
|
|
|
5142 |
|
|
end case;
|
5143 |
|
|
|
5144 |
|
|
else
|
5145 |
|
|
|
5146 |
|
|
report admin_report_prefix & "unsupported memory type specified" severity error;
|
5147 |
|
|
|
5148 |
|
|
end if;
|
5149 |
|
|
-- end of initialisation sequence
|
5150 |
|
|
|
5151 |
|
|
when s_program_cal_mrs =>
|
5152 |
|
|
|
5153 |
|
|
if MEM_IF_MEMTYPE = "DDR2" then -- DDR2 style mode register settings
|
5154 |
|
|
case ac_state is
|
5155 |
|
|
when s_0 =>
|
5156 |
|
|
ac_state <= s_1;
|
5157 |
|
|
stage_counter <= 1;
|
5158 |
|
|
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
|
5159 |
|
|
addr_cmd); -- previous value
|
5160 |
|
|
|
5161 |
|
|
-- JEDEC (JESD79-2E) stage d
|
5162 |
|
|
when s_1 =>
|
5163 |
|
|
ac_state <= s_2;
|
5164 |
|
|
stage_counter <= c_trp_in_clks;
|
5165 |
|
|
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
|
5166 |
|
|
2**current_cs); -- rank
|
5167 |
|
|
|
5168 |
|
|
-- JEDEC (JESD79-2E) stage e
|
5169 |
|
|
when s_2 =>
|
5170 |
|
|
ac_state <= s_3;
|
5171 |
|
|
stage_counter <= c_tmrd_in_clks;
|
5172 |
|
|
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
|
5173 |
|
|
2, -- mode register number
|
5174 |
|
|
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
|
5175 |
|
|
2**current_cs, -- rank
|
5176 |
|
|
false); -- remap address and bank address
|
5177 |
|
|
|
5178 |
|
|
-- JEDEC (JESD79-2E) stage f
|
5179 |
|
|
when s_3 =>
|
5180 |
|
|
ac_state <= s_4;
|
5181 |
|
|
stage_counter <= c_tmrd_in_clks;
|
5182 |
|
|
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
|
5183 |
|
|
3, -- mode register number
|
5184 |
|
|
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
|
5185 |
|
|
2**current_cs, -- rank
|
5186 |
|
|
false); -- remap address and bank address
|
5187 |
|
|
|
5188 |
|
|
-- JEDEC (JESD79-2E) stage g
|
5189 |
|
|
when s_4 =>
|
5190 |
|
|
ac_state <= s_5;
|
5191 |
|
|
stage_counter <= c_tmrd_in_clks;
|
5192 |
|
|
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
|
5193 |
|
|
v_mr_overload(0) := '0'; -- override DLL enable
|
5194 |
|
|
v_mr_overload(9 downto 7) := "000"; -- required in JESD79-2E (but not in JESD79-2B)
|
5195 |
|
|
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
|
5196 |
|
|
1, -- mode register number
|
5197 |
|
|
v_mr_overload , -- mode register value
|
5198 |
|
|
2**current_cs, -- rank
|
5199 |
|
|
false); -- remap address and bank address
|
5200 |
|
|
|
5201 |
|
|
-- JEDEC (JESD79-2E) stage h
|
5202 |
|
|
when s_5 =>
|
5203 |
|
|
ac_state <= s_6;
|
5204 |
|
|
stage_counter <= c_tmod_in_clks;
|
5205 |
|
|
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
|
5206 |
|
|
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
|
5207 |
|
|
2**current_cs, -- rank
|
5208 |
|
|
false); -- remap address and bank address
|
5209 |
|
|
|
5210 |
|
|
-- JEDEC (JESD79-2E) stage i
|
5211 |
|
|
when s_6 =>
|
5212 |
|
|
ac_state <= s_7;
|
5213 |
|
|
stage_counter <= c_trp_in_clks;
|
5214 |
|
|
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
|
5215 |
|
|
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
|
5216 |
|
|
|
5217 |
|
|
-- JEDEC (JESD79-2E) stage j
|
5218 |
|
|
when s_7 =>
|
5219 |
|
|
ac_state <= s_8;
|
5220 |
|
|
stage_counter <= c_trfc_min_in_clks;
|
5221 |
|
|
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
|
5222 |
|
|
addr_cmd, -- previous value
|
5223 |
|
|
2**current_cs); -- rank
|
5224 |
|
|
|
5225 |
|
|
-- JEDEC (JESD79-2E) stage j - second refresh
|
5226 |
|
|
when s_8 =>
|
5227 |
|
|
ac_state <= s_9;
|
5228 |
|
|
stage_counter <= c_trfc_min_in_clks;
|
5229 |
|
|
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
|
5230 |
|
|
addr_cmd, -- previous value
|
5231 |
|
|
2**current_cs); -- rank
|
5232 |
|
|
|
5233 |
|
|
-- JEDEC (JESD79-2E) stage k
|
5234 |
|
|
when s_9 =>
|
5235 |
|
|
ac_state <= s_10;
|
5236 |
|
|
stage_counter <= c_tmrd_in_clks;
|
5237 |
|
|
|
5238 |
|
|
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
|
5239 |
|
|
v_mr_overload(8) := '0'; -- required in JESD79-2E
|
5240 |
|
|
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
|
5241 |
|
|
0, -- mode register number
|
5242 |
|
|
v_mr_overload, -- mode register value
|
5243 |
|
|
2**current_cs, -- rank
|
5244 |
|
|
false); -- remap address and bank address
|
5245 |
|
|
|
5246 |
|
|
-- JEDEC (JESD79-2E) stage l - wait 200 cycles
|
5247 |
|
|
when s_10 =>
|
5248 |
|
|
ac_state <= s_11;
|
5249 |
|
|
stage_counter <= 200;
|
5250 |
|
|
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
|
5251 |
|
|
addr_cmd); -- previous value
|
5252 |
|
|
|
5253 |
|
|
-- JEDEC (JESD79-2E) stage l - OCD default
|
5254 |
|
|
when s_11 =>
|
5255 |
|
|
ac_state <= s_12;
|
5256 |
|
|
stage_counter <= c_tmrd_in_clks;
|
5257 |
|
|
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
|
5258 |
|
|
v_mr_overload(9 downto 7) := "111"; -- OCD calibration default (i.e. OCD unused)
|
5259 |
|
|
v_mr_overload(0) := '0'; -- override for DLL enable
|
5260 |
|
|
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
|
5261 |
|
|
1, -- mode register number
|
5262 |
|
|
v_mr_overload , -- mode register value
|
5263 |
|
|
2**current_cs, -- rank
|
5264 |
|
|
false); -- remap address and bank address
|
5265 |
|
|
|
5266 |
|
|
-- JEDEC (JESD79-2E) stage l - OCD cal exit
|
5267 |
|
|
when s_12 =>
|
5268 |
|
|
ac_state <= s_13;
|
5269 |
|
|
stage_counter <= c_tmod_in_clks;
|
5270 |
|
|
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
|
5271 |
|
|
v_mr_overload(9 downto 7) := "000"; -- OCD calibration exit
|
5272 |
|
|
v_mr_overload(0) := '0'; -- override for DLL enable
|
5273 |
|
|
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
|
5274 |
|
|
1, -- mode register number
|
5275 |
|
|
v_mr_overload , -- mode register value
|
5276 |
|
|
2**current_cs, -- rank
|
5277 |
|
|
false); -- remap address and bank address
|
5278 |
|
|
|
5279 |
|
|
per_cs_init_seen(current_cs) <= '1';
|
5280 |
|
|
|
5281 |
|
|
-- JEDEC (JESD79-2E) stage m - cal finished
|
5282 |
|
|
when s_13 =>
|
5283 |
|
|
ac_state <= s_0;
|
5284 |
|
|
stage_counter <= 1;
|
5285 |
|
|
finished_state <= '1';
|
5286 |
|
|
|
5287 |
|
|
when others =>
|
5288 |
|
|
null;
|
5289 |
|
|
end case;
|
5290 |
|
|
|
5291 |
|
|
elsif MEM_IF_MEMTYPE = "DDR" then -- DDR style mode register setting following JEDEC (JESD79E)
|
5292 |
|
|
|
5293 |
|
|
case ac_state is
|
5294 |
|
|
when s_0 =>
|
5295 |
|
|
ac_state <= s_1;
|
5296 |
|
|
stage_counter <= 1;
|
5297 |
|
|
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
|
5298 |
|
|
addr_cmd); -- previous value
|
5299 |
|
|
|
5300 |
|
|
when s_1 =>
|
5301 |
|
|
ac_state <= s_2;
|
5302 |
|
|
stage_counter <= c_trp_in_clks;
|
5303 |
|
|
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
|
5304 |
|
|
2**current_cs); -- rank(s)
|
5305 |
|
|
|
5306 |
|
|
when s_2 =>
|
5307 |
|
|
ac_state <= s_3;
|
5308 |
|
|
stage_counter <= c_tmrd_in_clks;
|
5309 |
|
|
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
|
5310 |
|
|
v_mr_overload(0) := '0'; -- override DLL enable
|
5311 |
|
|
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
|
5312 |
|
|
1, -- mode register number
|
5313 |
|
|
v_mr_overload , -- mode register value
|
5314 |
|
|
2**current_cs, -- rank
|
5315 |
|
|
false); -- remap address and bank address
|
5316 |
|
|
|
5317 |
|
|
when s_3 =>
|
5318 |
|
|
ac_state <= s_4;
|
5319 |
|
|
stage_counter <= c_tmod_in_clks;
|
5320 |
|
|
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
|
5321 |
|
|
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
|
5322 |
|
|
2**current_cs, -- rank
|
5323 |
|
|
false); -- remap address and bank address
|
5324 |
|
|
|
5325 |
|
|
when s_4 =>
|
5326 |
|
|
ac_state <= s_5;
|
5327 |
|
|
stage_counter <= c_trp_in_clks;
|
5328 |
|
|
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
|
5329 |
|
|
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
|
5330 |
|
|
|
5331 |
|
|
when s_5 =>
|
5332 |
|
|
ac_state <= s_6;
|
5333 |
|
|
stage_counter <= c_trfc_min_in_clks;
|
5334 |
|
|
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
|
5335 |
|
|
addr_cmd, -- previous value
|
5336 |
|
|
2**current_cs); -- rank
|
5337 |
|
|
|
5338 |
|
|
when s_6 =>
|
5339 |
|
|
ac_state <= s_7;
|
5340 |
|
|
stage_counter <= c_trfc_min_in_clks;
|
5341 |
|
|
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
|
5342 |
|
|
addr_cmd, -- previous value
|
5343 |
|
|
2**current_cs); -- rank
|
5344 |
|
|
|
5345 |
|
|
when s_7 =>
|
5346 |
|
|
ac_state <= s_8;
|
5347 |
|
|
stage_counter <= c_tmrd_in_clks;
|
5348 |
|
|
|
5349 |
|
|
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
|
5350 |
|
|
|
5351 |
|
|
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
|
5352 |
|
|
0, -- mode register number
|
5353 |
|
|
v_mr_overload, -- mode register value
|
5354 |
|
|
2**current_cs, -- rank
|
5355 |
|
|
false); -- remap address and bank address
|
5356 |
|
|
|
5357 |
|
|
when s_8 =>
|
5358 |
|
|
ac_state <= s_9;
|
5359 |
|
|
stage_counter <= 200;
|
5360 |
|
|
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
|
5361 |
|
|
addr_cmd); -- previous value
|
5362 |
|
|
|
5363 |
|
|
per_cs_init_seen(current_cs) <= '1';
|
5364 |
|
|
|
5365 |
|
|
when s_9 =>
|
5366 |
|
|
ac_state <= s_0;
|
5367 |
|
|
stage_counter <= 1;
|
5368 |
|
|
finished_state <= '1';
|
5369 |
|
|
|
5370 |
|
|
when others =>
|
5371 |
|
|
null;
|
5372 |
|
|
end case;
|
5373 |
|
|
|
5374 |
|
|
elsif MEM_IF_MEMTYPE = "DDR3" then
|
5375 |
|
|
|
5376 |
|
|
case ac_state is
|
5377 |
|
|
|
5378 |
|
|
when s_0 =>
|
5379 |
|
|
ac_state <= s_1;
|
5380 |
|
|
stage_counter <= c_trp_in_clks;
|
5381 |
|
|
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
|
5382 |
|
|
addr_cmd); -- previous value
|
5383 |
|
|
|
5384 |
|
|
when s_1 =>
|
5385 |
|
|
ac_state <= s_2;
|
5386 |
|
|
stage_counter <= c_tmrd_in_clks;
|
5387 |
|
|
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
|
5388 |
|
|
2, -- mode register number
|
5389 |
|
|
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
|
5390 |
|
|
2**current_cs, -- rank
|
5391 |
|
|
false); -- remap address and bank address
|
5392 |
|
|
|
5393 |
|
|
when s_2 =>
|
5394 |
|
|
ac_state <= s_3;
|
5395 |
|
|
stage_counter <= c_tmrd_in_clks;
|
5396 |
|
|
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
|
5397 |
|
|
3, -- mode register number
|
5398 |
|
|
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
|
5399 |
|
|
2**current_cs, -- rank
|
5400 |
|
|
false); -- remap address and bank address
|
5401 |
|
|
|
5402 |
|
|
when s_3 =>
|
5403 |
|
|
ac_state <= s_4;
|
5404 |
|
|
stage_counter <= c_tmrd_in_clks;
|
5405 |
|
|
|
5406 |
|
|
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
|
5407 |
|
|
v_mr_overload(0) := '0'; -- Override for DLL enable
|
5408 |
|
|
v_mr_overload(12) := '0'; -- output buffer enable.
|
5409 |
|
|
v_mr_overload(7) := '0'; -- Disable Write levelling
|
5410 |
|
|
|
5411 |
|
|
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
|
5412 |
|
|
1, -- mode register number
|
5413 |
|
|
v_mr_overload, -- mode register value
|
5414 |
|
|
2**current_cs, -- rank
|
5415 |
|
|
false); -- remap address and bank address
|
5416 |
|
|
|
5417 |
|
|
when s_4 =>
|
5418 |
|
|
ac_state <= s_5;
|
5419 |
|
|
stage_counter <= c_tmod_in_clks;
|
5420 |
|
|
|
5421 |
|
|
v_mr_overload := int_mr0(c_max_mode_reg_index downto 0);
|
5422 |
|
|
|
5423 |
|
|
v_mr_overload(1 downto 0) := "01"; -- override to on the fly burst length choice
|
5424 |
|
|
v_mr_overload(7) := '0'; -- test mode not enabled
|
5425 |
|
|
v_mr_overload(8) := '1'; -- DLL reset
|
5426 |
|
|
|
5427 |
|
|
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
|
5428 |
|
|
0, -- mode register number
|
5429 |
|
|
v_mr_overload, -- mode register value
|
5430 |
|
|
2**current_cs, -- rank
|
5431 |
|
|
false); -- remap address and bank address
|
5432 |
|
|
|
5433 |
|
|
|
5434 |
|
|
when s_5 =>
|
5435 |
|
|
ac_state <= s_6;
|
5436 |
|
|
stage_counter <= c_zq_init_duration_clks;
|
5437 |
|
|
addr_cmd <= ZQCL(c_seq_addr_cmd_config, -- configuration
|
5438 |
|
|
2**current_cs); -- rank
|
5439 |
|
|
|
5440 |
|
|
per_cs_init_seen(current_cs) <= '1';
|
5441 |
|
|
|
5442 |
|
|
when s_6 =>
|
5443 |
|
|
ac_state <= s_0;
|
5444 |
|
|
stage_counter <= 1;
|
5445 |
|
|
finished_state <= '1';
|
5446 |
|
|
|
5447 |
|
|
when others =>
|
5448 |
|
|
ac_state <= s_0;
|
5449 |
|
|
|
5450 |
|
|
end case;
|
5451 |
|
|
|
5452 |
|
|
else
|
5453 |
|
|
|
5454 |
|
|
report admin_report_prefix & "unsupported memory type specified" severity error;
|
5455 |
|
|
|
5456 |
|
|
end if;
|
5457 |
|
|
|
5458 |
|
|
-- end of s_program_cal_mrs case
|
5459 |
|
|
|
5460 |
|
|
when s_prog_user_mrs =>
|
5461 |
|
|
|
5462 |
|
|
case ac_state is
|
5463 |
|
|
when s_0 =>
|
5464 |
|
|
ac_state <= s_1;
|
5465 |
|
|
stage_counter <= 1;
|
5466 |
|
|
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
|
5467 |
|
|
addr_cmd); -- previous value
|
5468 |
|
|
|
5469 |
|
|
when s_1 =>
|
5470 |
|
|
|
5471 |
|
|
if MEM_IF_MEMTYPE = "DDR" then -- for DDR memory skip MR2/3 because not present
|
5472 |
|
|
ac_state <= s_4;
|
5473 |
|
|
else -- for DDR2/DDR3 all MRs programmed
|
5474 |
|
|
ac_state <= s_2;
|
5475 |
|
|
end if;
|
5476 |
|
|
|
5477 |
|
|
stage_counter <= c_trp_in_clks;
|
5478 |
|
|
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
|
5479 |
|
|
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
|
5480 |
|
|
|
5481 |
|
|
when s_2 =>
|
5482 |
|
|
ac_state <= s_3;
|
5483 |
|
|
stage_counter <= c_tmrd_in_clks;
|
5484 |
|
|
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
|
5485 |
|
|
2, -- mode register number
|
5486 |
|
|
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
|
5487 |
|
|
2**current_cs, -- rank
|
5488 |
|
|
false); -- remap address and bank address
|
5489 |
|
|
|
5490 |
|
|
when s_3 =>
|
5491 |
|
|
ac_state <= s_4;
|
5492 |
|
|
stage_counter <= c_tmrd_in_clks;
|
5493 |
|
|
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
|
5494 |
|
|
3, -- mode register number
|
5495 |
|
|
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
|
5496 |
|
|
2**current_cs, -- rank
|
5497 |
|
|
false); -- remap address and bank address
|
5498 |
|
|
|
5499 |
|
|
if to_integer(unsigned(int_mr3)) /= 0 then
|
5500 |
|
|
report admin_report_prefix & " mode register 3 is expected to have a value of 0 but has a value of : " &
|
5501 |
|
|
integer'image(to_integer(unsigned(int_mr3))) severity warning;
|
5502 |
|
|
end if;
|
5503 |
|
|
|
5504 |
|
|
when s_4 =>
|
5505 |
|
|
ac_state <= s_5;
|
5506 |
|
|
stage_counter <= c_tmrd_in_clks;
|
5507 |
|
|
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
|
5508 |
|
|
1, -- mode register number
|
5509 |
|
|
int_mr1(c_max_mode_reg_index downto 0), -- mode register value
|
5510 |
|
|
2**current_cs, -- rank
|
5511 |
|
|
false); -- remap address and bank address
|
5512 |
|
|
|
5513 |
|
|
if (MEM_IF_DQSN_EN = 0) and (int_mr1(10) = '0') and (MEM_IF_MEMTYPE = "DDR2") then
|
5514 |
|
|
report admin_report_prefix & "mode register and generic conflict:" & LF &
|
5515 |
|
|
"* generic MEM_IF_DQSN_EN is set to 'disable' DQSN" & LF &
|
5516 |
|
|
"* user mode register MEM_IF_MR1 bit 10 is set to 'enable' DQSN" severity warning;
|
5517 |
|
|
end if;
|
5518 |
|
|
|
5519 |
|
|
when s_5 =>
|
5520 |
|
|
ac_state <= s_6;
|
5521 |
|
|
stage_counter <= c_tmod_in_clks;
|
5522 |
|
|
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
|
5523 |
|
|
0, -- mode register number
|
5524 |
|
|
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
|
5525 |
|
|
2**current_cs, -- rank
|
5526 |
|
|
false); -- remap address and bank address
|
5527 |
|
|
|
5528 |
|
|
when s_6 =>
|
5529 |
|
|
ac_state <= s_7;
|
5530 |
|
|
stage_counter <= 1;
|
5531 |
|
|
|
5532 |
|
|
when s_7 =>
|
5533 |
|
|
ac_state <= s_0;
|
5534 |
|
|
stage_counter <= 1;
|
5535 |
|
|
finished_state <= '1';
|
5536 |
|
|
|
5537 |
|
|
when others =>
|
5538 |
|
|
ac_state <= s_0;
|
5539 |
|
|
|
5540 |
|
|
end case;
|
5541 |
|
|
|
5542 |
|
|
-- end of s_prog_user_mr case
|
5543 |
|
|
|
5544 |
|
|
when s_access_precharge =>
|
5545 |
|
|
|
5546 |
|
|
case ac_state is
|
5547 |
|
|
when s_0 =>
|
5548 |
|
|
ac_state <= s_1;
|
5549 |
|
|
stage_counter <= 8;
|
5550 |
|
|
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
|
5551 |
|
|
addr_cmd); -- previous value
|
5552 |
|
|
|
5553 |
|
|
when s_1 =>
|
5554 |
|
|
ac_state <= s_2;
|
5555 |
|
|
stage_counter <= c_trp_in_clks;
|
5556 |
|
|
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
|
5557 |
|
|
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
|
5558 |
|
|
|
5559 |
|
|
when s_2 =>
|
5560 |
|
|
ac_state <= s_0;
|
5561 |
|
|
stage_counter <= 1;
|
5562 |
|
|
finished_state <= '1';
|
5563 |
|
|
|
5564 |
|
|
when others =>
|
5565 |
|
|
ac_state <= s_0;
|
5566 |
|
|
end case;
|
5567 |
|
|
|
5568 |
|
|
when s_topup_refresh | s_refresh =>
|
5569 |
|
|
|
5570 |
|
|
case ac_state is
|
5571 |
|
|
when s_0 =>
|
5572 |
|
|
ac_state <= s_1;
|
5573 |
|
|
stage_counter <= 1;
|
5574 |
|
|
|
5575 |
|
|
when s_1 =>
|
5576 |
|
|
ac_state <= s_2;
|
5577 |
|
|
stage_counter <= 1;
|
5578 |
|
|
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
|
5579 |
|
|
addr_cmd, -- previous value
|
5580 |
|
|
2**MEM_IF_NUM_RANKS - 1); -- rank
|
5581 |
|
|
|
5582 |
|
|
when s_2 =>
|
5583 |
|
|
ac_state <= s_0;
|
5584 |
|
|
stage_counter <= 1;
|
5585 |
|
|
finished_state <= '1';
|
5586 |
|
|
|
5587 |
|
|
when others =>
|
5588 |
|
|
ac_state <= s_0;
|
5589 |
|
|
end case;
|
5590 |
|
|
|
5591 |
|
|
when s_topup_refresh_done | s_refresh_done =>
|
5592 |
|
|
|
5593 |
|
|
case ac_state is
|
5594 |
|
|
when s_0 =>
|
5595 |
|
|
ac_state <= s_1;
|
5596 |
|
|
stage_counter <= c_trfc_min_in_clks;
|
5597 |
|
|
refresh_done <= '1'; -- ensure trfc not violated
|
5598 |
|
|
when s_1 =>
|
5599 |
|
|
ac_state <= s_0;
|
5600 |
|
|
stage_counter <= 1;
|
5601 |
|
|
finished_state <= '1';
|
5602 |
|
|
|
5603 |
|
|
when others =>
|
5604 |
|
|
ac_state <= s_0;
|
5605 |
|
|
end case;
|
5606 |
|
|
|
5607 |
|
|
when s_zq_cal_short =>
|
5608 |
|
|
|
5609 |
|
|
case ac_state is
|
5610 |
|
|
when s_0 =>
|
5611 |
|
|
ac_state <= s_1;
|
5612 |
|
|
stage_counter <= 1;
|
5613 |
|
|
|
5614 |
|
|
when s_1 =>
|
5615 |
|
|
ac_state <= s_2;
|
5616 |
|
|
stage_counter <= c_tzqcs;
|
5617 |
|
|
addr_cmd <= ZQCS(c_seq_addr_cmd_config, -- configuration
|
5618 |
|
|
2**MEM_IF_NUM_RANKS - 1); -- all ranks
|
5619 |
|
|
|
5620 |
|
|
when s_2 =>
|
5621 |
|
|
ac_state <= s_0;
|
5622 |
|
|
stage_counter <= 1;
|
5623 |
|
|
finished_state <= '1';
|
5624 |
|
|
|
5625 |
|
|
when others =>
|
5626 |
|
|
ac_state <= s_0;
|
5627 |
|
|
|
5628 |
|
|
end case;
|
5629 |
|
|
|
5630 |
|
|
when s_access_act =>
|
5631 |
|
|
|
5632 |
|
|
case ac_state is
|
5633 |
|
|
when s_0 =>
|
5634 |
|
|
ac_state <= s_1;
|
5635 |
|
|
stage_counter <= c_trrd_min_in_clks;
|
5636 |
|
|
|
5637 |
|
|
when s_1 =>
|
5638 |
|
|
ac_state <= s_2;
|
5639 |
|
|
stage_counter <= c_trcd_min_in_clks;
|
5640 |
|
|
addr_cmd <= activate(c_seq_addr_cmd_config, -- configuration
|
5641 |
|
|
addr_cmd, -- previous value
|
5642 |
|
|
MEM_IF_CAL_BANK, -- bank
|
5643 |
|
|
MEM_IF_CAL_BASE_ROW, -- row address
|
5644 |
|
|
2**current_cs); -- rank
|
5645 |
|
|
|
5646 |
|
|
when s_2 =>
|
5647 |
|
|
ac_state <= s_0;
|
5648 |
|
|
stage_counter <= 1;
|
5649 |
|
|
finished_state <= '1';
|
5650 |
|
|
|
5651 |
|
|
when others =>
|
5652 |
|
|
ac_state <= s_0;
|
5653 |
|
|
end case;
|
5654 |
|
|
|
5655 |
|
|
-- counter to delay transition from s_idle to s_refresh - this is to ensure a refresh command is not sent
|
5656 |
|
|
-- just as we enter operational state (could cause a trfc violation)
|
5657 |
|
|
when s_dummy_wait =>
|
5658 |
|
|
|
5659 |
|
|
case ac_state is
|
5660 |
|
|
when s_0 =>
|
5661 |
|
|
ac_state <= s_1;
|
5662 |
|
|
stage_counter <= c_max_wait_value;
|
5663 |
|
|
|
5664 |
|
|
when s_1 =>
|
5665 |
|
|
ac_state <= s_0;
|
5666 |
|
|
stage_counter <= 1;
|
5667 |
|
|
finished_state <= '1';
|
5668 |
|
|
|
5669 |
|
|
when others =>
|
5670 |
|
|
ac_state <= s_0;
|
5671 |
|
|
end case;
|
5672 |
|
|
|
5673 |
|
|
when s_reset =>
|
5674 |
|
|
|
5675 |
|
|
stage_counter <= 1;
|
5676 |
|
|
|
5677 |
|
|
-- default some s_non_operational signals
|
5678 |
|
|
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
|
5679 |
|
|
nop_toggle_signal <= addr;
|
5680 |
|
|
nop_toggle_pin <= 0;
|
5681 |
|
|
nop_toggle_value <= '0';
|
5682 |
|
|
end if;
|
5683 |
|
|
|
5684 |
|
|
when s_non_operational => -- if failed then output a recognised pattern to the memory (Only executes if GENERATE_ADDITIONAL_DBG_RTL set)
|
5685 |
|
|
|
5686 |
|
|
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
|
5687 |
|
|
addr_cmd); -- previous value
|
5688 |
|
|
|
5689 |
|
|
if NON_OP_EVAL_MD = "PIN_FINDER" then -- toggle pins in turn for 200 memory clk cycles
|
5690 |
|
|
|
5691 |
|
|
stage_counter <= 200/(DWIDTH_RATIO/2); -- 200 mem_clk cycles
|
5692 |
|
|
|
5693 |
|
|
case nop_toggle_signal is
|
5694 |
|
|
|
5695 |
|
|
when addr =>
|
5696 |
|
|
|
5697 |
|
|
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, '0');
|
5698 |
|
|
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value, nop_toggle_pin);
|
5699 |
|
|
|
5700 |
|
|
nop_toggle_value <= not nop_toggle_value;
|
5701 |
|
|
|
5702 |
|
|
if nop_toggle_value = '1' then
|
5703 |
|
|
if nop_toggle_pin = MEM_IF_ADDR_WIDTH-1 then
|
5704 |
|
|
nop_toggle_signal <= ba;
|
5705 |
|
|
nop_toggle_pin <= 0;
|
5706 |
|
|
else
|
5707 |
|
|
nop_toggle_pin <= nop_toggle_pin + 1;
|
5708 |
|
|
end if;
|
5709 |
|
|
end if;
|
5710 |
|
|
|
5711 |
|
|
when ba =>
|
5712 |
|
|
|
5713 |
|
|
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, '0');
|
5714 |
|
|
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, nop_toggle_value, nop_toggle_pin);
|
5715 |
|
|
|
5716 |
|
|
nop_toggle_value <= not nop_toggle_value;
|
5717 |
|
|
|
5718 |
|
|
if nop_toggle_value = '1' then
|
5719 |
|
|
if nop_toggle_pin = MEM_IF_BANKADDR_WIDTH-1 then
|
5720 |
|
|
nop_toggle_signal <= cas_n;
|
5721 |
|
|
nop_toggle_pin <= 0;
|
5722 |
|
|
else
|
5723 |
|
|
nop_toggle_pin <= nop_toggle_pin + 1;
|
5724 |
|
|
end if;
|
5725 |
|
|
end if;
|
5726 |
|
|
|
5727 |
|
|
when cas_n =>
|
5728 |
|
|
|
5729 |
|
|
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, cas_n, nop_toggle_value);
|
5730 |
|
|
|
5731 |
|
|
nop_toggle_value <= not nop_toggle_value;
|
5732 |
|
|
|
5733 |
|
|
if nop_toggle_value = '1' then
|
5734 |
|
|
nop_toggle_signal <= ras_n;
|
5735 |
|
|
end if;
|
5736 |
|
|
|
5737 |
|
|
when ras_n =>
|
5738 |
|
|
|
5739 |
|
|
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ras_n, nop_toggle_value);
|
5740 |
|
|
|
5741 |
|
|
nop_toggle_value <= not nop_toggle_value;
|
5742 |
|
|
|
5743 |
|
|
if nop_toggle_value = '1' then
|
5744 |
|
|
nop_toggle_signal <= we_n;
|
5745 |
|
|
end if;
|
5746 |
|
|
|
5747 |
|
|
when we_n =>
|
5748 |
|
|
|
5749 |
|
|
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, we_n, nop_toggle_value);
|
5750 |
|
|
|
5751 |
|
|
nop_toggle_value <= not nop_toggle_value;
|
5752 |
|
|
|
5753 |
|
|
if nop_toggle_value = '1' then
|
5754 |
|
|
nop_toggle_signal <= addr;
|
5755 |
|
|
end if;
|
5756 |
|
|
|
5757 |
|
|
when others =>
|
5758 |
|
|
|
5759 |
|
|
report admin_report_prefix & " an attempt to toggle a non addr/cmd pin detected" severity failure;
|
5760 |
|
|
|
5761 |
|
|
end case;
|
5762 |
|
|
|
5763 |
|
|
elsif NON_OP_EVAL_MD = "SI_EVALUATOR" then -- toggle all addr/cmd pins at fmax
|
5764 |
|
|
|
5765 |
|
|
stage_counter <= 0; -- every mem_clk cycle
|
5766 |
|
|
stage_counter_zero <= '1';
|
5767 |
|
|
|
5768 |
|
|
v_nop_ac_0 := mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value);
|
5769 |
|
|
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ba, nop_toggle_value);
|
5770 |
|
|
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, we_n, nop_toggle_value);
|
5771 |
|
|
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ras_n, nop_toggle_value);
|
5772 |
|
|
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, cas_n, nop_toggle_value);
|
5773 |
|
|
|
5774 |
|
|
v_nop_ac_1 := mask (c_seq_addr_cmd_config, addr_cmd, addr, not nop_toggle_value);
|
5775 |
|
|
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ba, not nop_toggle_value);
|
5776 |
|
|
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, we_n, not nop_toggle_value);
|
5777 |
|
|
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ras_n, not nop_toggle_value);
|
5778 |
|
|
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, cas_n, not nop_toggle_value);
|
5779 |
|
|
|
5780 |
|
|
for i in 0 to DWIDTH_RATIO/2 - 1 loop
|
5781 |
|
|
if i mod 2 = 0 then
|
5782 |
|
|
addr_cmd(i) <= v_nop_ac_0(i);
|
5783 |
|
|
else
|
5784 |
|
|
addr_cmd(i) <= v_nop_ac_1(i);
|
5785 |
|
|
end if;
|
5786 |
|
|
end loop;
|
5787 |
|
|
|
5788 |
|
|
if DWIDTH_RATIO = 2 then
|
5789 |
|
|
nop_toggle_value <= not nop_toggle_value;
|
5790 |
|
|
end if;
|
5791 |
|
|
|
5792 |
|
|
else
|
5793 |
|
|
|
5794 |
|
|
report admin_report_prefix & "unknown non-operational evaluation mode " & NON_OP_EVAL_MD severity failure;
|
5795 |
|
|
|
5796 |
|
|
end if;
|
5797 |
|
|
|
5798 |
|
|
when others =>
|
5799 |
|
|
|
5800 |
|
|
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
|
5801 |
|
|
addr_cmd); -- previous value
|
5802 |
|
|
stage_counter <= 1;
|
5803 |
|
|
|
5804 |
|
|
end case;
|
5805 |
|
|
end if;
|
5806 |
|
|
|
5807 |
|
|
end if;
|
5808 |
|
|
end process;
|
5809 |
|
|
|
5810 |
|
|
-- -------------------------------------------------------------------
|
5811 |
|
|
-- output packing of mode register settings and enabling of ODT
|
5812 |
|
|
-- -------------------------------------------------------------------
|
5813 |
|
|
process (int_mr0, int_mr1, int_mr2, int_mr3, mem_init_complete)
|
5814 |
|
|
begin
|
5815 |
|
|
admin_regs_status_rec.mr0 <= int_mr0;
|
5816 |
|
|
admin_regs_status_rec.mr1 <= int_mr1;
|
5817 |
|
|
admin_regs_status_rec.mr2 <= int_mr2;
|
5818 |
|
|
admin_regs_status_rec.mr3 <= int_mr3;
|
5819 |
|
|
admin_regs_status_rec.init_done <= mem_init_complete;
|
5820 |
|
|
enable_odt <= int_mr1(2) or int_mr1(6); -- if ODT enabled in MR settings (i.e. MR1 bits 2 or 6 /= 0)
|
5821 |
|
|
end process;
|
5822 |
|
|
|
5823 |
|
|
-- --------------------------------------------------------------------------------
|
5824 |
|
|
-- generation of handshake signals with ctrl, dgrb and dgwb blocks (this includes
|
5825 |
|
|
-- command ack, command done for ctrl and access grant for dgrb/dgwb)
|
5826 |
|
|
-- --------------------------------------------------------------------------------
|
5827 |
|
|
process (rst_n, clk)
|
5828 |
|
|
begin
|
5829 |
|
|
if rst_n = '0' then
|
5830 |
|
|
|
5831 |
|
|
admin_ctrl <= defaults;
|
5832 |
|
|
ac_access_gnt <= '0';
|
5833 |
|
|
|
5834 |
|
|
elsif rising_edge(clk) then
|
5835 |
|
|
|
5836 |
|
|
admin_ctrl <= defaults;
|
5837 |
|
|
ac_access_gnt <= '0';
|
5838 |
|
|
|
5839 |
|
|
admin_ctrl.command_ack <= command_started;
|
5840 |
|
|
admin_ctrl.command_done <= command_done;
|
5841 |
|
|
|
5842 |
|
|
if state = s_access then
|
5843 |
|
|
ac_access_gnt <= '1';
|
5844 |
|
|
end if;
|
5845 |
|
|
|
5846 |
|
|
end if;
|
5847 |
|
|
|
5848 |
|
|
end process;
|
5849 |
|
|
|
5850 |
|
|
end architecture struct;
|
5851 |
|
|
--
|
5852 |
|
|
|
5853 |
|
|
-- -----------------------------------------------------------------------------
|
5854 |
|
|
-- Abstract : inferred ram for the non-levelling AFI PHY sequencer
|
5855 |
|
|
-- The inferred ram is used in the iram block to store
|
5856 |
|
|
-- debug information about the sequencer. It is variable in
|
5857 |
|
|
-- size based on the IRAM_AWIDTH generic and is of size
|
5858 |
|
|
-- 32 * (2 ** IRAM_ADDR_WIDTH) bits
|
5859 |
|
|
-- -----------------------------------------------------------------------------
|
5860 |
|
|
|
5861 |
|
|
library ieee;
|
5862 |
|
|
use ieee.std_logic_1164.all;
|
5863 |
|
|
use ieee.numeric_std.all;
|
5864 |
|
|
|
5865 |
|
|
library work;
|
5866 |
|
|
|
5867 |
|
|
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
|
5868 |
|
|
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
|
5869 |
|
|
-- for the stages of DRAM memory calibration.
|
5870 |
|
|
--
|
5871 |
|
|
use work.altera_ddr_phy_alt_mem_phy_record_pkg.all;
|
5872 |
|
|
|
5873 |
|
|
--
|
5874 |
|
|
entity altera_ddr_phy_alt_mem_phy_iram_ram IS
|
5875 |
|
|
generic (
|
5876 |
|
|
IRAM_AWIDTH : natural := 12
|
5877 |
|
|
);
|
5878 |
|
|
port (
|
5879 |
|
|
clk : in std_logic;
|
5880 |
|
|
rst_n : in std_logic;
|
5881 |
|
|
|
5882 |
|
|
-- ram ports
|
5883 |
|
|
addr : in unsigned(IRAM_AWIDTH-1 downto 0);
|
5884 |
|
|
wdata : in std_logic_vector(31 downto 0);
|
5885 |
|
|
write : in std_logic;
|
5886 |
|
|
rdata : out std_logic_vector(31 downto 0)
|
5887 |
|
|
);
|
5888 |
|
|
end entity;
|
5889 |
|
|
|
5890 |
|
|
--
|
5891 |
|
|
architecture struct of altera_ddr_phy_alt_mem_phy_iram_ram is
|
5892 |
|
|
|
5893 |
|
|
-- infer ram
|
5894 |
|
|
|
5895 |
|
|
constant c_max_ram_address : natural := 2**IRAM_AWIDTH -1;
|
5896 |
|
|
|
5897 |
|
|
-- registered ram signals
|
5898 |
|
|
signal addr_r : unsigned(IRAM_AWIDTH-1 downto 0);
|
5899 |
|
|
signal wdata_r : std_logic_vector(31 downto 0);
|
5900 |
|
|
signal write_r : std_logic;
|
5901 |
|
|
signal rdata_r : std_logic_vector(31 downto 0);
|
5902 |
|
|
|
5903 |
|
|
-- ram storage array
|
5904 |
|
|
type t_iram is array (0 to c_max_ram_address) of std_logic_vector(31 downto 0);
|
5905 |
|
|
signal iram_ram : t_iram;
|
5906 |
|
|
attribute altera_attribute : string;
|
5907 |
|
|
attribute altera_attribute of iram_ram : signal is "-name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ""OFF""";
|
5908 |
|
|
|
5909 |
|
|
begin -- architecture struct
|
5910 |
|
|
|
5911 |
|
|
-- inferred ram instance - standard ram logic
|
5912 |
|
|
process (clk, rst_n)
|
5913 |
|
|
begin
|
5914 |
|
|
if rst_n = '0' then
|
5915 |
|
|
rdata_r <= (others => '0');
|
5916 |
|
|
|
5917 |
|
|
elsif rising_edge(clk) then
|
5918 |
|
|
if write_r = '1' then
|
5919 |
|
|
iram_ram(to_integer(addr_r)) <= wdata_r;
|
5920 |
|
|
end if;
|
5921 |
|
|
|
5922 |
|
|
rdata_r <= iram_ram(to_integer(addr_r));
|
5923 |
|
|
end if;
|
5924 |
|
|
|
5925 |
|
|
end process;
|
5926 |
|
|
|
5927 |
|
|
-- register i/o for speed
|
5928 |
|
|
process (clk, rst_n)
|
5929 |
|
|
begin
|
5930 |
|
|
if rst_n = '0' then
|
5931 |
|
|
|
5932 |
|
|
rdata <= (others => '0');
|
5933 |
|
|
write_r <= '0';
|
5934 |
|
|
addr_r <= (others => '0');
|
5935 |
|
|
wdata_r <= (others => '0');
|
5936 |
|
|
|
5937 |
|
|
elsif rising_edge(clk) then
|
5938 |
|
|
|
5939 |
|
|
rdata <= rdata_r;
|
5940 |
|
|
write_r <= write;
|
5941 |
|
|
addr_r <= addr;
|
5942 |
|
|
wdata_r <= wdata;
|
5943 |
|
|
|
5944 |
|
|
end if;
|
5945 |
|
|
end process;
|
5946 |
|
|
|
5947 |
|
|
end architecture struct;
|
5948 |
|
|
--
|
5949 |
|
|
|
5950 |
|
|
-- -----------------------------------------------------------------------------
|
5951 |
|
|
-- Abstract : iram block for the non-levelling AFI PHY sequencer
|
5952 |
|
|
-- This block is an optional storage of debug information for
|
5953 |
|
|
-- the sequencer. In the current form the iram stores header
|
5954 |
|
|
-- information about the arrangement of the sequencer and pass/
|
5955 |
|
|
-- fail information for per-delay/phase/pin sweeps for the
|
5956 |
|
|
-- read resynch phase calibration stage. Support for debug of
|
5957 |
|
|
-- additional commands can be added at a later date
|
5958 |
|
|
-- -----------------------------------------------------------------------------
|
5959 |
|
|
|
5960 |
|
|
library ieee;
|
5961 |
|
|
use ieee.std_logic_1164.all;
|
5962 |
|
|
use ieee.numeric_std.all;
|
5963 |
|
|
|
5964 |
|
|
library work;
|
5965 |
|
|
|
5966 |
|
|
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
|
5967 |
|
|
-- registers for the mmi status registers and functions/procedures applied to the registers
|
5968 |
|
|
--
|
5969 |
|
|
use work.altera_ddr_phy_alt_mem_phy_regs_pkg.all;
|
5970 |
|
|
|
5971 |
|
|
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
|
5972 |
|
|
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
|
5973 |
|
|
-- for the stages of DRAM memory calibration.
|
5974 |
|
|
--
|
5975 |
|
|
use work.altera_ddr_phy_alt_mem_phy_record_pkg.all;
|
5976 |
|
|
|
5977 |
|
|
-- The altmemphy iram ram (alt_mem_phy_iram_ram) is an inferred ram memory to implement the debug
|
5978 |
|
|
-- iram ram block
|
5979 |
|
|
--
|
5980 |
|
|
use work.altera_ddr_phy_alt_mem_phy_iram_ram;
|
5981 |
|
|
|
5982 |
|
|
--
|
5983 |
|
|
entity altera_ddr_phy_alt_mem_phy_iram is
|
5984 |
|
|
generic (
|
5985 |
|
|
-- physical interface width definitions
|
5986 |
|
|
MEM_IF_MEMTYPE : string := "DDR2";
|
5987 |
|
|
FAMILYGROUP_ID : natural := 2;
|
5988 |
|
|
MEM_IF_DQS_WIDTH : natural := 9;
|
5989 |
|
|
MEM_IF_DQ_PER_DQS : natural := 8;
|
5990 |
|
|
MEM_IF_DWIDTH : natural := 72;
|
5991 |
|
|
MEM_IF_DM_WIDTH : natural := 9;
|
5992 |
|
|
MEM_IF_NUM_RANKS : natural := 1;
|
5993 |
|
|
IRAM_AWIDTH : natural := 12;
|
5994 |
|
|
REFRESH_COUNT_INIT : natural := 12;
|
5995 |
|
|
PRESET_RLAT : natural := 0;
|
5996 |
|
|
PLL_STEPS_PER_CYCLE : natural := 1;
|
5997 |
|
|
CAPABILITIES : natural := 0;
|
5998 |
|
|
IP_BUILDNUM : natural := 0
|
5999 |
|
|
);
|
6000 |
|
|
port (
|
6001 |
|
|
-- clk / reset
|
6002 |
|
|
clk : in std_logic;
|
6003 |
|
|
rst_n : in std_logic;
|
6004 |
|
|
|
6005 |
|
|
-- read interface from mmi block:
|
6006 |
|
|
mmi_iram : in t_iram_ctrl;
|
6007 |
|
|
mmi_iram_enable_writes : in std_logic;
|
6008 |
|
|
|
6009 |
|
|
--iram status signal (includes read data from iram)
|
6010 |
|
|
iram_status : out t_iram_stat;
|
6011 |
|
|
iram_push_done : out std_logic;
|
6012 |
|
|
|
6013 |
|
|
-- from ctrl block
|
6014 |
|
|
ctrl_iram : in t_ctrl_command;
|
6015 |
|
|
ctrl_iram_ihi_write : in std_logic;
|
6016 |
|
|
|
6017 |
|
|
-- from dgrb block
|
6018 |
|
|
dgrb_iram : in t_iram_push;
|
6019 |
|
|
|
6020 |
|
|
-- from admin block
|
6021 |
|
|
admin_regs_status_rec : in t_admin_stat;
|
6022 |
|
|
|
6023 |
|
|
-- current write position in the iram
|
6024 |
|
|
ctrl_idib_top : in natural range 0 to 2 ** IRAM_AWIDTH - 1;
|
6025 |
|
|
|
6026 |
|
|
ctrl_iram_push : in t_ctrl_iram;
|
6027 |
|
|
|
6028 |
|
|
-- the following signals are unused and reserved for future use
|
6029 |
|
|
ctrl_active_block : in t_ctrl_active_block;
|
6030 |
|
|
ctrl_calibration_stage : in std_logic_vector(7 downto 0);
|
6031 |
|
|
proc_iram : in t_iram_ctrl;
|
6032 |
|
|
setup_iram : in t_iram_ctrl;
|
6033 |
|
|
dgwb_iram : in t_iram_push
|
6034 |
|
|
);
|
6035 |
|
|
end entity;
|
6036 |
|
|
|
6037 |
|
|
--
|
6038 |
|
|
architecture struct of altera_ddr_phy_alt_mem_phy_iram is
|
6039 |
|
|
|
6040 |
|
|
-- -------------------------------------------
|
6041 |
|
|
-- IHI fields
|
6042 |
|
|
-- -------------------------------------------
|
6043 |
|
|
|
6044 |
|
|
-- memory type , Quartus Build No., Quartus release, sequencer architecture version :
|
6045 |
|
|
signal memtype : std_logic_vector(7 downto 0);
|
6046 |
|
|
signal ihi_self_description : std_logic_vector(31 downto 0);
|
6047 |
|
|
|
6048 |
|
|
signal ihi_self_description_extra : std_logic_vector(31 downto 0);
|
6049 |
|
|
|
6050 |
|
|
-- for iram address generation:
|
6051 |
|
|
signal curr_iram_offset : natural range 0 to 2 ** IRAM_AWIDTH - 1;
|
6052 |
|
|
|
6053 |
|
|
-- set read latency for iram_rdata_valid signal control:
|
6054 |
|
|
constant c_iram_rlat : natural := 3; -- iram read latency (increment if read pipelining added
|
6055 |
|
|
|
6056 |
|
|
-- for rdata valid generation:
|
6057 |
|
|
signal read_valid_ctr : natural range 0 to c_iram_rlat;
|
6058 |
|
|
signal iram_addr_r : unsigned(IRAM_AWIDTH downto 0);
|
6059 |
|
|
|
6060 |
|
|
constant c_ihi_phys_if_desc : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(MEM_IF_NUM_RANKS,8) & to_unsigned(MEM_IF_DM_WIDTH,8) & to_unsigned(MEM_IF_DQS_WIDTH,8) & to_unsigned(MEM_IF_DWIDTH,8));
|
6061 |
|
|
constant c_ihi_timing_info : std_logic_vector(31 downto 0) := X"DEADDEAD";
|
6062 |
|
|
|
6063 |
|
|
constant c_ihi_ctrl_ss_word2 : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(PRESET_RLAT,16) & X"0000");
|
6064 |
|
|
|
6065 |
|
|
-- IDIB header codes
|
6066 |
|
|
constant c_idib_header_code0 : std_logic_vector(7 downto 0) := X"4A";
|
6067 |
|
|
constant c_idib_footer_code : std_logic_vector(7 downto 0) := X"5A";
|
6068 |
|
|
|
6069 |
|
|
-- encoded Quartus version
|
6070 |
|
|
-- constant c_quartus_version : natural := 0; -- Quartus 7.2
|
6071 |
|
|
-- constant c_quartus_version : natural := 1; -- Quartus 8.0
|
6072 |
|
|
--constant c_quartus_version : natural := 2; -- Quartus 8.1
|
6073 |
|
|
--constant c_quartus_version : natural := 3; -- Quartus 9.0
|
6074 |
|
|
constant c_quartus_version : natural := 4; -- Quartus 9.0sp2
|
6075 |
|
|
-- constant c_quartus_version : natural := 114; -- reserved
|
6076 |
|
|
|
6077 |
|
|
-- allow for different variants for debug i/f
|
6078 |
|
|
constant c_dbg_if_version : natural := 2;
|
6079 |
|
|
|
6080 |
|
|
-- sequencer type 1 for levelling, 2 for non-levelling
|
6081 |
|
|
constant c_sequencer_type : natural := 2;
|
6082 |
|
|
-- a prefix for all report signals to identify phy and sequencer block
|
6083 |
|
|
--
|
6084 |
|
|
constant iram_report_prefix : string := "altera_ddr_phy_alt_mem_phy_seq (iram) : ";
|
6085 |
|
|
|
6086 |
|
|
-- -------------------------------------------
|
6087 |
|
|
-- signal and type declarations
|
6088 |
|
|
-- -------------------------------------------
|
6089 |
|
|
|
6090 |
|
|
type t_iram_state is ( s_reset, -- system reset
|
6091 |
|
|
s_pre_init_ram, -- identify pre-initialisation
|
6092 |
|
|
s_init_ram, -- zero all locations
|
6093 |
|
|
s_idle, -- default state
|
6094 |
|
|
s_word_access_ram, -- mmi access to the iram (post-calibration)
|
6095 |
|
|
s_word_fetch_ram_rdata, -- sample read data from RAM
|
6096 |
|
|
s_word_fetch_ram_rdata_r,-- register the sampling of data from RAM (to improve timing)
|
6097 |
|
|
s_word_complete, -- finalise iram ram write
|
6098 |
|
|
s_idib_header_write, -- when starting a command
|
6099 |
|
|
s_idib_header_inc_addr, -- address increment
|
6100 |
|
|
s_idib_footer_write, -- unique footer to indicate end of data
|
6101 |
|
|
s_cal_data_read, -- read RAM location (read occurs continuously from idle state)
|
6102 |
|
|
s_cal_data_read_r,
|
6103 |
|
|
s_cal_data_modify, -- modify RAM location (read occurs continuously)
|
6104 |
|
|
s_cal_data_write, -- write modified value back to RAM
|
6105 |
|
|
s_ihi_header_word0_wr, -- from 0 to 6 writing iram header info
|
6106 |
|
|
s_ihi_header_word1_wr,
|
6107 |
|
|
s_ihi_header_word2_wr,
|
6108 |
|
|
s_ihi_header_word3_wr,
|
6109 |
|
|
s_ihi_header_word4_wr,
|
6110 |
|
|
s_ihi_header_word5_wr,
|
6111 |
|
|
s_ihi_header_word6_wr,
|
6112 |
|
|
s_ihi_header_word7_wr-- end writing iram header info
|
6113 |
|
|
);
|
6114 |
|
|
|
6115 |
|
|
signal state : t_iram_state;
|
6116 |
|
|
|
6117 |
|
|
signal contested_access : std_logic;
|
6118 |
|
|
signal idib_header_count : std_logic_vector(7 downto 0);
|
6119 |
|
|
|
6120 |
|
|
-- register a new cmd request
|
6121 |
|
|
signal new_cmd : std_logic;
|
6122 |
|
|
signal cmd_processed : std_logic;
|
6123 |
|
|
|
6124 |
|
|
-- signals to control dgrb writes
|
6125 |
|
|
signal iram_modified_data : std_logic_vector(31 downto 0); -- scratchpad memory for read-modify-write
|
6126 |
|
|
|
6127 |
|
|
-- -------------------------------------------
|
6128 |
|
|
-- physical ram connections
|
6129 |
|
|
-- -------------------------------------------
|
6130 |
|
|
|
6131 |
|
|
-- Note that the iram_addr here is created IRAM_AWIDTH downto 0, and not
|
6132 |
|
|
-- IRAM_AWIDTH-1 downto 0. This means that the MSB is outside the addressable
|
6133 |
|
|
-- area of the RAM. The purpose of this is that this shall be our memory
|
6134 |
|
|
-- overflow bit. It shall be directly connected to the iram_out_of_memory flag
|
6135 |
|
|
|
6136 |
|
|
-- 32-bit interface port (read and write)
|
6137 |
|
|
signal iram_addr : unsigned(IRAM_AWIDTH downto 0);
|
6138 |
|
|
signal iram_wdata : std_logic_vector(31 downto 0);
|
6139 |
|
|
signal iram_rdata : std_logic_vector(31 downto 0);
|
6140 |
|
|
signal iram_write : std_logic;
|
6141 |
|
|
|
6142 |
|
|
-- signal generated external to the iram to say when read data is valid
|
6143 |
|
|
signal iram_rdata_valid : std_logic;
|
6144 |
|
|
|
6145 |
|
|
-- The FSM owns local storage that is loaded with the wdata/addr from the
|
6146 |
|
|
-- requesting sub-block, which is then fed to the iram's wdata/addr in turn
|
6147 |
|
|
-- until all data has gone across
|
6148 |
|
|
signal fsm_read : std_logic;
|
6149 |
|
|
|
6150 |
|
|
-- -------------------------------------------
|
6151 |
|
|
-- multiplexed push data
|
6152 |
|
|
-- -------------------------------------------
|
6153 |
|
|
signal iram_done : std_logic; -- unused
|
6154 |
|
|
signal iram_pushdata : std_logic_vector(31 downto 0);
|
6155 |
|
|
signal pending_push : std_logic; -- push data to RAM
|
6156 |
|
|
signal iram_wordnum : natural range 0 to 255;
|
6157 |
|
|
signal iram_bitnum : natural range 0 to 31;
|
6158 |
|
|
|
6159 |
|
|
begin -- architecture struct
|
6160 |
|
|
|
6161 |
|
|
-- -------------------------------------------
|
6162 |
|
|
-- iram ram instantiation
|
6163 |
|
|
-- -------------------------------------------
|
6164 |
|
|
-- Note that the IRAM_AWIDTH is the physical number of address bits that the RAM has.
|
6165 |
|
|
-- However, for out of range access detection purposes, an additional bit is added to
|
6166 |
|
|
-- the various address signals. The iRAM does not register any of its inputs as the addr,
|
6167 |
|
|
-- wdata etc are registered directly before being driven to it.
|
6168 |
|
|
|
6169 |
|
|
-- The dgrb accesses are of format read-modify-write to a single bit of a 32-bit word, the
|
6170 |
|
|
-- mmi reads and header writes are in 32-bit words
|
6171 |
|
|
|
6172 |
|
|
--
|
6173 |
|
|
ram : entity altera_ddr_phy_alt_mem_phy_iram_ram
|
6174 |
|
|
generic map (
|
6175 |
|
|
IRAM_AWIDTH => IRAM_AWIDTH
|
6176 |
|
|
)
|
6177 |
|
|
port map (
|
6178 |
|
|
clk => clk,
|
6179 |
|
|
rst_n => rst_n,
|
6180 |
|
|
addr => iram_addr(IRAM_AWIDTH-1 downto 0),
|
6181 |
|
|
wdata => iram_wdata,
|
6182 |
|
|
write => iram_write,
|
6183 |
|
|
rdata => iram_rdata
|
6184 |
|
|
);
|
6185 |
|
|
|
6186 |
|
|
-- -------------------------------------------
|
6187 |
|
|
-- IHI fields
|
6188 |
|
|
-- asynchronously
|
6189 |
|
|
-- -------------------------------------------
|
6190 |
|
|
|
6191 |
|
|
-- this field identifies the type of memory
|
6192 |
|
|
memtype <= X"03" when (MEM_IF_MEMTYPE = "DDR3") else
|
6193 |
|
|
X"02" when (MEM_IF_MEMTYPE = "DDR2") else
|
6194 |
|
|
X"01" when (MEM_IF_MEMTYPE = "DDR") else
|
6195 |
|
|
X"10" when (MEM_IF_MEMTYPE = "QDRII") else
|
6196 |
|
|
X"00" ;
|
6197 |
|
|
|
6198 |
|
|
-- this field indentifies the gross level description of the sequencer
|
6199 |
|
|
ihi_self_description <= memtype
|
6200 |
|
|
& std_logic_vector(to_unsigned(IP_BUILDNUM,8))
|
6201 |
|
|
& std_logic_vector(to_unsigned(c_quartus_version,8))
|
6202 |
|
|
& std_logic_vector(to_unsigned(c_dbg_if_version,8));
|
6203 |
|
|
|
6204 |
|
|
-- some extra information for the debug gui - sequencer type and familygroup
|
6205 |
|
|
ihi_self_description_extra <= std_logic_vector(to_unsigned(FAMILYGROUP_ID,4))
|
6206 |
|
|
& std_logic_vector(to_unsigned(c_sequencer_type,4))
|
6207 |
|
|
& x"000000";
|
6208 |
|
|
|
6209 |
|
|
|
6210 |
|
|
-- -------------------------------------------
|
6211 |
|
|
-- check for contested memory accesses
|
6212 |
|
|
-- -------------------------------------------
|
6213 |
|
|
|
6214 |
|
|
process(clk,rst_n)
|
6215 |
|
|
begin
|
6216 |
|
|
if rst_n = '0' then
|
6217 |
|
|
contested_access <= '0';
|
6218 |
|
|
elsif rising_edge(clk) then
|
6219 |
|
|
contested_access <= '0';
|
6220 |
|
|
|
6221 |
|
|
if mmi_iram.read = '1' and pending_push = '1' then
|
6222 |
|
|
report iram_report_prefix & "contested memory accesses to the iram" severity failure;
|
6223 |
|
|
contested_access <= '1';
|
6224 |
|
|
end if;
|
6225 |
|
|
|
6226 |
|
|
-- sanity checks
|
6227 |
|
|
if mmi_iram.write = '1' then
|
6228 |
|
|
report iram_report_prefix & "mmi writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
|
6229 |
|
|
end if;
|
6230 |
|
|
if dgwb_iram.iram_write = '1' then
|
6231 |
|
|
report iram_report_prefix & "dgwb writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
|
6232 |
|
|
end if;
|
6233 |
|
|
end if;
|
6234 |
|
|
end process;
|
6235 |
|
|
|
6236 |
|
|
-- -------------------------------------------
|
6237 |
|
|
-- mux push data and associated signals
|
6238 |
|
|
-- note: single bit taken for iram_pushdata because 1-bit read-modify-write to
|
6239 |
|
|
-- a 32-bit word in the ram. This interface style is maintained for future
|
6240 |
|
|
-- scalability / wider application of the iram block.
|
6241 |
|
|
-- -------------------------------------------
|
6242 |
|
|
|
6243 |
|
|
process(clk,rst_n)
|
6244 |
|
|
begin
|
6245 |
|
|
|
6246 |
|
|
if rst_n = '0' then
|
6247 |
|
|
|
6248 |
|
|
iram_done <= '0';
|
6249 |
|
|
iram_pushdata <= (others => '0');
|
6250 |
|
|
pending_push <= '0';
|
6251 |
|
|
iram_wordnum <= 0;
|
6252 |
|
|
iram_bitnum <= 0;
|
6253 |
|
|
|
6254 |
|
|
elsif rising_edge(clk) then
|
6255 |
|
|
|
6256 |
|
|
case curr_active_block(ctrl_iram.command) is
|
6257 |
|
|
|
6258 |
|
|
when dgrb =>
|
6259 |
|
|
iram_done <= dgrb_iram.iram_done;
|
6260 |
|
|
iram_pushdata <= dgrb_iram.iram_pushdata;
|
6261 |
|
|
pending_push <= dgrb_iram.iram_write;
|
6262 |
|
|
iram_wordnum <= dgrb_iram.iram_wordnum;
|
6263 |
|
|
iram_bitnum <= dgrb_iram.iram_bitnum;
|
6264 |
|
|
|
6265 |
|
|
when others => -- default dgrb
|
6266 |
|
|
iram_done <= dgrb_iram.iram_done;
|
6267 |
|
|
iram_pushdata <= dgrb_iram.iram_pushdata;
|
6268 |
|
|
pending_push <= dgrb_iram.iram_write;
|
6269 |
|
|
iram_wordnum <= dgrb_iram.iram_wordnum;
|
6270 |
|
|
iram_bitnum <= dgrb_iram.iram_bitnum;
|
6271 |
|
|
|
6272 |
|
|
end case;
|
6273 |
|
|
end if;
|
6274 |
|
|
|
6275 |
|
|
end process;
|
6276 |
|
|
|
6277 |
|
|
-- -------------------------------------------
|
6278 |
|
|
-- generate write signal for the ram
|
6279 |
|
|
-- -------------------------------------------
|
6280 |
|
|
|
6281 |
|
|
process(clk, rst_n)
|
6282 |
|
|
begin
|
6283 |
|
|
|
6284 |
|
|
if rst_n = '0' then
|
6285 |
|
|
iram_write <= '0';
|
6286 |
|
|
|
6287 |
|
|
elsif rising_edge(clk) then
|
6288 |
|
|
|
6289 |
|
|
case state is
|
6290 |
|
|
|
6291 |
|
|
when s_idle =>
|
6292 |
|
|
iram_write <= '0';
|
6293 |
|
|
|
6294 |
|
|
when s_pre_init_ram |
|
6295 |
|
|
s_init_ram =>
|
6296 |
|
|
iram_write <= '1';
|
6297 |
|
|
|
6298 |
|
|
when s_ihi_header_word0_wr |
|
6299 |
|
|
s_ihi_header_word1_wr |
|
6300 |
|
|
s_ihi_header_word2_wr |
|
6301 |
|
|
s_ihi_header_word3_wr |
|
6302 |
|
|
s_ihi_header_word4_wr |
|
6303 |
|
|
s_ihi_header_word5_wr |
|
6304 |
|
|
s_ihi_header_word6_wr |
|
6305 |
|
|
s_ihi_header_word7_wr =>
|
6306 |
|
|
iram_write <= '1';
|
6307 |
|
|
|
6308 |
|
|
when s_idib_header_write =>
|
6309 |
|
|
iram_write <= '1';
|
6310 |
|
|
|
6311 |
|
|
when s_idib_footer_write =>
|
6312 |
|
|
iram_write <= '1';
|
6313 |
|
|
|
6314 |
|
|
when s_cal_data_write =>
|
6315 |
|
|
iram_write <= '1';
|
6316 |
|
|
|
6317 |
|
|
when others =>
|
6318 |
|
|
iram_write <= '0'; -- default
|
6319 |
|
|
|
6320 |
|
|
end case;
|
6321 |
|
|
|
6322 |
|
|
end if;
|
6323 |
|
|
|
6324 |
|
|
end process;
|
6325 |
|
|
|
6326 |
|
|
-- -------------------------------------------
|
6327 |
|
|
-- generate wdata for the ram
|
6328 |
|
|
-- -------------------------------------------
|
6329 |
|
|
|
6330 |
|
|
process(clk, rst_n)
|
6331 |
|
|
variable v_current_cs : std_logic_vector(3 downto 0);
|
6332 |
|
|
variable v_mtp_alignment : std_logic_vector(0 downto 0);
|
6333 |
|
|
variable v_single_bit : std_logic;
|
6334 |
|
|
|
6335 |
|
|
begin
|
6336 |
|
|
|
6337 |
|
|
if rst_n = '0' then
|
6338 |
|
|
iram_wdata <= (others => '0');
|
6339 |
|
|
|
6340 |
|
|
elsif rising_edge(clk) then
|
6341 |
|
|
|
6342 |
|
|
case state is
|
6343 |
|
|
|
6344 |
|
|
when s_pre_init_ram |
|
6345 |
|
|
s_init_ram =>
|
6346 |
|
|
iram_wdata <= (others => '0');
|
6347 |
|
|
|
6348 |
|
|
when s_ihi_header_word0_wr =>
|
6349 |
|
|
iram_wdata <= ihi_self_description;
|
6350 |
|
|
|
6351 |
|
|
when s_ihi_header_word1_wr =>
|
6352 |
|
|
iram_wdata <= c_ihi_phys_if_desc;
|
6353 |
|
|
|
6354 |
|
|
when s_ihi_header_word2_wr =>
|
6355 |
|
|
iram_wdata <= c_ihi_timing_info;
|
6356 |
|
|
|
6357 |
|
|
when s_ihi_header_word3_wr =>
|
6358 |
|
|
iram_wdata <= ( others => '0');
|
6359 |
|
|
iram_wdata(admin_regs_status_rec.mr0'range) <= admin_regs_status_rec.mr0;
|
6360 |
|
|
iram_wdata(admin_regs_status_rec.mr1'high + 16 downto 16) <= admin_regs_status_rec.mr1;
|
6361 |
|
|
|
6362 |
|
|
when s_ihi_header_word4_wr =>
|
6363 |
|
|
iram_wdata <= ( others => '0');
|
6364 |
|
|
iram_wdata(admin_regs_status_rec.mr2'range) <= admin_regs_status_rec.mr2;
|
6365 |
|
|
iram_wdata(admin_regs_status_rec.mr3'high + 16 downto 16) <= admin_regs_status_rec.mr3;
|
6366 |
|
|
|
6367 |
|
|
when s_ihi_header_word5_wr =>
|
6368 |
|
|
iram_wdata <= c_ihi_ctrl_ss_word2;
|
6369 |
|
|
|
6370 |
|
|
when s_ihi_header_word6_wr =>
|
6371 |
|
|
iram_wdata <= std_logic_vector(to_unsigned(IRAM_AWIDTH,32)); -- tbd write the occupancy at end of cal
|
6372 |
|
|
|
6373 |
|
|
when s_ihi_header_word7_wr =>
|
6374 |
|
|
iram_wdata <= ihi_self_description_extra;
|
6375 |
|
|
|
6376 |
|
|
when s_idib_header_write =>
|
6377 |
|
|
|
6378 |
|
|
-- encode command_op for current operation
|
6379 |
|
|
v_current_cs := std_logic_vector(to_unsigned(ctrl_iram.command_op.current_cs, 4));
|
6380 |
|
|
v_mtp_alignment := std_logic_vector(to_unsigned(ctrl_iram.command_op.mtp_almt, 1));
|
6381 |
|
|
v_single_bit := ctrl_iram.command_op.single_bit;
|
6382 |
|
|
|
6383 |
|
|
iram_wdata <= encode_current_stage(ctrl_iram.command) & -- which command being executed (currently this should only be cmd_rrp_sweep (8 bits)
|
6384 |
|
|
v_current_cs & -- which chip select being processed (4 bits)
|
6385 |
|
|
v_mtp_alignment & -- currently used MTP alignment (1 bit)
|
6386 |
|
|
v_single_bit & -- is single bit calibration selected (1 bit) - used during MTP alignment
|
6387 |
|
|
"00" & -- RFU
|
6388 |
|
|
idib_header_count & -- unique ID to how many headers have been written (8 bits)
|
6389 |
|
|
c_idib_header_code0; -- unique ID for headers (8 bits)
|
6390 |
|
|
|
6391 |
|
|
when s_idib_footer_write =>
|
6392 |
|
|
|
6393 |
|
|
iram_wdata <= c_idib_footer_code & c_idib_footer_code & c_idib_footer_code & c_idib_footer_code;
|
6394 |
|
|
|
6395 |
|
|
when s_cal_data_modify =>
|
6396 |
|
|
|
6397 |
|
|
-- default don't overwrite
|
6398 |
|
|
iram_modified_data <= iram_rdata;
|
6399 |
|
|
|
6400 |
|
|
-- update iram data based on packing and write modes
|
6401 |
|
|
if ctrl_iram_push.packing_mode = dq_bitwise then
|
6402 |
|
|
|
6403 |
|
|
case ctrl_iram_push.write_mode is
|
6404 |
|
|
when overwrite_ram =>
|
6405 |
|
|
iram_modified_data(iram_bitnum) <= iram_pushdata(0);
|
6406 |
|
|
when or_into_ram =>
|
6407 |
|
|
iram_modified_data(iram_bitnum) <= iram_pushdata(0) or iram_rdata(0);
|
6408 |
|
|
when and_into_ram =>
|
6409 |
|
|
iram_modified_data(iram_bitnum) <= iram_pushdata(0) and iram_rdata(0);
|
6410 |
|
|
when others =>
|
6411 |
|
|
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
|
6412 |
|
|
" specified when generating iram write data" severity failure;
|
6413 |
|
|
end case;
|
6414 |
|
|
|
6415 |
|
|
elsif ctrl_iram_push.packing_mode = dq_wordwise then
|
6416 |
|
|
|
6417 |
|
|
case ctrl_iram_push.write_mode is
|
6418 |
|
|
when overwrite_ram =>
|
6419 |
|
|
iram_modified_data <= iram_pushdata;
|
6420 |
|
|
when or_into_ram =>
|
6421 |
|
|
iram_modified_data <= iram_pushdata or iram_rdata;
|
6422 |
|
|
when and_into_ram =>
|
6423 |
|
|
iram_modified_data <= iram_pushdata and iram_rdata;
|
6424 |
|
|
when others =>
|
6425 |
|
|
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
|
6426 |
|
|
" specified when generating iram write data" severity failure;
|
6427 |
|
|
end case;
|
6428 |
|
|
else
|
6429 |
|
|
report iram_report_prefix & "unidentified packing mode of " & t_iram_packing_mode'image(ctrl_iram_push.packing_mode) &
|
6430 |
|
|
" specified when generating iram write data" severity failure;
|
6431 |
|
|
end if;
|
6432 |
|
|
|
6433 |
|
|
|
6434 |
|
|
when s_cal_data_write =>
|
6435 |
|
|
iram_wdata <= iram_modified_data;
|
6436 |
|
|
|
6437 |
|
|
when others =>
|
6438 |
|
|
iram_wdata <= (others => '0');
|
6439 |
|
|
|
6440 |
|
|
end case;
|
6441 |
|
|
|
6442 |
|
|
end if;
|
6443 |
|
|
|
6444 |
|
|
end process;
|
6445 |
|
|
|
6446 |
|
|
-- -------------------------------------------
|
6447 |
|
|
-- generate addr for the ram
|
6448 |
|
|
-- -------------------------------------------
|
6449 |
|
|
|
6450 |
|
|
process(clk, rst_n)
|
6451 |
|
|
begin
|
6452 |
|
|
|
6453 |
|
|
if rst_n = '0' then
|
6454 |
|
|
iram_addr <= (others => '0');
|
6455 |
|
|
curr_iram_offset <= 0;
|
6456 |
|
|
|
6457 |
|
|
elsif rising_edge(clk) then
|
6458 |
|
|
|
6459 |
|
|
case (state) is
|
6460 |
|
|
|
6461 |
|
|
when s_idle =>
|
6462 |
|
|
if mmi_iram.read = '1' then -- pre-set mmi read location address
|
6463 |
|
|
|
6464 |
|
|
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
|
6465 |
|
|
|
6466 |
|
|
else -- default get next push data location from iram
|
6467 |
|
|
|
6468 |
|
|
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1);
|
6469 |
|
|
|
6470 |
|
|
end if;
|
6471 |
|
|
|
6472 |
|
|
when s_word_access_ram =>
|
6473 |
|
|
|
6474 |
|
|
-- calculate the address
|
6475 |
|
|
if mmi_iram.read = '1' then -- mmi access
|
6476 |
|
|
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
|
6477 |
|
|
end if;
|
6478 |
|
|
|
6479 |
|
|
|
6480 |
|
|
when s_ihi_header_word0_wr =>
|
6481 |
|
|
iram_addr <= (others => '0');
|
6482 |
|
|
|
6483 |
|
|
-- increment address for IHI word writes :
|
6484 |
|
|
when s_ihi_header_word1_wr |
|
6485 |
|
|
s_ihi_header_word2_wr |
|
6486 |
|
|
s_ihi_header_word3_wr |
|
6487 |
|
|
s_ihi_header_word4_wr |
|
6488 |
|
|
s_ihi_header_word5_wr |
|
6489 |
|
|
s_ihi_header_word6_wr |
|
6490 |
|
|
s_ihi_header_word7_wr =>
|
6491 |
|
|
iram_addr <= iram_addr + 1;
|
6492 |
|
|
|
6493 |
|
|
when s_idib_header_write =>
|
6494 |
|
|
iram_addr <= '0' & to_unsigned(ctrl_idib_top, IRAM_AWIDTH); -- Always write header at idib_top location
|
6495 |
|
|
|
6496 |
|
|
when s_idib_footer_write =>
|
6497 |
|
|
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1); -- active block communicates where to put the footer with done signal
|
6498 |
|
|
|
6499 |
|
|
when s_idib_header_inc_addr =>
|
6500 |
|
|
iram_addr <= iram_addr + 1;
|
6501 |
|
|
curr_iram_offset <= to_integer('0' & iram_addr) + 1;
|
6502 |
|
|
|
6503 |
|
|
when s_init_ram =>
|
6504 |
|
|
|
6505 |
|
|
if iram_addr(IRAM_AWIDTH) = '1' then
|
6506 |
|
|
iram_addr <= (others => '0'); -- this prevents erroneous out-of-mem flag after initialisation
|
6507 |
|
|
else
|
6508 |
|
|
iram_addr <= iram_addr + 1;
|
6509 |
|
|
end if;
|
6510 |
|
|
|
6511 |
|
|
when others =>
|
6512 |
|
|
iram_addr <= iram_addr;
|
6513 |
|
|
|
6514 |
|
|
end case;
|
6515 |
|
|
|
6516 |
|
|
end if;
|
6517 |
|
|
|
6518 |
|
|
end process;
|
6519 |
|
|
|
6520 |
|
|
-- -------------------------------------------
|
6521 |
|
|
-- generate new cmd signal to register the command_req signal
|
6522 |
|
|
-- -------------------------------------------
|
6523 |
|
|
|
6524 |
|
|
process(clk, rst_n)
|
6525 |
|
|
begin
|
6526 |
|
|
|
6527 |
|
|
if rst_n = '0' then
|
6528 |
|
|
new_cmd <= '0';
|
6529 |
|
|
|
6530 |
|
|
elsif rising_edge(clk) then
|
6531 |
|
|
|
6532 |
|
|
if ctrl_iram.command_req = '1' then
|
6533 |
|
|
|
6534 |
|
|
case ctrl_iram.command is
|
6535 |
|
|
|
6536 |
|
|
when cmd_rrp_sweep | -- only prompt new_cmd for commands we wish to write headers for
|
6537 |
|
|
cmd_rrp_seek |
|
6538 |
|
|
cmd_read_mtp |
|
6539 |
|
|
cmd_write_ihi =>
|
6540 |
|
|
|
6541 |
|
|
new_cmd <= '1';
|
6542 |
|
|
|
6543 |
|
|
when others =>
|
6544 |
|
|
|
6545 |
|
|
new_cmd <= '0';
|
6546 |
|
|
|
6547 |
|
|
end case;
|
6548 |
|
|
|
6549 |
|
|
end if;
|
6550 |
|
|
|
6551 |
|
|
if cmd_processed = '1' then
|
6552 |
|
|
new_cmd <= '0';
|
6553 |
|
|
end if;
|
6554 |
|
|
|
6555 |
|
|
end if;
|
6556 |
|
|
end process;
|
6557 |
|
|
|
6558 |
|
|
-- -------------------------------------------
|
6559 |
|
|
-- generate read valid signal which takes account of pipelining of reads
|
6560 |
|
|
-- -------------------------------------------
|
6561 |
|
|
|
6562 |
|
|
process(clk, rst_n)
|
6563 |
|
|
begin
|
6564 |
|
|
|
6565 |
|
|
if rst_n = '0' then
|
6566 |
|
|
iram_rdata_valid <= '0';
|
6567 |
|
|
read_valid_ctr <= 0;
|
6568 |
|
|
iram_addr_r <= (others => '0');
|
6569 |
|
|
|
6570 |
|
|
elsif rising_edge(clk) then
|
6571 |
|
|
|
6572 |
|
|
if read_valid_ctr < c_iram_rlat then
|
6573 |
|
|
iram_rdata_valid <= '0';
|
6574 |
|
|
read_valid_ctr <= read_valid_ctr + 1;
|
6575 |
|
|
else
|
6576 |
|
|
iram_rdata_valid <= '1';
|
6577 |
|
|
end if;
|
6578 |
|
|
|
6579 |
|
|
if to_integer(iram_addr) /= to_integer(iram_addr_r) or
|
6580 |
|
|
iram_write = '1' then
|
6581 |
|
|
read_valid_ctr <= 0;
|
6582 |
|
|
iram_rdata_valid <= '0';
|
6583 |
|
|
end if;
|
6584 |
|
|
|
6585 |
|
|
-- register iram address
|
6586 |
|
|
iram_addr_r <= iram_addr;
|
6587 |
|
|
|
6588 |
|
|
end if;
|
6589 |
|
|
end process;
|
6590 |
|
|
|
6591 |
|
|
|
6592 |
|
|
-- -------------------------------------------
|
6593 |
|
|
-- state machine
|
6594 |
|
|
-- -------------------------------------------
|
6595 |
|
|
|
6596 |
|
|
process(clk, rst_n)
|
6597 |
|
|
begin
|
6598 |
|
|
|
6599 |
|
|
if rst_n = '0' then
|
6600 |
|
|
state <= s_reset;
|
6601 |
|
|
cmd_processed <= '0';
|
6602 |
|
|
|
6603 |
|
|
elsif rising_edge(clk) then
|
6604 |
|
|
|
6605 |
|
|
cmd_processed <= '0';
|
6606 |
|
|
|
6607 |
|
|
case state is
|
6608 |
|
|
|
6609 |
|
|
when s_reset =>
|
6610 |
|
|
state <= s_pre_init_ram;
|
6611 |
|
|
|
6612 |
|
|
when s_pre_init_ram =>
|
6613 |
|
|
state <= s_init_ram;
|
6614 |
|
|
|
6615 |
|
|
-- remain in the init_ram state until all the ram locations have been zero'ed
|
6616 |
|
|
when s_init_ram =>
|
6617 |
|
|
|
6618 |
|
|
if iram_addr(IRAM_AWIDTH) = '1' then
|
6619 |
|
|
state <= s_idle;
|
6620 |
|
|
end if;
|
6621 |
|
|
|
6622 |
|
|
-- default state after reset
|
6623 |
|
|
when s_idle =>
|
6624 |
|
|
|
6625 |
|
|
if pending_push = '1' then
|
6626 |
|
|
|
6627 |
|
|
state <= s_cal_data_read;
|
6628 |
|
|
|
6629 |
|
|
elsif iram_done = '1' then
|
6630 |
|
|
|
6631 |
|
|
state <= s_idib_footer_write;
|
6632 |
|
|
|
6633 |
|
|
elsif new_cmd = '1' then
|
6634 |
|
|
|
6635 |
|
|
case ctrl_iram.command is
|
6636 |
|
|
|
6637 |
|
|
when cmd_rrp_sweep |
|
6638 |
|
|
cmd_rrp_seek |
|
6639 |
|
|
cmd_read_mtp => state <= s_idib_header_write;
|
6640 |
|
|
|
6641 |
|
|
when cmd_write_ihi => state <= s_ihi_header_word0_wr;
|
6642 |
|
|
|
6643 |
|
|
when others => state <= state;
|
6644 |
|
|
|
6645 |
|
|
end case;
|
6646 |
|
|
|
6647 |
|
|
cmd_processed <= '1';
|
6648 |
|
|
|
6649 |
|
|
elsif mmi_iram.read = '1' then
|
6650 |
|
|
|
6651 |
|
|
state <= s_word_access_ram;
|
6652 |
|
|
|
6653 |
|
|
end if;
|
6654 |
|
|
|
6655 |
|
|
-- mmi read accesses
|
6656 |
|
|
when s_word_access_ram => state <= s_word_fetch_ram_rdata;
|
6657 |
|
|
when s_word_fetch_ram_rdata => state <= s_word_fetch_ram_rdata_r;
|
6658 |
|
|
|
6659 |
|
|
when s_word_fetch_ram_rdata_r => if iram_rdata_valid = '1' then
|
6660 |
|
|
state <= s_word_complete;
|
6661 |
|
|
end if;
|
6662 |
|
|
|
6663 |
|
|
when s_word_complete => if iram_rdata_valid = '1' then -- return to idle when iram_rdata stable
|
6664 |
|
|
state <= s_idle;
|
6665 |
|
|
end if;
|
6666 |
|
|
|
6667 |
|
|
-- header write (currently only for cmp_rrp stage)
|
6668 |
|
|
when s_idib_header_write => state <= s_idib_header_inc_addr;
|
6669 |
|
|
when s_idib_header_inc_addr => state <= s_idle; -- return to idle to wait for push
|
6670 |
|
|
|
6671 |
|
|
when s_idib_footer_write => state <= s_word_complete;
|
6672 |
|
|
|
6673 |
|
|
-- push data accesses (only used by the dgrb block at present)
|
6674 |
|
|
when s_cal_data_read => state <= s_cal_data_read_r;
|
6675 |
|
|
|
6676 |
|
|
when s_cal_data_read_r => if iram_rdata_valid = '1' then
|
6677 |
|
|
state <= s_cal_data_modify;
|
6678 |
|
|
end if;
|
6679 |
|
|
|
6680 |
|
|
when s_cal_data_modify => state <= s_cal_data_write;
|
6681 |
|
|
when s_cal_data_write => state <= s_word_complete;
|
6682 |
|
|
|
6683 |
|
|
-- IHI Header write accesses
|
6684 |
|
|
when s_ihi_header_word0_wr => state <= s_ihi_header_word1_wr;
|
6685 |
|
|
when s_ihi_header_word1_wr => state <= s_ihi_header_word2_wr;
|
6686 |
|
|
when s_ihi_header_word2_wr => state <= s_ihi_header_word3_wr;
|
6687 |
|
|
when s_ihi_header_word3_wr => state <= s_ihi_header_word4_wr;
|
6688 |
|
|
when s_ihi_header_word4_wr => state <= s_ihi_header_word5_wr;
|
6689 |
|
|
when s_ihi_header_word5_wr => state <= s_ihi_header_word6_wr;
|
6690 |
|
|
when s_ihi_header_word6_wr => state <= s_ihi_header_word7_wr;
|
6691 |
|
|
when s_ihi_header_word7_wr => state <= s_idle;
|
6692 |
|
|
|
6693 |
|
|
when others => state <= state;
|
6694 |
|
|
|
6695 |
|
|
end case;
|
6696 |
|
|
|
6697 |
|
|
end if;
|
6698 |
|
|
|
6699 |
|
|
end process;
|
6700 |
|
|
|
6701 |
|
|
-- -------------------------------------------
|
6702 |
|
|
-- drive read data and responses back.
|
6703 |
|
|
-- -------------------------------------------
|
6704 |
|
|
|
6705 |
|
|
process(clk, rst_n)
|
6706 |
|
|
begin
|
6707 |
|
|
|
6708 |
|
|
if rst_n = '0' then
|
6709 |
|
|
iram_status <= defaults;
|
6710 |
|
|
iram_push_done <= '0';
|
6711 |
|
|
idib_header_count <= (others => '0');
|
6712 |
|
|
fsm_read <= '0';
|
6713 |
|
|
|
6714 |
|
|
elsif rising_edge(clk) then
|
6715 |
|
|
|
6716 |
|
|
-- defaults
|
6717 |
|
|
iram_status <= defaults;
|
6718 |
|
|
iram_status.done <= '0';
|
6719 |
|
|
iram_status.rdata <= (others => '0');
|
6720 |
|
|
iram_push_done <= '0';
|
6721 |
|
|
|
6722 |
|
|
|
6723 |
|
|
if state = s_init_ram then
|
6724 |
|
|
iram_status.out_of_mem <= '0';
|
6725 |
|
|
else
|
6726 |
|
|
iram_status.out_of_mem <= iram_addr(IRAM_AWIDTH);
|
6727 |
|
|
end if;
|
6728 |
|
|
|
6729 |
|
|
-- register read flag for 32 bit accesses
|
6730 |
|
|
if state = s_idle then
|
6731 |
|
|
|
6732 |
|
|
fsm_read <= mmi_iram.read;
|
6733 |
|
|
|
6734 |
|
|
end if;
|
6735 |
|
|
|
6736 |
|
|
if state = s_word_complete then
|
6737 |
|
|
|
6738 |
|
|
iram_status.done <= '1';
|
6739 |
|
|
|
6740 |
|
|
if fsm_read = '1' then
|
6741 |
|
|
iram_status.rdata <= iram_rdata;
|
6742 |
|
|
else
|
6743 |
|
|
iram_status.rdata <= (others => '0');
|
6744 |
|
|
end if;
|
6745 |
|
|
|
6746 |
|
|
end if;
|
6747 |
|
|
|
6748 |
|
|
-- if another access is ever presented while the FSM is busy, set the contested flag
|
6749 |
|
|
if contested_access = '1' then
|
6750 |
|
|
iram_status.contested_access <= '1';
|
6751 |
|
|
end if;
|
6752 |
|
|
|
6753 |
|
|
-- set (and keep set) the iram_init_done output once initialisation of the RAM is complete
|
6754 |
|
|
if (state /= s_init_ram) and (state /= s_pre_init_ram) and (state /= s_reset) then
|
6755 |
|
|
iram_status.init_done <= '1';
|
6756 |
|
|
end if;
|
6757 |
|
|
|
6758 |
|
|
if state = s_ihi_header_word7_wr then
|
6759 |
|
|
iram_push_done <= '1';
|
6760 |
|
|
end if;
|
6761 |
|
|
|
6762 |
|
|
-- if completing push or footer write then acknowledge
|
6763 |
|
|
if state = s_cal_data_modify or state = s_idib_footer_write then
|
6764 |
|
|
iram_push_done <= '1';
|
6765 |
|
|
end if;
|
6766 |
|
|
|
6767 |
|
|
-- increment IDIB header count each time a header is written
|
6768 |
|
|
if state = s_idib_header_write then
|
6769 |
|
|
idib_header_count <= std_logic_vector(unsigned(idib_header_count) + to_unsigned(1,idib_header_count'high +1));
|
6770 |
|
|
end if;
|
6771 |
|
|
|
6772 |
|
|
end if;
|
6773 |
|
|
|
6774 |
|
|
end process;
|
6775 |
|
|
|
6776 |
|
|
end architecture struct;
|
6777 |
|
|
--
|
6778 |
|
|
|
6779 |
|
|
-- -----------------------------------------------------------------------------
|
6780 |
|
|
-- Abstract : data gatherer (read bias) [dgrb] block for the non-levelling
|
6781 |
|
|
-- AFI PHY sequencer
|
6782 |
|
|
-- -----------------------------------------------------------------------------
|
6783 |
|
|
|
6784 |
|
|
|
6785 |
|
|
|
6786 |
|
|
library ieee;
|
6787 |
|
|
use ieee.std_logic_1164.all;
|
6788 |
|
|
use ieee.numeric_std.all;
|
6789 |
|
|
|
6790 |
|
|
library work;
|
6791 |
|
|
|
6792 |
|
|
|
6793 |
|
|
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
|
6794 |
|
|
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
|
6795 |
|
|
-- for the stages of DRAM memory calibration.
|
6796 |
|
|
--
|
6797 |
|
|
use work.altera_ddr_phy_alt_mem_phy_record_pkg.all;
|
6798 |
|
|
|
6799 |
|
|
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
|
6800 |
|
|
-- for iram writes during calibration
|
6801 |
|
|
--
|
6802 |
|
|
use work.altera_ddr_phy_alt_mem_phy_iram_addr_pkg.all;
|
6803 |
|
|
|
6804 |
|
|
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
|
6805 |
|
|
-- thoughout the sequencer and will not change (for constants which may change between sequencer
|
6806 |
|
|
-- instances generics are used)
|
6807 |
|
|
--
|
6808 |
|
|
use work.altera_ddr_phy_alt_mem_phy_constants_pkg.all;
|
6809 |
|
|
|
6810 |
|
|
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
|
6811 |
|
|
-- and command signals in one record and unify the functions operating on this record.
|
6812 |
|
|
--
|
6813 |
|
|
use work.altera_ddr_phy_alt_mem_phy_addr_cmd_pkg.all;
|
6814 |
|
|
|
6815 |
|
|
|
6816 |
|
|
--
|
6817 |
|
|
entity altera_ddr_phy_alt_mem_phy_dgrb is
|
6818 |
|
|
generic (
|
6819 |
|
|
MEM_IF_DQS_WIDTH : natural := 9;
|
6820 |
|
|
MEM_IF_DQ_PER_DQS : natural := 8;
|
6821 |
|
|
MEM_IF_DWIDTH : natural := 72;
|
6822 |
|
|
MEM_IF_DM_WIDTH : natural := 9;
|
6823 |
|
|
MEM_IF_DQS_CAPTURE : natural := 0;
|
6824 |
|
|
MEM_IF_ADDR_WIDTH : natural := 13;
|
6825 |
|
|
MEM_IF_BANKADDR_WIDTH : natural := 3;
|
6826 |
|
|
MEM_IF_NUM_RANKS : natural := 1;
|
6827 |
|
|
MEM_IF_MEMTYPE : string := "DDR2";
|
6828 |
|
|
|
6829 |
|
|
ADV_LAT_WIDTH : natural := 5;
|
6830 |
|
|
|
6831 |
|
|
CLOCK_INDEX_WIDTH : natural := 4;
|
6832 |
|
|
|
6833 |
|
|
DWIDTH_RATIO : natural := 4;
|
6834 |
|
|
PRESET_RLAT : natural := 0;
|
6835 |
|
|
|
6836 |
|
|
PLL_STEPS_PER_CYCLE : natural := 16; -- number of PLL phase steps per PHY clock cycle
|
6837 |
|
|
MAX_RSC_DRIFT_IN_PHASES : natural := 127;
|
6838 |
|
|
|
6839 |
|
|
SIM_TIME_REDUCTIONS : natural := 0;
|
6840 |
|
|
GENERATE_ADDITIONAL_DBG_RTL : natural := 1;
|
6841 |
|
|
|
6842 |
|
|
PRESET_CODVW_PHASE : natural := 0;
|
6843 |
|
|
PRESET_CODVW_SIZE : natural := 0;
|
6844 |
|
|
|
6845 |
|
|
-- base column address to which calibration data is written
|
6846 |
|
|
-- memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
|
6847 |
|
|
-- is assumed to contain the proper data
|
6848 |
|
|
MEM_IF_CAL_BANK : natural := 0; -- bank to which calibration data is written
|
6849 |
|
|
MEM_IF_CAL_BASE_COL : natural := 0;
|
6850 |
|
|
EN_OCT : natural := 0
|
6851 |
|
|
);
|
6852 |
|
|
port (
|
6853 |
|
|
-- clk / reset
|
6854 |
|
|
clk : in std_logic;
|
6855 |
|
|
rst_n : in std_logic;
|
6856 |
|
|
|
6857 |
|
|
-- control interface
|
6858 |
|
|
dgrb_ctrl : out t_ctrl_stat;
|
6859 |
|
|
ctrl_dgrb : in t_ctrl_command;
|
6860 |
|
|
parameterisation_rec : in t_algm_paramaterisation;
|
6861 |
|
|
|
6862 |
|
|
-- PLL reconfig interface
|
6863 |
|
|
phs_shft_busy : in std_logic;
|
6864 |
|
|
seq_pll_inc_dec_n : out std_logic;
|
6865 |
|
|
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
|
6866 |
|
|
seq_pll_start_reconfig : out std_logic;
|
6867 |
|
|
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
|
6868 |
|
|
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic / aka measure clock
|
6869 |
|
|
|
6870 |
|
|
-- iram 'push' interface
|
6871 |
|
|
dgrb_iram : out t_iram_push;
|
6872 |
|
|
iram_push_done : in std_logic;
|
6873 |
|
|
|
6874 |
|
|
-- addr/cmd output for write commands
|
6875 |
|
|
dgrb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
|
6876 |
|
|
|
6877 |
|
|
-- admin block req/gnt interface
|
6878 |
|
|
dgrb_ac_access_req : out std_logic;
|
6879 |
|
|
dgrb_ac_access_gnt : in std_logic;
|
6880 |
|
|
|
6881 |
|
|
-- read datapath latency controls
|
6882 |
|
|
seq_rdp_inc_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
|
6883 |
|
|
seq_rdp_dec_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
|
6884 |
|
|
|
6885 |
|
|
-- RDV latency controls
|
6886 |
|
|
seq_rdata_valid_lat_inc : out std_logic;
|
6887 |
|
|
seq_rdata_valid_lat_dec : out std_logic;
|
6888 |
|
|
|
6889 |
|
|
-- POA latency controls
|
6890 |
|
|
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
|
6891 |
|
|
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
|
6892 |
|
|
|
6893 |
|
|
-- read datapath interface
|
6894 |
|
|
rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0);
|
6895 |
|
|
rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
|
6896 |
|
|
doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
|
6897 |
|
|
rd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
|
6898 |
|
|
|
6899 |
|
|
-- advertised write latency
|
6900 |
|
|
wd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
|
6901 |
|
|
|
6902 |
|
|
-- OCT control
|
6903 |
|
|
seq_oct_value : out std_logic;
|
6904 |
|
|
dgrb_wdp_ovride : out std_logic;
|
6905 |
|
|
|
6906 |
|
|
-- mimic path interface
|
6907 |
|
|
seq_mmc_start : out std_logic;
|
6908 |
|
|
mmc_seq_done : in std_logic;
|
6909 |
|
|
mmc_seq_value : in std_logic;
|
6910 |
|
|
|
6911 |
|
|
-- scanchain interface (unused in ddr/ddr2 AFI PHY sequencer)
|
6912 |
|
|
dgrb_sc : out t_sc_int_ctrl;
|
6913 |
|
|
sc_dgrb_ack : in std_logic;
|
6914 |
|
|
|
6915 |
|
|
-- calibration byte lane select (RFU)
|
6916 |
|
|
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
|
6917 |
|
|
|
6918 |
|
|
-- odt settings per chip select
|
6919 |
|
|
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1);
|
6920 |
|
|
|
6921 |
|
|
-- signal to identify if a/c nt setting is correct (set after wr_lat calculation)
|
6922 |
|
|
-- NOTE: labelled nt for future scalability to quarter rate interfaces
|
6923 |
|
|
dgrb_ctrl_ac_nt_good : out std_logic;
|
6924 |
|
|
|
6925 |
|
|
-- status signals on calibrated cdvw
|
6926 |
|
|
dgrb_mmi : out t_dgrb_mmi
|
6927 |
|
|
);
|
6928 |
|
|
|
6929 |
|
|
end entity;
|
6930 |
|
|
|
6931 |
|
|
|
6932 |
|
|
--
|
6933 |
|
|
architecture struct of altera_ddr_phy_alt_mem_phy_dgrb is
|
6934 |
|
|
|
6935 |
|
|
-- ------------------------------------------------------------------
|
6936 |
|
|
-- constant declarations
|
6937 |
|
|
-- ------------------------------------------------------------------
|
6938 |
|
|
|
6939 |
|
|
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
|
6940 |
|
|
|
6941 |
|
|
-- command/result length
|
6942 |
|
|
constant c_command_result_len : natural := 8;
|
6943 |
|
|
|
6944 |
|
|
-- burst characteristics and latency characteristics
|
6945 |
|
|
constant c_max_read_lat : natural := 2**rd_lat'length - 1; -- maximum read latency in phy clock-cycles
|
6946 |
|
|
|
6947 |
|
|
-- training pattern characteristics
|
6948 |
|
|
constant c_cal_mtp_len : natural := 16;
|
6949 |
|
|
constant c_cal_mtp : std_logic_vector(c_cal_mtp_len - 1 downto 0) := x"30F5";
|
6950 |
|
|
constant c_cal_mtp_t : natural := c_cal_mtp_len / DWIDTH_RATIO; -- number of phy-clk cycles required to read BTP
|
6951 |
|
|
|
6952 |
|
|
-- read/write latency defaults
|
6953 |
|
|
constant c_default_rd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_rd_lat, ADV_LAT_WIDTH));
|
6954 |
|
|
constant c_default_wd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_wr_lat, ADV_LAT_WIDTH));
|
6955 |
|
|
|
6956 |
|
|
|
6957 |
|
|
-- Returns '1' when boolean b is True; '0' otherwise.
|
6958 |
|
|
function active_high(b : in boolean) return std_logic is
|
6959 |
|
|
variable r : std_logic;
|
6960 |
|
|
begin
|
6961 |
|
|
if b then
|
6962 |
|
|
r := '1';
|
6963 |
|
|
else
|
6964 |
|
|
r := '0';
|
6965 |
|
|
end if;
|
6966 |
|
|
|
6967 |
|
|
return r;
|
6968 |
|
|
end function;
|
6969 |
|
|
|
6970 |
|
|
|
6971 |
|
|
-- Return the number of clock periods the resync clock should sweep.
|
6972 |
|
|
--
|
6973 |
|
|
-- On half-rate systems and in DQS-capture based systems a 720
|
6974 |
|
|
-- to guarantee the resync window can be properly observed.
|
6975 |
|
|
function rsc_sweep_clk_periods return natural is
|
6976 |
|
|
variable v_num_periods : natural;
|
6977 |
|
|
begin
|
6978 |
|
|
if DWIDTH_RATIO = 2 then
|
6979 |
|
|
if MEM_IF_DQS_CAPTURE = 1 then -- families which use DQS capture require a 720 degree sweep for FR to show a window
|
6980 |
|
|
v_num_periods := 2;
|
6981 |
|
|
else
|
6982 |
|
|
v_num_periods := 1;
|
6983 |
|
|
end if;
|
6984 |
|
|
elsif DWIDTH_RATIO = 4 then
|
6985 |
|
|
v_num_periods := 2;
|
6986 |
|
|
else
|
6987 |
|
|
report "Unsupported DWIDTH_RATIO." severity failure;
|
6988 |
|
|
end if;
|
6989 |
|
|
|
6990 |
|
|
return v_num_periods;
|
6991 |
|
|
end function;
|
6992 |
|
|
|
6993 |
|
|
|
6994 |
|
|
-- window for PLL sweep
|
6995 |
|
|
constant c_max_phase_shifts : natural := rsc_sweep_clk_periods*PLL_STEPS_PER_CYCLE;
|
6996 |
|
|
|
6997 |
|
|
-- a prefix for all report signals to identify phy and sequencer block
|
6998 |
|
|
--
|
6999 |
|
|
constant dgrb_report_prefix : string := "altera_ddr_phy_alt_mem_phy_seq (dgrb) : ";
|
7000 |
|
|
|
7001 |
|
|
constant c_pll_phs_inc : std_logic := '1';
|
7002 |
|
|
constant c_pll_phs_dec : std_logic := not c_pll_phs_inc;
|
7003 |
|
|
|
7004 |
|
|
-- ------------------------------------------------------------------
|
7005 |
|
|
-- type declarations
|
7006 |
|
|
-- ------------------------------------------------------------------
|
7007 |
|
|
|
7008 |
|
|
-- dgrb main state machine
|
7009 |
|
|
type t_dgrb_state is (
|
7010 |
|
|
s_idle,
|
7011 |
|
|
s_wait_admin,
|
7012 |
|
|
s_release_admin,
|
7013 |
|
|
s_reset_cdvw,
|
7014 |
|
|
s_test_phases,
|
7015 |
|
|
s_read_mtp,
|
7016 |
|
|
s_seek_cdvw,
|
7017 |
|
|
s_rdata_valid_align,
|
7018 |
|
|
s_adv_rd_lat_setup,
|
7019 |
|
|
s_adv_rd_lat,
|
7020 |
|
|
s_adv_wd_lat,
|
7021 |
|
|
s_poa_cal,
|
7022 |
|
|
s_track
|
7023 |
|
|
);
|
7024 |
|
|
|
7025 |
|
|
-- dgrb state machine for addr/cmd signals
|
7026 |
|
|
type t_ac_state is (
|
7027 |
|
|
s_ac_idle,
|
7028 |
|
|
s_ac_relax,
|
7029 |
|
|
s_ac_read_mtp,
|
7030 |
|
|
s_ac_read_rdv,
|
7031 |
|
|
s_ac_read_poa_mtp,
|
7032 |
|
|
s_ac_read_wd_lat
|
7033 |
|
|
);
|
7034 |
|
|
|
7035 |
|
|
-- dgrb state machine for read resync phase calibration
|
7036 |
|
|
type t_resync_state is (
|
7037 |
|
|
s_rsc_idle,
|
7038 |
|
|
s_rsc_next_phase,
|
7039 |
|
|
s_rsc_test_phase,
|
7040 |
|
|
s_rsc_wait_for_idle_dimm,
|
7041 |
|
|
s_rsc_flush_datapath,
|
7042 |
|
|
s_rsc_test_dq,
|
7043 |
|
|
s_rsc_rewind_phase,
|
7044 |
|
|
s_rsc_reset_cdvw,
|
7045 |
|
|
s_rsc_cdvw_calc,
|
7046 |
|
|
s_rsc_cdvw_wait,
|
7047 |
|
|
s_rsc_seek_cdvw,
|
7048 |
|
|
s_rsc_wait_iram -- only entered if GENERATE_ADDITIONAL_DBG_RTL = 1
|
7049 |
|
|
);
|
7050 |
|
|
|
7051 |
|
|
-- record definitions for window processing
|
7052 |
|
|
type t_win_processing_status is ( calculating,
|
7053 |
|
|
valid_result,
|
7054 |
|
|
no_invalid_phases,
|
7055 |
|
|
multiple_equal_windows,
|
7056 |
|
|
no_valid_phases
|
7057 |
|
|
);
|
7058 |
|
|
|
7059 |
|
|
type t_window_processing is record
|
7060 |
|
|
working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
|
7061 |
|
|
first_good_edge : natural range 0 to c_max_phase_shifts - 1; -- pointer to first detected good edge
|
7062 |
|
|
current_window_start : natural range 0 to c_max_phase_shifts - 1;
|
7063 |
|
|
current_window_size : natural range 0 to c_max_phase_shifts - 1;
|
7064 |
|
|
current_window_centre : natural range 0 to c_max_phase_shifts - 1;
|
7065 |
|
|
largest_window_start : natural range 0 to c_max_phase_shifts - 1;
|
7066 |
|
|
largest_window_size : natural range 0 to c_max_phase_shifts - 1;
|
7067 |
|
|
largest_window_centre : natural range 0 to c_max_phase_shifts - 1;
|
7068 |
|
|
current_bit : natural range 0 to c_max_phase_shifts - 1;
|
7069 |
|
|
window_centre_update : std_logic;
|
7070 |
|
|
last_bit_value : std_logic;
|
7071 |
|
|
valid_phase_seen : boolean;
|
7072 |
|
|
invalid_phase_seen : boolean;
|
7073 |
|
|
first_cycle : boolean;
|
7074 |
|
|
multiple_eq_windows : boolean;
|
7075 |
|
|
found_a_good_edge : boolean;
|
7076 |
|
|
status : t_win_processing_status;
|
7077 |
|
|
windows_seen : natural range 0 to c_max_phase_shifts/2 - 1;
|
7078 |
|
|
end record;
|
7079 |
|
|
|
7080 |
|
|
-- ------------------------------------------------------------------
|
7081 |
|
|
-- function and procedure definitions
|
7082 |
|
|
-- ------------------------------------------------------------------
|
7083 |
|
|
|
7084 |
|
|
function str(v: std_logic_vector) return string is
|
7085 |
|
|
variable str_value : string (1 to v'length);
|
7086 |
|
|
variable str_len : integer;
|
7087 |
|
|
variable c : character;
|
7088 |
|
|
begin
|
7089 |
|
|
str_len := 1;
|
7090 |
|
|
for i in v'range loop
|
7091 |
|
|
case v(i) is
|
7092 |
|
|
when '0' => c := '0';
|
7093 |
|
|
when '1' => c := '1';
|
7094 |
|
|
when others => c := '?';
|
7095 |
|
|
end case;
|
7096 |
|
|
|
7097 |
|
|
str_value(str_len) := c;
|
7098 |
|
|
str_len := str_len + 1;
|
7099 |
|
|
end loop;
|
7100 |
|
|
return str_value;
|
7101 |
|
|
end str;
|
7102 |
|
|
|
7103 |
|
|
|
7104 |
|
|
-- functions and procedures for window processing
|
7105 |
|
|
|
7106 |
|
|
function defaults return t_window_processing is
|
7107 |
|
|
variable output : t_window_processing;
|
7108 |
|
|
begin
|
7109 |
|
|
output.working_window := (others => '1');
|
7110 |
|
|
output.last_bit_value := '1';
|
7111 |
|
|
output.first_good_edge := 0;
|
7112 |
|
|
output.current_window_start := 0;
|
7113 |
|
|
output.current_window_size := 0;
|
7114 |
|
|
output.current_window_centre := 0;
|
7115 |
|
|
output.largest_window_start := 0;
|
7116 |
|
|
output.largest_window_size := 0;
|
7117 |
|
|
output.largest_window_centre := 0;
|
7118 |
|
|
output.window_centre_update := '1';
|
7119 |
|
|
output.current_bit := 0;
|
7120 |
|
|
output.multiple_eq_windows := false;
|
7121 |
|
|
output.valid_phase_seen := false;
|
7122 |
|
|
output.invalid_phase_seen := false;
|
7123 |
|
|
output.found_a_good_edge := false;
|
7124 |
|
|
output.status := no_valid_phases;
|
7125 |
|
|
output.first_cycle := false;
|
7126 |
|
|
output.windows_seen := 0;
|
7127 |
|
|
return output;
|
7128 |
|
|
end function defaults;
|
7129 |
|
|
|
7130 |
|
|
|
7131 |
|
|
procedure initialise_window_for_proc ( working : inout t_window_processing ) is
|
7132 |
|
|
variable v_working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
|
7133 |
|
|
begin
|
7134 |
|
|
v_working_window := working.working_window;
|
7135 |
|
|
working := defaults;
|
7136 |
|
|
working.working_window := v_working_window;
|
7137 |
|
|
working.status := calculating;
|
7138 |
|
|
working.first_cycle := true;
|
7139 |
|
|
working.window_centre_update := '1';
|
7140 |
|
|
working.windows_seen := 0;
|
7141 |
|
|
end procedure initialise_window_for_proc;
|
7142 |
|
|
|
7143 |
|
|
|
7144 |
|
|
procedure shift_window (working : inout t_window_processing;
|
7145 |
|
|
num_phases : in natural range 1 to c_max_phase_shifts
|
7146 |
|
|
)
|
7147 |
|
|
is
|
7148 |
|
|
begin
|
7149 |
|
|
if working.working_window(0) = '0' then
|
7150 |
|
|
working.invalid_phase_seen := true;
|
7151 |
|
|
else
|
7152 |
|
|
working.valid_phase_seen := true;
|
7153 |
|
|
end if;
|
7154 |
|
|
|
7155 |
|
|
-- general bit serial shifting of window and incrementing of current bit counter.
|
7156 |
|
|
if working.current_bit < num_phases - 1 then
|
7157 |
|
|
working.current_bit := working.current_bit + 1;
|
7158 |
|
|
else
|
7159 |
|
|
working.current_bit := 0;
|
7160 |
|
|
end if;
|
7161 |
|
|
|
7162 |
|
|
working.last_bit_value := working.working_window(0);
|
7163 |
|
|
working.working_window := working.working_window(0) & working.working_window(working.working_window'high downto 1);
|
7164 |
|
|
|
7165 |
|
|
--synopsis translate_off
|
7166 |
|
|
-- for simulation to make it simpler to see IF we are not using all the bits in the window
|
7167 |
|
|
working.working_window(working.working_window'high) := 'H'; -- for visual debug
|
7168 |
|
|
--synopsis translate_on
|
7169 |
|
|
working.working_window(num_phases -1) := working.last_bit_value;
|
7170 |
|
|
|
7171 |
|
|
working.first_cycle := false;
|
7172 |
|
|
end procedure shift_window;
|
7173 |
|
|
|
7174 |
|
|
|
7175 |
|
|
procedure find_centre_of_largest_data_valid_window
|
7176 |
|
|
( working : inout t_window_processing;
|
7177 |
|
|
num_phases : in natural range 1 to c_max_phase_shifts
|
7178 |
|
|
) is
|
7179 |
|
|
begin
|
7180 |
|
|
if working.first_cycle = false then -- not first call to procedure, then handle end conditions
|
7181 |
|
|
if working.current_bit = 0 and working.found_a_good_edge = false then -- have been all way arround window (circular)
|
7182 |
|
|
if working.valid_phase_seen = false then
|
7183 |
|
|
working.status := no_valid_phases;
|
7184 |
|
|
elsif working.invalid_phase_seen = false then
|
7185 |
|
|
working.status := no_invalid_phases;
|
7186 |
|
|
end if;
|
7187 |
|
|
elsif working.current_bit = working.first_good_edge then -- if have found a good edge then complete a circular sweep to that edge
|
7188 |
|
|
if working.multiple_eq_windows = true then
|
7189 |
|
|
working.status := multiple_equal_windows;
|
7190 |
|
|
else
|
7191 |
|
|
working.status := valid_result;
|
7192 |
|
|
end if;
|
7193 |
|
|
end if;
|
7194 |
|
|
end if;
|
7195 |
|
|
|
7196 |
|
|
-- start of a window condition
|
7197 |
|
|
if working.last_bit_value = '0' and working.working_window(0) = '1' then
|
7198 |
|
|
working.current_window_start := working.current_bit;
|
7199 |
|
|
working.current_window_size := working.current_window_size + 1; -- equivalent to assigning to one because if not in a window then it is set to 0
|
7200 |
|
|
working.window_centre_update := not working.window_centre_update;
|
7201 |
|
|
working.current_window_centre := working.current_bit;
|
7202 |
|
|
|
7203 |
|
|
if working.found_a_good_edge /= true then -- if have not yet found a good edge then store this value
|
7204 |
|
|
working.first_good_edge := working.current_bit;
|
7205 |
|
|
working.found_a_good_edge := true;
|
7206 |
|
|
end if;
|
7207 |
|
|
|
7208 |
|
|
-- end of window conditions
|
7209 |
|
|
elsif working.last_bit_value = '1' and working.working_window(0) = '0' then
|
7210 |
|
|
|
7211 |
|
|
if working.current_window_size > working.largest_window_size then
|
7212 |
|
|
|
7213 |
|
|
working.largest_window_size := working.current_window_size;
|
7214 |
|
|
working.largest_window_start := working.current_window_start;
|
7215 |
|
|
working.largest_window_centre := working.current_window_centre;
|
7216 |
|
|
working.multiple_eq_windows := false;
|
7217 |
|
|
|
7218 |
|
|
elsif working.current_window_size = working.largest_window_size then
|
7219 |
|
|
|
7220 |
|
|
working.multiple_eq_windows := true;
|
7221 |
|
|
|
7222 |
|
|
end if;
|
7223 |
|
|
|
7224 |
|
|
-- put counter in here because start of window 1 is observed twice
|
7225 |
|
|
if working.found_a_good_edge = true then
|
7226 |
|
|
working.windows_seen := working.windows_seen + 1;
|
7227 |
|
|
end if;
|
7228 |
|
|
|
7229 |
|
|
working.current_window_size := 0;
|
7230 |
|
|
|
7231 |
|
|
elsif working.last_bit_value = '1' and working.working_window(0) = '1' and (working.found_a_good_edge = true) then --note operand in brackets is excessive but for may provide power savings and makes visual inspection of simulatuion easier
|
7232 |
|
|
|
7233 |
|
|
if working.window_centre_update = '1' then
|
7234 |
|
|
if working.current_window_centre < num_phases -1 then
|
7235 |
|
|
working.current_window_centre := working.current_window_centre + 1;
|
7236 |
|
|
else
|
7237 |
|
|
working.current_window_centre := 0;
|
7238 |
|
|
end if;
|
7239 |
|
|
end if;
|
7240 |
|
|
|
7241 |
|
|
working.window_centre_update := not working.window_centre_update;
|
7242 |
|
|
|
7243 |
|
|
working.current_window_size := working.current_window_size + 1;
|
7244 |
|
|
end if;
|
7245 |
|
|
|
7246 |
|
|
shift_window(working,num_phases);
|
7247 |
|
|
end procedure find_centre_of_largest_data_valid_window;
|
7248 |
|
|
|
7249 |
|
|
|
7250 |
|
|
procedure find_last_failing_phase
|
7251 |
|
|
( working : inout t_window_processing;
|
7252 |
|
|
num_phases : in natural range 1 to c_max_phase_shifts + 1
|
7253 |
|
|
) is
|
7254 |
|
|
begin
|
7255 |
|
|
if working.first_cycle = false then -- not first call to procedure
|
7256 |
|
|
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
|
7257 |
|
|
if working.valid_phase_seen = false then
|
7258 |
|
|
working.status := no_valid_phases;
|
7259 |
|
|
elsif working.invalid_phase_seen = false then
|
7260 |
|
|
working.status := no_invalid_phases;
|
7261 |
|
|
else
|
7262 |
|
|
working.status := valid_result;
|
7263 |
|
|
end if;
|
7264 |
|
|
end if;
|
7265 |
|
|
end if;
|
7266 |
|
|
|
7267 |
|
|
if working.working_window(1) = '1' and working.working_window(0) = '0' and working.status = calculating then
|
7268 |
|
|
working.current_window_start := working.current_bit;
|
7269 |
|
|
end if;
|
7270 |
|
|
|
7271 |
|
|
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
|
7272 |
|
|
end procedure find_last_failing_phase;
|
7273 |
|
|
|
7274 |
|
|
|
7275 |
|
|
procedure find_first_passing_phase
|
7276 |
|
|
( working : inout t_window_processing;
|
7277 |
|
|
num_phases : in natural range 1 to c_max_phase_shifts
|
7278 |
|
|
) is
|
7279 |
|
|
begin
|
7280 |
|
|
if working.first_cycle = false then -- not first call to procedure
|
7281 |
|
|
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
|
7282 |
|
|
if working.valid_phase_seen = false then
|
7283 |
|
|
working.status := no_valid_phases;
|
7284 |
|
|
elsif working.invalid_phase_seen = false then
|
7285 |
|
|
working.status := no_invalid_phases;
|
7286 |
|
|
else
|
7287 |
|
|
working.status := valid_result;
|
7288 |
|
|
end if;
|
7289 |
|
|
end if;
|
7290 |
|
|
end if;
|
7291 |
|
|
|
7292 |
|
|
if working.working_window(0) = '1' and working.last_bit_value = '0' and working.status = calculating then
|
7293 |
|
|
working.current_window_start := working.current_bit;
|
7294 |
|
|
end if;
|
7295 |
|
|
|
7296 |
|
|
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
|
7297 |
|
|
end procedure find_first_passing_phase;
|
7298 |
|
|
|
7299 |
|
|
|
7300 |
|
|
-- shift in current pass/fail result to the working window
|
7301 |
|
|
procedure shift_in(
|
7302 |
|
|
working : inout t_window_processing;
|
7303 |
|
|
status : in std_logic;
|
7304 |
|
|
num_phases : in natural range 1 to c_max_phase_shifts
|
7305 |
|
|
) is
|
7306 |
|
|
begin
|
7307 |
|
|
working.last_bit_value := working.working_window(0);
|
7308 |
|
|
working.working_window(num_phases-1 downto 0) := (working.working_window(0) and status) & working.working_window(num_phases-1 downto 1);
|
7309 |
|
|
end procedure;
|
7310 |
|
|
|
7311 |
|
|
-- The following function sets the width over which
|
7312 |
|
|
-- write latency should be repeated on the dq bus
|
7313 |
|
|
-- the default value is MEM_IF_DQ_PER_DQS
|
7314 |
|
|
function set_wlat_dq_rep_width return natural is
|
7315 |
|
|
begin
|
7316 |
|
|
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
|
7317 |
|
|
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
|
7318 |
|
|
return i*MEM_IF_DQ_PER_DQS;
|
7319 |
|
|
end if;
|
7320 |
|
|
end loop;
|
7321 |
|
|
report dgrb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
|
7322 |
|
|
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
|
7323 |
|
|
return MEM_IF_DQ_PER_DQS;
|
7324 |
|
|
end function;
|
7325 |
|
|
|
7326 |
|
|
constant C_WLAT_DQ_REP_WIDTH : natural := set_wlat_dq_rep_width;
|
7327 |
|
|
|
7328 |
|
|
-- extract PHY 'addr/cmd' to 'wdata_valid' write latency from current read data
|
7329 |
|
|
function wd_lat_from_rdata(signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0))
|
7330 |
|
|
return std_logic_vector is
|
7331 |
|
|
variable v_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
|
7332 |
|
|
begin
|
7333 |
|
|
v_wd_lat := (others => '0');
|
7334 |
|
|
|
7335 |
|
|
if C_WLAT_DQ_REP_WIDTH >= ADV_LAT_WIDTH then
|
7336 |
|
|
v_wd_lat := rdata(v_wd_lat'high downto 0);
|
7337 |
|
|
else
|
7338 |
|
|
v_wd_lat := (others => '0');
|
7339 |
|
|
v_wd_lat(C_WLAT_DQ_REP_WIDTH - 1 downto 0) := rdata(C_WLAT_DQ_REP_WIDTH - 1 downto 0);
|
7340 |
|
|
end if;
|
7341 |
|
|
|
7342 |
|
|
return v_wd_lat;
|
7343 |
|
|
end function;
|
7344 |
|
|
|
7345 |
|
|
-- check if rdata_valid is correctly aligned
|
7346 |
|
|
function rdata_valid_aligned(
|
7347 |
|
|
signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
|
7348 |
|
|
signal rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0)
|
7349 |
|
|
) return std_logic is
|
7350 |
|
|
|
7351 |
|
|
variable v_dq_rdata : std_logic_vector(DWIDTH_RATIO - 1 downto 0);
|
7352 |
|
|
variable v_aligned : std_logic;
|
7353 |
|
|
begin
|
7354 |
|
|
-- Look at data from a single DQ pin 0 (DWIDTH_RATIO data bits)
|
7355 |
|
|
for i in 0 to DWIDTH_RATIO - 1 loop
|
7356 |
|
|
v_dq_rdata(i) := rdata(i*MEM_IF_DWIDTH);
|
7357 |
|
|
end loop;
|
7358 |
|
|
|
7359 |
|
|
-- Check each alignment (necessary because in the HR case rdata can be in any alignment)
|
7360 |
|
|
v_aligned := '0';
|
7361 |
|
|
for i in 0 to DWIDTH_RATIO/2 - 1 loop
|
7362 |
|
|
if rdata_valid(i) = '1' then
|
7363 |
|
|
if v_dq_rdata(2*i + 1 downto 2*i) = "00" then
|
7364 |
|
|
v_aligned := '1';
|
7365 |
|
|
end if;
|
7366 |
|
|
end if;
|
7367 |
|
|
end loop;
|
7368 |
|
|
|
7369 |
|
|
return v_aligned;
|
7370 |
|
|
end function;
|
7371 |
|
|
|
7372 |
|
|
-- ------------------------------------------------------------------
|
7373 |
|
|
-- signal declarations
|
7374 |
|
|
-- ------------------------------------------------------------------
|
7375 |
|
|
|
7376 |
|
|
-- main state machine
|
7377 |
|
|
signal sig_dgrb_state : t_dgrb_state;
|
7378 |
|
|
signal sig_dgrb_last_state : t_dgrb_state;
|
7379 |
|
|
|
7380 |
|
|
signal sig_trk_req : t_resync_state;
|
7381 |
|
|
signal sig_rsc_req : t_resync_state;
|
7382 |
|
|
|
7383 |
|
|
-- centre of data-valid window process
|
7384 |
|
|
signal sig_cdvw_state : t_window_processing;
|
7385 |
|
|
|
7386 |
|
|
-- control signals for the address/command process
|
7387 |
|
|
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
|
7388 |
|
|
signal sig_ac_req : t_ac_state;
|
7389 |
|
|
signal sig_dimm_driving_dq : std_logic;
|
7390 |
|
|
signal sig_doing_rd : std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
|
7391 |
|
|
signal sig_ac_even : std_logic; -- odd/even count of PHY clock cycles.
|
7392 |
|
|
--
|
7393 |
|
|
-- sig_ac_even behaviour
|
7394 |
|
|
--
|
7395 |
|
|
-- ; ; ; ; ; ;
|
7396 |
|
|
-- ; _______ ; ; ; ; ;
|
7397 |
|
|
-- XXXXX / \ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
|
7398 |
|
|
-- addr/cmd XXXXXX CMD XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
|
7399 |
|
|
-- XXXXX \_______/ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
|
7400 |
|
|
-- ; ; ; ; ; ;
|
7401 |
|
|
-- ; ; ; ; ; ;
|
7402 |
|
|
-- _________ _________ _________
|
7403 |
|
|
-- sig_ac_even ____| |_________| |_________| |__________
|
7404 |
|
|
-- ; ; ; ; ; ;
|
7405 |
|
|
-- ; ; ; ; ; ;
|
7406 |
|
|
-- phy clk
|
7407 |
|
|
-- count (0) (1) (2) (3) (4)
|
7408 |
|
|
--
|
7409 |
|
|
--
|
7410 |
|
|
|
7411 |
|
|
-- resync related signals
|
7412 |
|
|
signal sig_rsc_ack : std_logic;
|
7413 |
|
|
signal sig_rsc_err : std_logic;
|
7414 |
|
|
signal sig_rsc_result : std_logic_vector(c_command_result_len - 1 downto 0 );
|
7415 |
|
|
|
7416 |
|
|
signal sig_rsc_cdvw_phase : std_logic;
|
7417 |
|
|
signal sig_rsc_cdvw_shift_in : std_logic;
|
7418 |
|
|
signal sig_rsc_cdvw_calc : std_logic;
|
7419 |
|
|
|
7420 |
|
|
signal sig_rsc_pll_start_reconfig : std_logic;
|
7421 |
|
|
signal sig_rsc_pll_inc_dec_n : std_logic;
|
7422 |
|
|
|
7423 |
|
|
signal sig_rsc_ac_access_req : std_logic; -- High when the resync block requires a training pattern to be read.
|
7424 |
|
|
|
7425 |
|
|
-- tracking related signals
|
7426 |
|
|
signal sig_trk_ack : std_logic;
|
7427 |
|
|
signal sig_trk_err : std_logic;
|
7428 |
|
|
signal sig_trk_result : std_logic_vector(c_command_result_len - 1 downto 0 );
|
7429 |
|
|
|
7430 |
|
|
signal sig_trk_cdvw_phase : std_logic;
|
7431 |
|
|
signal sig_trk_cdvw_shift_in : std_logic;
|
7432 |
|
|
signal sig_trk_cdvw_calc : std_logic;
|
7433 |
|
|
|
7434 |
|
|
signal sig_trk_pll_start_reconfig : std_logic;
|
7435 |
|
|
signal sig_trk_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
|
7436 |
|
|
signal sig_trk_pll_inc_dec_n : std_logic;
|
7437 |
|
|
|
7438 |
|
|
signal sig_trk_rsc_drift : integer range -MAX_RSC_DRIFT_IN_PHASES to MAX_RSC_DRIFT_IN_PHASES; -- stores total change in rsc phase from first calibration
|
7439 |
|
|
|
7440 |
|
|
-- phs_shft_busy could (potentially) be asynchronous
|
7441 |
|
|
-- triple register it for metastability hardening
|
7442 |
|
|
-- these signals are the taps on the shift register
|
7443 |
|
|
signal sig_phs_shft_busy : std_logic;
|
7444 |
|
|
signal sig_phs_shft_busy_1t : std_logic;
|
7445 |
|
|
signal sig_phs_shft_start : std_logic;
|
7446 |
|
|
signal sig_phs_shft_end : std_logic;
|
7447 |
|
|
|
7448 |
|
|
-- locally register crl_dgrb to minimise fan out
|
7449 |
|
|
signal ctrl_dgrb_r : t_ctrl_command;
|
7450 |
|
|
|
7451 |
|
|
-- command_op signals
|
7452 |
|
|
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1;
|
7453 |
|
|
signal current_mtp_almt : natural range 0 to 1;
|
7454 |
|
|
signal single_bit_cal : std_logic;
|
7455 |
|
|
|
7456 |
|
|
-- codvw status signals (packed into record and sent to mmi block)
|
7457 |
|
|
signal cal_codvw_phase : std_logic_vector(7 downto 0);
|
7458 |
|
|
signal codvw_trk_shift : std_logic_vector(11 downto 0);
|
7459 |
|
|
signal cal_codvw_size : std_logic_vector(7 downto 0);
|
7460 |
|
|
|
7461 |
|
|
-- error signal and result from main state machine (operations other than rsc or tracking)
|
7462 |
|
|
signal sig_cmd_err : std_logic;
|
7463 |
|
|
signal sig_cmd_result : std_logic_vector(c_command_result_len - 1 downto 0 );
|
7464 |
|
|
|
7465 |
|
|
|
7466 |
|
|
-- signals that the training pattern matched correctly on the last clock
|
7467 |
|
|
-- cycle.
|
7468 |
|
|
signal sig_dq_pin_ctr : natural range 0 to MEM_IF_DWIDTH - 1;
|
7469 |
|
|
signal sig_mtp_match : std_logic;
|
7470 |
|
|
|
7471 |
|
|
-- controls postamble match and timing.
|
7472 |
|
|
signal sig_poa_match_en : std_logic;
|
7473 |
|
|
signal sig_poa_match : std_logic;
|
7474 |
|
|
|
7475 |
|
|
-- postamble signals
|
7476 |
|
|
signal sig_poa_ack : std_logic; -- '1' for postamble block to acknowledge.
|
7477 |
|
|
|
7478 |
|
|
-- calibration byte lane select
|
7479 |
|
|
signal cal_byte_lanes : std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
|
7480 |
|
|
|
7481 |
|
|
signal codvw_grt_one_dvw : std_logic;
|
7482 |
|
|
|
7483 |
|
|
begin
|
7484 |
|
|
|
7485 |
|
|
-- some default signals (unused outputs)
|
7486 |
|
|
seq_rdp_inc_read_lat_1x <= (others => '0');
|
7487 |
|
|
seq_rdp_dec_read_lat_1x <= (others => '0');
|
7488 |
|
|
dgrb_sc <= defaults;
|
7489 |
|
|
|
7490 |
|
|
doing_rd <= sig_doing_rd;
|
7491 |
|
|
|
7492 |
|
|
-- pack record of codvw status signals
|
7493 |
|
|
dgrb_mmi.cal_codvw_phase <= cal_codvw_phase;
|
7494 |
|
|
dgrb_mmi.codvw_trk_shift <= codvw_trk_shift;
|
7495 |
|
|
dgrb_mmi.cal_codvw_size <= cal_codvw_size;
|
7496 |
|
|
dgrb_mmi.codvw_grt_one_dvw <= codvw_grt_one_dvw;
|
7497 |
|
|
|
7498 |
|
|
-- map some internal signals to outputs
|
7499 |
|
|
dgrb_ac <= sig_addr_cmd;
|
7500 |
|
|
|
7501 |
|
|
-- locally register crl_dgrb to minimise fan out
|
7502 |
|
|
process (clk, rst_n)
|
7503 |
|
|
begin
|
7504 |
|
|
if rst_n = '0' then
|
7505 |
|
|
ctrl_dgrb_r <= defaults;
|
7506 |
|
|
elsif rising_edge(clk) then
|
7507 |
|
|
ctrl_dgrb_r <= ctrl_dgrb;
|
7508 |
|
|
end if;
|
7509 |
|
|
end process;
|
7510 |
|
|
|
7511 |
|
|
-- generate the current_cs signal to track which cs accessed by PHY at any instance
|
7512 |
|
|
current_cs_proc : process (clk, rst_n)
|
7513 |
|
|
begin
|
7514 |
|
|
if rst_n = '0' then
|
7515 |
|
|
current_cs <= 0;
|
7516 |
|
|
current_mtp_almt <= 0;
|
7517 |
|
|
single_bit_cal <= '0';
|
7518 |
|
|
|
7519 |
|
|
cal_byte_lanes <= (others => '0');
|
7520 |
|
|
|
7521 |
|
|
elsif rising_edge(clk) then
|
7522 |
|
|
if ctrl_dgrb_r.command_req = '1' then
|
7523 |
|
|
current_cs <= ctrl_dgrb_r.command_op.current_cs;
|
7524 |
|
|
current_mtp_almt <= ctrl_dgrb_r.command_op.mtp_almt;
|
7525 |
|
|
single_bit_cal <= ctrl_dgrb_r.command_op.single_bit;
|
7526 |
|
|
end if;
|
7527 |
|
|
|
7528 |
|
|
-- mux byte lane select for given chip select
|
7529 |
|
|
for i in 0 to MEM_IF_DQS_WIDTH - 1 loop
|
7530 |
|
|
cal_byte_lanes(i) <= ctl_cal_byte_lanes((current_cs * MEM_IF_DQS_WIDTH) + i);
|
7531 |
|
|
end loop;
|
7532 |
|
|
|
7533 |
|
|
assert ctl_cal_byte_lanes(0) = '1' report dgrb_report_prefix & " Byte lane 0 (chip select 0) disable is not supported - ending simulation" severity failure;
|
7534 |
|
|
end if;
|
7535 |
|
|
end process;
|
7536 |
|
|
|
7537 |
|
|
|
7538 |
|
|
-- ------------------------------------------------------------------
|
7539 |
|
|
-- main state machine for dgrb architecture
|
7540 |
|
|
-- ------------------------------------------------------------------
|
7541 |
|
|
|
7542 |
|
|
dgrb_main_block : block
|
7543 |
|
|
signal sig_count : natural range 0 to 2**8 - 1;
|
7544 |
|
|
signal sig_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
|
7545 |
|
|
begin
|
7546 |
|
|
dgrb_state_proc : process(rst_n, clk)
|
7547 |
|
|
begin
|
7548 |
|
|
if rst_n = '0' then
|
7549 |
|
|
-- initialise state
|
7550 |
|
|
sig_dgrb_state <= s_idle;
|
7551 |
|
|
sig_dgrb_last_state <= s_idle;
|
7552 |
|
|
|
7553 |
|
|
sig_ac_req <= s_ac_idle;
|
7554 |
|
|
sig_rsc_req <= s_rsc_idle;
|
7555 |
|
|
|
7556 |
|
|
-- set up rd_lat defaults
|
7557 |
|
|
rd_lat <= c_default_rd_lat_slv;
|
7558 |
|
|
wd_lat <= c_default_wd_lat_slv;
|
7559 |
|
|
|
7560 |
|
|
-- set up rdata_valid latency control defaults
|
7561 |
|
|
seq_rdata_valid_lat_inc <= '0';
|
7562 |
|
|
seq_rdata_valid_lat_dec <= '0';
|
7563 |
|
|
|
7564 |
|
|
-- Set up our private signals
|
7565 |
|
|
sig_count <= 0;
|
7566 |
|
|
|
7567 |
|
|
-- error signals
|
7568 |
|
|
sig_cmd_err <= '0';
|
7569 |
|
|
sig_cmd_result <= (others => '0');
|
7570 |
|
|
|
7571 |
|
|
-- sig_wd_lat
|
7572 |
|
|
sig_wd_lat <= (others => '0');
|
7573 |
|
|
|
7574 |
|
|
-- status of the ac_nt alignment
|
7575 |
|
|
dgrb_ctrl_ac_nt_good <= '1';
|
7576 |
|
|
|
7577 |
|
|
elsif rising_edge(clk) then
|
7578 |
|
|
sig_dgrb_last_state <= sig_dgrb_state;
|
7579 |
|
|
sig_rsc_req <= s_rsc_idle;
|
7580 |
|
|
|
7581 |
|
|
-- set up rdata_valid latency control defaults
|
7582 |
|
|
seq_rdata_valid_lat_inc <= '0';
|
7583 |
|
|
seq_rdata_valid_lat_dec <= '0';
|
7584 |
|
|
|
7585 |
|
|
-- error signals
|
7586 |
|
|
sig_cmd_err <= '0';
|
7587 |
|
|
sig_cmd_result <= (others => '0');
|
7588 |
|
|
|
7589 |
|
|
-- register wd_lat output.
|
7590 |
|
|
wd_lat <= sig_wd_lat;
|
7591 |
|
|
|
7592 |
|
|
case sig_dgrb_state is
|
7593 |
|
|
when s_idle =>
|
7594 |
|
|
sig_count <= 0;
|
7595 |
|
|
|
7596 |
|
|
if ctrl_dgrb_r.command_req = '1' then
|
7597 |
|
|
if curr_active_block(ctrl_dgrb_r.command) = dgrb then
|
7598 |
|
|
sig_dgrb_state <= s_wait_admin;
|
7599 |
|
|
end if;
|
7600 |
|
|
end if;
|
7601 |
|
|
|
7602 |
|
|
sig_ac_req <= s_ac_idle;
|
7603 |
|
|
|
7604 |
|
|
|
7605 |
|
|
when s_wait_admin =>
|
7606 |
|
|
sig_dgrb_state <= s_wait_admin;
|
7607 |
|
|
|
7608 |
|
|
case ctrl_dgrb_r.command is
|
7609 |
|
|
|
7610 |
|
|
when cmd_read_mtp => sig_dgrb_state <= s_read_mtp;
|
7611 |
|
|
when cmd_rrp_reset => sig_dgrb_state <= s_reset_cdvw;
|
7612 |
|
|
when cmd_rrp_sweep => sig_dgrb_state <= s_test_phases;
|
7613 |
|
|
when cmd_rrp_seek => sig_dgrb_state <= s_seek_cdvw;
|
7614 |
|
|
when cmd_rdv => sig_dgrb_state <= s_rdata_valid_align;
|
7615 |
|
|
when cmd_prep_adv_rd_lat => sig_dgrb_state <= s_adv_rd_lat_setup;
|
7616 |
|
|
when cmd_prep_adv_wr_lat => sig_dgrb_state <= s_adv_wd_lat;
|
7617 |
|
|
when cmd_tr_due => sig_dgrb_state <= s_track;
|
7618 |
|
|
when cmd_poa => sig_dgrb_state <= s_poa_cal;
|
7619 |
|
|
|
7620 |
|
|
when others =>
|
7621 |
|
|
report dgrb_report_prefix & "unknown command" severity error;
|
7622 |
|
|
sig_dgrb_state <= s_idle;
|
7623 |
|
|
end case;
|
7624 |
|
|
|
7625 |
|
|
|
7626 |
|
|
when s_reset_cdvw =>
|
7627 |
|
|
-- the cdvw proc watches for this state and resets the cdvw
|
7628 |
|
|
-- state block.
|
7629 |
|
|
if sig_rsc_ack = '1' then
|
7630 |
|
|
sig_dgrb_state <= s_release_admin;
|
7631 |
|
|
else
|
7632 |
|
|
sig_rsc_req <= s_rsc_reset_cdvw;
|
7633 |
|
|
end if;
|
7634 |
|
|
|
7635 |
|
|
|
7636 |
|
|
when s_test_phases =>
|
7637 |
|
|
if sig_rsc_ack = '1' then
|
7638 |
|
|
sig_dgrb_state <= s_release_admin;
|
7639 |
|
|
else
|
7640 |
|
|
sig_rsc_req <= s_rsc_test_phase;
|
7641 |
|
|
if sig_rsc_ac_access_req = '1' then
|
7642 |
|
|
sig_ac_req <= s_ac_read_mtp;
|
7643 |
|
|
else
|
7644 |
|
|
sig_ac_req <= s_ac_idle;
|
7645 |
|
|
end if;
|
7646 |
|
|
end if;
|
7647 |
|
|
|
7648 |
|
|
|
7649 |
|
|
when s_seek_cdvw | s_read_mtp =>
|
7650 |
|
|
if sig_rsc_ack = '1' then
|
7651 |
|
|
sig_dgrb_state <= s_release_admin;
|
7652 |
|
|
else
|
7653 |
|
|
sig_rsc_req <= s_rsc_cdvw_calc;
|
7654 |
|
|
end if;
|
7655 |
|
|
|
7656 |
|
|
|
7657 |
|
|
when s_release_admin =>
|
7658 |
|
|
sig_ac_req <= s_ac_idle;
|
7659 |
|
|
|
7660 |
|
|
if dgrb_ac_access_gnt = '0' and sig_dimm_driving_dq = '0' then
|
7661 |
|
|
sig_dgrb_state <= s_idle;
|
7662 |
|
|
end if;
|
7663 |
|
|
|
7664 |
|
|
|
7665 |
|
|
when s_rdata_valid_align =>
|
7666 |
|
|
sig_ac_req <= s_ac_read_rdv;
|
7667 |
|
|
|
7668 |
|
|
seq_rdata_valid_lat_dec <= '0';
|
7669 |
|
|
seq_rdata_valid_lat_inc <= '0';
|
7670 |
|
|
|
7671 |
|
|
if sig_dimm_driving_dq = '1' then
|
7672 |
|
|
-- only do comparison if rdata_valid is all 'ones'
|
7673 |
|
|
if rdata_valid /= std_logic_vector(to_unsigned(0, DWIDTH_RATIO/2)) then
|
7674 |
|
|
-- rdata_valid is all ones
|
7675 |
|
|
if rdata_valid_aligned(rdata, rdata_valid) = '1' then
|
7676 |
|
|
-- success: rdata_valid and rdata are properly aligned
|
7677 |
|
|
sig_dgrb_state <= s_release_admin;
|
7678 |
|
|
else
|
7679 |
|
|
-- misaligned: bring in rdata_valid by a clock cycle
|
7680 |
|
|
seq_rdata_valid_lat_dec <= '1';
|
7681 |
|
|
end if;
|
7682 |
|
|
end if;
|
7683 |
|
|
end if;
|
7684 |
|
|
|
7685 |
|
|
|
7686 |
|
|
when s_adv_rd_lat_setup =>
|
7687 |
|
|
-- wait for sig_doing_rd to go high
|
7688 |
|
|
sig_ac_req <= s_ac_read_rdv;
|
7689 |
|
|
|
7690 |
|
|
if sig_dgrb_state /= sig_dgrb_last_state then
|
7691 |
|
|
rd_lat <= (others => '0');
|
7692 |
|
|
sig_count <= 0;
|
7693 |
|
|
elsif sig_dimm_driving_dq = '1' and sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) = '1' then
|
7694 |
|
|
-- a read has started: start counter
|
7695 |
|
|
sig_dgrb_state <= s_adv_rd_lat;
|
7696 |
|
|
end if;
|
7697 |
|
|
|
7698 |
|
|
|
7699 |
|
|
when s_adv_rd_lat =>
|
7700 |
|
|
sig_ac_req <= s_ac_read_rdv;
|
7701 |
|
|
|
7702 |
|
|
if sig_dimm_driving_dq = '1' then
|
7703 |
|
|
if sig_count >= 2**rd_lat'length then
|
7704 |
|
|
report dgrb_report_prefix & "maximum read latency exceeded while waiting for rdata_valid" severity warning;
|
7705 |
|
|
sig_cmd_err <= '1';
|
7706 |
|
|
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_MAX_RD_LAT_EXCEEDED,sig_cmd_result'length));
|
7707 |
|
|
end if;
|
7708 |
|
|
|
7709 |
|
|
if rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
|
7710 |
|
|
-- have found the read latency
|
7711 |
|
|
sig_dgrb_state <= s_release_admin;
|
7712 |
|
|
else
|
7713 |
|
|
sig_count <= sig_count + 1;
|
7714 |
|
|
end if;
|
7715 |
|
|
|
7716 |
|
|
rd_lat <= std_logic_vector(to_unsigned(sig_count, rd_lat'length));
|
7717 |
|
|
end if;
|
7718 |
|
|
|
7719 |
|
|
|
7720 |
|
|
when s_adv_wd_lat =>
|
7721 |
|
|
sig_ac_req <= s_ac_read_wd_lat;
|
7722 |
|
|
|
7723 |
|
|
if sig_dgrb_state /= sig_dgrb_last_state then
|
7724 |
|
|
sig_wd_lat <= (others => '0');
|
7725 |
|
|
else
|
7726 |
|
|
if sig_dimm_driving_dq = '1' and rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
|
7727 |
|
|
-- construct wd_lat using data from the lowest addresses
|
7728 |
|
|
-- wd_lat <= rdata(MEM_IF_DQ_PER_DQS - 1 downto 0);
|
7729 |
|
|
sig_wd_lat <= wd_lat_from_rdata(rdata);
|
7730 |
|
|
sig_dgrb_state <= s_release_admin;
|
7731 |
|
|
|
7732 |
|
|
-- check data integrity
|
7733 |
|
|
for i in 1 to MEM_IF_DWIDTH/C_WLAT_DQ_REP_WIDTH - 1 loop
|
7734 |
|
|
-- wd_lat is copied across MEM_IF_DWIDTH bits in fields of width MEM_IF_DQ_PER_DQS.
|
7735 |
|
|
-- All of these fields must have the same value or it is an error.
|
7736 |
|
|
|
7737 |
|
|
-- only check if byte lane not disabled
|
7738 |
|
|
if cal_byte_lanes((i*C_WLAT_DQ_REP_WIDTH)/MEM_IF_DQ_PER_DQS) = '1' then
|
7739 |
|
|
|
7740 |
|
|
if rdata(C_WLAT_DQ_REP_WIDTH - 1 downto 0) /= rdata((i+1)*C_WLAT_DQ_REP_WIDTH - 1 downto i*C_WLAT_DQ_REP_WIDTH) then
|
7741 |
|
|
-- signal write latency different between DQS groups
|
7742 |
|
|
report dgrb_report_prefix & "the write latency read from memory is different accross dqs groups" severity warning;
|
7743 |
|
|
sig_cmd_err <= '1';
|
7744 |
|
|
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_WD_LAT_DISAGREEMENT, sig_cmd_result'length));
|
7745 |
|
|
end if;
|
7746 |
|
|
end if;
|
7747 |
|
|
|
7748 |
|
|
end loop;
|
7749 |
|
|
|
7750 |
|
|
-- check if ac_nt alignment is ok
|
7751 |
|
|
-- in this condition all DWIDTH_RATIO copies of rdata should be identical
|
7752 |
|
|
dgrb_ctrl_ac_nt_good <= '1';
|
7753 |
|
|
if DWIDTH_RATIO /= 2 then
|
7754 |
|
|
for j in 0 to DWIDTH_RATIO/2 - 1 loop
|
7755 |
|
|
if rdata(j*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto j*MEM_IF_DWIDTH) /= rdata((j+2)*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto (j+2)*MEM_IF_DWIDTH) then
|
7756 |
|
|
dgrb_ctrl_ac_nt_good <= '0';
|
7757 |
|
|
end if;
|
7758 |
|
|
end loop;
|
7759 |
|
|
end if;
|
7760 |
|
|
|
7761 |
|
|
end if;
|
7762 |
|
|
end if;
|
7763 |
|
|
|
7764 |
|
|
|
7765 |
|
|
when s_poa_cal =>
|
7766 |
|
|
-- Request the address/command block begins reading the "M"
|
7767 |
|
|
-- training pattern here. There is no provision for doing
|
7768 |
|
|
-- refreshes so this limits the time spent in this state
|
7769 |
|
|
-- to 9 x tREFI (by the DDR2 JEDEC spec). Instead of the
|
7770 |
|
|
-- maximum value, a maximum "safe" time in this postamble
|
7771 |
|
|
-- state is chosen to be tpoamax = 5 x tREFI = 5 x 3.9us.
|
7772 |
|
|
-- When entering this s_poa_cal state it must be guaranteed
|
7773 |
|
|
-- that the number of stacked refreshes is at maximum.
|
7774 |
|
|
--
|
7775 |
|
|
-- Minimum clock freq supported by DRAM is fck,min=125MHz.
|
7776 |
|
|
-- Each adjustment to postamble latency requires 16*clock
|
7777 |
|
|
-- cycles (time to read "M" training pattern twice) so
|
7778 |
|
|
-- maximum number of adjustments to POA latency (n) is:
|
7779 |
|
|
--
|
7780 |
|
|
-- n = (5 x trefi x fck,min) / 16
|
7781 |
|
|
-- = (5 x 3.9us x 125MHz) / 16
|
7782 |
|
|
-- ~ 152
|
7783 |
|
|
--
|
7784 |
|
|
-- Postamble latency must be adjusted less than 152 cycles
|
7785 |
|
|
-- to meet this requirement.
|
7786 |
|
|
--
|
7787 |
|
|
|
7788 |
|
|
sig_ac_req <= s_ac_read_poa_mtp;
|
7789 |
|
|
|
7790 |
|
|
if sig_poa_ack = '1' then
|
7791 |
|
|
sig_dgrb_state <= s_release_admin;
|
7792 |
|
|
end if;
|
7793 |
|
|
|
7794 |
|
|
--sig_dgrb_state <= s_release_admin;
|
7795 |
|
|
|
7796 |
|
|
when s_track =>
|
7797 |
|
|
if sig_trk_ack = '1' then
|
7798 |
|
|
sig_dgrb_state <= s_release_admin;
|
7799 |
|
|
end if;
|
7800 |
|
|
|
7801 |
|
|
|
7802 |
|
|
when others => null;
|
7803 |
|
|
report dgrb_report_prefix & "undefined state" severity error;
|
7804 |
|
|
sig_dgrb_state <= s_idle;
|
7805 |
|
|
end case;
|
7806 |
|
|
|
7807 |
|
|
|
7808 |
|
|
-- default if not calibrating go to idle state via s_release_admin
|
7809 |
|
|
if ctrl_dgrb_r.command = cmd_idle and
|
7810 |
|
|
sig_dgrb_state /= s_idle and
|
7811 |
|
|
sig_dgrb_state /= s_release_admin then
|
7812 |
|
|
|
7813 |
|
|
sig_dgrb_state <= s_release_admin;
|
7814 |
|
|
end if;
|
7815 |
|
|
|
7816 |
|
|
end if;
|
7817 |
|
|
end process;
|
7818 |
|
|
end block;
|
7819 |
|
|
|
7820 |
|
|
-- ------------------------------------------------------------------
|
7821 |
|
|
-- metastability hardening of potentially async phs_shift_busy signal
|
7822 |
|
|
--
|
7823 |
|
|
-- Triple register it for metastability hardening. This process
|
7824 |
|
|
-- creates the shift register. Also add a sig_phs_shft_busy and
|
7825 |
|
|
-- an sig_phs_shft_busy_1t echo because various other processes find
|
7826 |
|
|
-- this useful.
|
7827 |
|
|
-- ------------------------------------------------------------------
|
7828 |
|
|
phs_shft_busy_reg: block
|
7829 |
|
|
signal phs_shft_busy_1r : std_logic;
|
7830 |
|
|
signal phs_shft_busy_2r : std_logic;
|
7831 |
|
|
signal phs_shft_busy_3r : std_logic;
|
7832 |
|
|
begin
|
7833 |
|
|
phs_shift_busy_sync : process (clk, rst_n)
|
7834 |
|
|
begin
|
7835 |
|
|
if rst_n = '0' then
|
7836 |
|
|
sig_phs_shft_busy <= '0';
|
7837 |
|
|
sig_phs_shft_busy_1t <= '0';
|
7838 |
|
|
|
7839 |
|
|
phs_shft_busy_1r <= '0';
|
7840 |
|
|
phs_shft_busy_2r <= '0';
|
7841 |
|
|
phs_shft_busy_3r <= '0';
|
7842 |
|
|
|
7843 |
|
|
sig_phs_shft_start <= '0';
|
7844 |
|
|
sig_phs_shft_end <= '0';
|
7845 |
|
|
|
7846 |
|
|
elsif rising_edge(clk) then
|
7847 |
|
|
sig_phs_shft_busy_1t <= phs_shft_busy_3r;
|
7848 |
|
|
sig_phs_shft_busy <= phs_shft_busy_2r;
|
7849 |
|
|
|
7850 |
|
|
-- register the below to reduce fan out on sig_phs_shft_busy and sig_phs_shft_busy_1t
|
7851 |
|
|
sig_phs_shft_start <= phs_shft_busy_3r or phs_shft_busy_2r;
|
7852 |
|
|
sig_phs_shft_end <= phs_shft_busy_3r and not(phs_shft_busy_2r);
|
7853 |
|
|
|
7854 |
|
|
phs_shft_busy_3r <= phs_shft_busy_2r;
|
7855 |
|
|
phs_shft_busy_2r <= phs_shft_busy_1r;
|
7856 |
|
|
phs_shft_busy_1r <= phs_shft_busy;
|
7857 |
|
|
end if;
|
7858 |
|
|
end process;
|
7859 |
|
|
end block;
|
7860 |
|
|
|
7861 |
|
|
-- ------------------------------------------------------------------
|
7862 |
|
|
-- PLL reconfig MUX
|
7863 |
|
|
--
|
7864 |
|
|
-- switches PLL Reconfig input between tracking and resync blocks
|
7865 |
|
|
-- ------------------------------------------------------------------
|
7866 |
|
|
pll_reconf_mux : process (clk, rst_n)
|
7867 |
|
|
begin
|
7868 |
|
|
if rst_n = '0' then
|
7869 |
|
|
seq_pll_inc_dec_n <= '0';
|
7870 |
|
|
seq_pll_select <= (others => '0');
|
7871 |
|
|
seq_pll_start_reconfig <= '0';
|
7872 |
|
|
elsif rising_edge(clk) then
|
7873 |
|
|
if sig_dgrb_state = s_seek_cdvw or
|
7874 |
|
|
sig_dgrb_state = s_test_phases or
|
7875 |
|
|
sig_dgrb_state = s_reset_cdvw then
|
7876 |
|
|
seq_pll_select <= pll_resync_clk_index;
|
7877 |
|
|
seq_pll_inc_dec_n <= sig_rsc_pll_inc_dec_n;
|
7878 |
|
|
seq_pll_start_reconfig <= sig_rsc_pll_start_reconfig;
|
7879 |
|
|
elsif sig_dgrb_state = s_track then
|
7880 |
|
|
seq_pll_select <= sig_trk_pll_select;
|
7881 |
|
|
seq_pll_inc_dec_n <= sig_trk_pll_inc_dec_n;
|
7882 |
|
|
seq_pll_start_reconfig <= sig_trk_pll_start_reconfig;
|
7883 |
|
|
else
|
7884 |
|
|
seq_pll_select <= pll_measure_clk_index;
|
7885 |
|
|
seq_pll_inc_dec_n <= '0';
|
7886 |
|
|
seq_pll_start_reconfig <= '0';
|
7887 |
|
|
end if;
|
7888 |
|
|
end if;
|
7889 |
|
|
end process;
|
7890 |
|
|
|
7891 |
|
|
|
7892 |
|
|
cdvw_block : block
|
7893 |
|
|
signal sig_cdvw_calc_1t : std_logic;
|
7894 |
|
|
begin
|
7895 |
|
|
-- purpose: manages centre of data valid window calculations
|
7896 |
|
|
-- type : sequential
|
7897 |
|
|
-- inputs : clk, rst_n
|
7898 |
|
|
-- outputs: sig_cdvw_state
|
7899 |
|
|
cdvw_proc: process (clk, rst_n)
|
7900 |
|
|
variable v_cdvw_state : t_window_processing;
|
7901 |
|
|
variable v_start_calc : std_logic;
|
7902 |
|
|
variable v_shift_in : std_logic;
|
7903 |
|
|
variable v_phase : std_logic;
|
7904 |
|
|
begin -- process cdvw_proc
|
7905 |
|
|
if rst_n = '0' then -- asynchronous reset (active low)
|
7906 |
|
|
|
7907 |
|
|
sig_cdvw_state <= defaults;
|
7908 |
|
|
sig_cdvw_calc_1t <= '0';
|
7909 |
|
|
|
7910 |
|
|
elsif rising_edge(clk) then -- rising clock edge
|
7911 |
|
|
v_cdvw_state := sig_cdvw_state;
|
7912 |
|
|
|
7913 |
|
|
case sig_dgrb_state is
|
7914 |
|
|
when s_track =>
|
7915 |
|
|
v_start_calc := sig_trk_cdvw_calc;
|
7916 |
|
|
v_phase := sig_trk_cdvw_phase;
|
7917 |
|
|
v_shift_in := sig_trk_cdvw_shift_in;
|
7918 |
|
|
|
7919 |
|
|
when s_read_mtp | s_seek_cdvw | s_test_phases =>
|
7920 |
|
|
v_start_calc := sig_rsc_cdvw_calc;
|
7921 |
|
|
v_phase := sig_rsc_cdvw_phase;
|
7922 |
|
|
v_shift_in := sig_rsc_cdvw_shift_in;
|
7923 |
|
|
|
7924 |
|
|
when others =>
|
7925 |
|
|
v_start_calc := '0';
|
7926 |
|
|
v_phase := '0';
|
7927 |
|
|
v_shift_in := '0';
|
7928 |
|
|
end case;
|
7929 |
|
|
|
7930 |
|
|
if sig_dgrb_state = s_reset_cdvw or (sig_dgrb_state = s_track and sig_dgrb_last_state /= s_track) then
|
7931 |
|
|
-- reset *C*entre of *D*ata *V*alid *W*indow
|
7932 |
|
|
v_cdvw_state := defaults;
|
7933 |
|
|
elsif sig_cdvw_calc_1t /= '1' and v_start_calc = '1' then
|
7934 |
|
|
initialise_window_for_proc(v_cdvw_state);
|
7935 |
|
|
elsif v_cdvw_state.status = calculating then
|
7936 |
|
|
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
|
7937 |
|
|
find_centre_of_largest_data_valid_window(v_cdvw_state, PLL_STEPS_PER_CYCLE);
|
7938 |
|
|
else -- can be a 720 degrees sweep
|
7939 |
|
|
find_centre_of_largest_data_valid_window(v_cdvw_state, c_max_phase_shifts);
|
7940 |
|
|
end if;
|
7941 |
|
|
elsif v_shift_in = '1' then
|
7942 |
|
|
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
|
7943 |
|
|
shift_in(v_cdvw_state, v_phase, PLL_STEPS_PER_CYCLE);
|
7944 |
|
|
else
|
7945 |
|
|
shift_in(v_cdvw_state, v_phase, c_max_phase_shifts);
|
7946 |
|
|
end if;
|
7947 |
|
|
end if;
|
7948 |
|
|
|
7949 |
|
|
sig_cdvw_calc_1t <= v_start_calc;
|
7950 |
|
|
sig_cdvw_state <= v_cdvw_state;
|
7951 |
|
|
end if;
|
7952 |
|
|
end process cdvw_proc;
|
7953 |
|
|
end block;
|
7954 |
|
|
|
7955 |
|
|
|
7956 |
|
|
-- ------------------------------------------------------------------
|
7957 |
|
|
-- code block for resync calculation.
|
7958 |
|
|
-- ------------------------------------------------------------------
|
7959 |
|
|
rsc_block : block
|
7960 |
|
|
|
7961 |
|
|
signal sig_rsc_state : t_resync_state;
|
7962 |
|
|
signal sig_rsc_last_state : t_resync_state;
|
7963 |
|
|
|
7964 |
|
|
signal sig_num_phase_shifts : natural range c_max_phase_shifts - 1 downto 0;
|
7965 |
|
|
|
7966 |
|
|
signal sig_rewind_direction : std_logic;
|
7967 |
|
|
signal sig_count : natural range 0 to 2**8 - 1;
|
7968 |
|
|
signal sig_test_dq_expired : std_logic;
|
7969 |
|
|
signal sig_chkd_all_dq_pins : std_logic;
|
7970 |
|
|
|
7971 |
|
|
-- prompts to write data to iram
|
7972 |
|
|
signal sig_dgrb_iram : t_iram_push; -- internal copy of dgrb to iram control signals
|
7973 |
|
|
signal sig_rsc_push_rrp_sweep : std_logic; -- push result of a rrp sweep pass (for cmd_rrp_sweep)
|
7974 |
|
|
signal sig_rsc_push_rrp_pass : std_logic; -- result of a rrp sweep result (for cmd_rrp_sweep)
|
7975 |
|
|
signal sig_rsc_push_rrp_seek : std_logic; -- write seek results (for cmd_rrp_seek / cmd_read_mtp states)
|
7976 |
|
|
signal sig_rsc_push_footer : std_logic; -- write a footer
|
7977 |
|
|
signal sig_dq_pin_ctr_r : natural range 0 to MEM_IF_DWIDTH - 1; -- registered version of dq_pin_ctr
|
7978 |
|
|
signal sig_rsc_curr_phase : natural range 0 to c_max_phase_shifts - 1; -- which phase is being processed
|
7979 |
|
|
signal sig_iram_idle : std_logic; -- track if iram currently writing data
|
7980 |
|
|
signal sig_mtp_match_en : std_logic;
|
7981 |
|
|
|
7982 |
|
|
-- current byte lane disabled?
|
7983 |
|
|
signal sig_curr_byte_ln_dis : std_logic;
|
7984 |
|
|
|
7985 |
|
|
begin
|
7986 |
|
|
-- When using DQS capture or not at full-rate only match on "even" clock cycles.
|
7987 |
|
|
sig_mtp_match_en <= active_high(sig_ac_even = '1' or MEM_IF_DQS_CAPTURE = 0 or DWIDTH_RATIO /= 2);
|
7988 |
|
|
|
7989 |
|
|
-- register current byte lane disable mux for speed
|
7990 |
|
|
byte_lane_dis: process (clk, rst_n)
|
7991 |
|
|
begin
|
7992 |
|
|
if rst_n = '0' then
|
7993 |
|
|
sig_curr_byte_ln_dis <= '0';
|
7994 |
|
|
elsif rising_edge(clk) then
|
7995 |
|
|
sig_curr_byte_ln_dis <= cal_byte_lanes(sig_dq_pin_ctr/MEM_IF_DQ_PER_DQS);
|
7996 |
|
|
end if;
|
7997 |
|
|
end process;
|
7998 |
|
|
|
7999 |
|
|
-- check if all dq pins checked in rsc sweep
|
8000 |
|
|
chkd_dq : process (clk, rst_n)
|
8001 |
|
|
begin
|
8002 |
|
|
if rst_n = '0' then
|
8003 |
|
|
sig_chkd_all_dq_pins <= '0';
|
8004 |
|
|
elsif rising_edge(clk) then
|
8005 |
|
|
if sig_dq_pin_ctr = 0 then
|
8006 |
|
|
sig_chkd_all_dq_pins <= '1';
|
8007 |
|
|
else
|
8008 |
|
|
sig_chkd_all_dq_pins <= '0';
|
8009 |
|
|
end if;
|
8010 |
|
|
end if;
|
8011 |
|
|
end process;
|
8012 |
|
|
|
8013 |
|
|
-- main rsc process
|
8014 |
|
|
rsc_proc : process (clk, rst_n)
|
8015 |
|
|
-- these are temporary variables which should not infer FFs and
|
8016 |
|
|
-- are not guaranteed to be initialized by s_rsc_idle.
|
8017 |
|
|
variable v_rdata_correct : std_logic;
|
8018 |
|
|
variable v_phase_works : std_logic;
|
8019 |
|
|
|
8020 |
|
|
begin
|
8021 |
|
|
if rst_n = '0' then
|
8022 |
|
|
-- initialise signals
|
8023 |
|
|
sig_rsc_state <= s_rsc_idle;
|
8024 |
|
|
sig_rsc_last_state <= s_rsc_idle;
|
8025 |
|
|
|
8026 |
|
|
sig_dq_pin_ctr <= 0;
|
8027 |
|
|
sig_num_phase_shifts <= c_max_phase_shifts - 1; -- want c_max_phase_shifts-1 inc / decs of phase
|
8028 |
|
|
|
8029 |
|
|
sig_count <= 0;
|
8030 |
|
|
sig_test_dq_expired <= '0';
|
8031 |
|
|
|
8032 |
|
|
v_phase_works := '0';
|
8033 |
|
|
|
8034 |
|
|
-- interface to other processes to tell them when we are done.
|
8035 |
|
|
sig_rsc_ack <= '0';
|
8036 |
|
|
sig_rsc_err <= '0';
|
8037 |
|
|
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, c_command_result_len));
|
8038 |
|
|
|
8039 |
|
|
-- centre of data valid window functions
|
8040 |
|
|
sig_rsc_cdvw_phase <= '0';
|
8041 |
|
|
sig_rsc_cdvw_shift_in <= '0';
|
8042 |
|
|
sig_rsc_cdvw_calc <= '0';
|
8043 |
|
|
|
8044 |
|
|
-- set up PLL reconfig interface controls
|
8045 |
|
|
sig_rsc_pll_start_reconfig <= '0';
|
8046 |
|
|
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
|
8047 |
|
|
sig_rewind_direction <= c_pll_phs_dec;
|
8048 |
|
|
|
8049 |
|
|
-- True when access to the ac_block is required.
|
8050 |
|
|
sig_rsc_ac_access_req <= '0';
|
8051 |
|
|
|
8052 |
|
|
-- default values on centre and size of data valid window
|
8053 |
|
|
if SIM_TIME_REDUCTIONS = 1 then
|
8054 |
|
|
cal_codvw_phase <= std_logic_vector(to_unsigned(PRESET_CODVW_PHASE, 8));
|
8055 |
|
|
cal_codvw_size <= std_logic_vector(to_unsigned(PRESET_CODVW_SIZE, 8));
|
8056 |
|
|
else
|
8057 |
|
|
cal_codvw_phase <= (others => '0');
|
8058 |
|
|
cal_codvw_size <= (others => '0');
|
8059 |
|
|
end if;
|
8060 |
|
|
|
8061 |
|
|
sig_rsc_push_rrp_sweep <= '0';
|
8062 |
|
|
sig_rsc_push_rrp_seek <= '0';
|
8063 |
|
|
sig_rsc_push_rrp_pass <= '0';
|
8064 |
|
|
sig_rsc_push_footer <= '0';
|
8065 |
|
|
|
8066 |
|
|
codvw_grt_one_dvw <= '0';
|
8067 |
|
|
|
8068 |
|
|
elsif rising_edge(clk) then
|
8069 |
|
|
-- default values assigned to some signals
|
8070 |
|
|
sig_rsc_ack <= '0';
|
8071 |
|
|
|
8072 |
|
|
sig_rsc_cdvw_phase <= '0';
|
8073 |
|
|
sig_rsc_cdvw_shift_in <= '0';
|
8074 |
|
|
sig_rsc_cdvw_calc <= '0';
|
8075 |
|
|
|
8076 |
|
|
sig_rsc_pll_start_reconfig <= '0';
|
8077 |
|
|
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
|
8078 |
|
|
sig_rewind_direction <= c_pll_phs_dec;
|
8079 |
|
|
|
8080 |
|
|
-- by default don't ask the resync block to read anything
|
8081 |
|
|
sig_rsc_ac_access_req <= '0';
|
8082 |
|
|
|
8083 |
|
|
sig_rsc_push_rrp_sweep <= '0';
|
8084 |
|
|
sig_rsc_push_rrp_seek <= '0';
|
8085 |
|
|
sig_rsc_push_rrp_pass <= '0';
|
8086 |
|
|
sig_rsc_push_footer <= '0';
|
8087 |
|
|
|
8088 |
|
|
sig_test_dq_expired <= '0';
|
8089 |
|
|
|
8090 |
|
|
-- resync state machine
|
8091 |
|
|
case sig_rsc_state is
|
8092 |
|
|
when s_rsc_idle =>
|
8093 |
|
|
-- initialize those signals we are ready to use.
|
8094 |
|
|
sig_dq_pin_ctr <= 0;
|
8095 |
|
|
|
8096 |
|
|
sig_count <= 0;
|
8097 |
|
|
|
8098 |
|
|
if sig_rsc_state = sig_rsc_last_state then -- avoid transition when acknowledging a command has finished
|
8099 |
|
|
if sig_rsc_req = s_rsc_test_phase then
|
8100 |
|
|
sig_rsc_state <= s_rsc_test_phase;
|
8101 |
|
|
elsif sig_rsc_req = s_rsc_cdvw_calc then
|
8102 |
|
|
sig_rsc_state <= s_rsc_cdvw_calc;
|
8103 |
|
|
elsif sig_rsc_req = s_rsc_seek_cdvw then
|
8104 |
|
|
sig_rsc_state <= s_rsc_seek_cdvw;
|
8105 |
|
|
elsif sig_rsc_req = s_rsc_reset_cdvw then
|
8106 |
|
|
sig_rsc_state <= s_rsc_reset_cdvw;
|
8107 |
|
|
else
|
8108 |
|
|
sig_rsc_state <= s_rsc_idle;
|
8109 |
|
|
end if;
|
8110 |
|
|
end if;
|
8111 |
|
|
|
8112 |
|
|
|
8113 |
|
|
when s_rsc_next_phase =>
|
8114 |
|
|
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
|
8115 |
|
|
sig_rsc_pll_start_reconfig <= '1';
|
8116 |
|
|
if sig_phs_shft_start = '1' then
|
8117 |
|
|
-- PLL phase shift started - so stop requesting a shift
|
8118 |
|
|
sig_rsc_pll_start_reconfig <= '0';
|
8119 |
|
|
end if;
|
8120 |
|
|
|
8121 |
|
|
if sig_phs_shft_end = '1' then
|
8122 |
|
|
-- PLL phase shift finished - so proceed to flush the datapath
|
8123 |
|
|
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
|
8124 |
|
|
sig_rsc_state <= s_rsc_test_phase;
|
8125 |
|
|
end if;
|
8126 |
|
|
|
8127 |
|
|
when s_rsc_test_phase =>
|
8128 |
|
|
v_phase_works := '1';
|
8129 |
|
|
-- Note: For single pin single CS calibration set sig_dq_pin_ctr to 0 to
|
8130 |
|
|
-- ensure that only 1 pin calibrated
|
8131 |
|
|
|
8132 |
|
|
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
|
8133 |
|
|
|
8134 |
|
|
if single_bit_cal = '1' then
|
8135 |
|
|
sig_dq_pin_ctr <= 0;
|
8136 |
|
|
else
|
8137 |
|
|
sig_dq_pin_ctr <= MEM_IF_DWIDTH-1;
|
8138 |
|
|
end if;
|
8139 |
|
|
|
8140 |
|
|
when s_rsc_wait_for_idle_dimm =>
|
8141 |
|
|
if sig_dimm_driving_dq = '0' then
|
8142 |
|
|
sig_rsc_state <= s_rsc_flush_datapath;
|
8143 |
|
|
end if;
|
8144 |
|
|
|
8145 |
|
|
|
8146 |
|
|
when s_rsc_flush_datapath =>
|
8147 |
|
|
sig_rsc_ac_access_req <= '1';
|
8148 |
|
|
if sig_rsc_state /= sig_rsc_last_state then
|
8149 |
|
|
-- reset variables we are interested in when we first arrive in this state.
|
8150 |
|
|
sig_count <= c_max_read_lat - 1;
|
8151 |
|
|
else
|
8152 |
|
|
if sig_dimm_driving_dq = '1' then
|
8153 |
|
|
if sig_count = 0 then
|
8154 |
|
|
sig_rsc_state <= s_rsc_test_dq;
|
8155 |
|
|
else
|
8156 |
|
|
sig_count <= sig_count - 1;
|
8157 |
|
|
end if;
|
8158 |
|
|
end if;
|
8159 |
|
|
end if;
|
8160 |
|
|
|
8161 |
|
|
|
8162 |
|
|
when s_rsc_test_dq =>
|
8163 |
|
|
sig_rsc_ac_access_req <= '1';
|
8164 |
|
|
|
8165 |
|
|
if sig_rsc_state /= sig_rsc_last_state then
|
8166 |
|
|
-- reset variables we are interested in when we first arrive in this state.
|
8167 |
|
|
sig_count <= 2*c_cal_mtp_t;
|
8168 |
|
|
|
8169 |
|
|
else
|
8170 |
|
|
|
8171 |
|
|
if sig_dimm_driving_dq = '1' then
|
8172 |
|
|
|
8173 |
|
|
if (
|
8174 |
|
|
(sig_mtp_match = '1' and sig_mtp_match_en = '1') or -- have a pattern match
|
8175 |
|
|
(sig_test_dq_expired = '1') or -- time in this phase has expired.
|
8176 |
|
|
sig_curr_byte_ln_dis = '0' -- byte lane disabled
|
8177 |
|
|
) then
|
8178 |
|
|
|
8179 |
|
|
v_phase_works := v_phase_works and ((sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis));
|
8180 |
|
|
|
8181 |
|
|
sig_rsc_push_rrp_sweep <= '1';
|
8182 |
|
|
sig_rsc_push_rrp_pass <= (sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis);
|
8183 |
|
|
|
8184 |
|
|
if sig_chkd_all_dq_pins = '1' then
|
8185 |
|
|
-- finished checking all dq pins.
|
8186 |
|
|
-- done checking this phase.
|
8187 |
|
|
|
8188 |
|
|
-- shift phase status into
|
8189 |
|
|
sig_rsc_cdvw_phase <= v_phase_works;
|
8190 |
|
|
sig_rsc_cdvw_shift_in <= '1';
|
8191 |
|
|
|
8192 |
|
|
if sig_num_phase_shifts /= 0 then
|
8193 |
|
|
-- there are more phases to test so shift to next phase
|
8194 |
|
|
sig_rsc_state <= s_rsc_next_phase;
|
8195 |
|
|
else
|
8196 |
|
|
-- no more phases to check.
|
8197 |
|
|
-- clean up after ourselves by
|
8198 |
|
|
-- going into s_rsc_rewind_phase
|
8199 |
|
|
sig_rsc_state <= s_rsc_rewind_phase;
|
8200 |
|
|
sig_rewind_direction <= c_pll_phs_dec;
|
8201 |
|
|
sig_num_phase_shifts <= c_max_phase_shifts - 1;
|
8202 |
|
|
end if;
|
8203 |
|
|
else
|
8204 |
|
|
-- shift to next dq pin
|
8205 |
|
|
if MEM_IF_DWIDTH > 71 and -- if >= 72 pins then:
|
8206 |
|
|
(sig_dq_pin_ctr mod 64) = 0 then -- ensure refreshes at least once every 64 pins
|
8207 |
|
|
|
8208 |
|
|
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
|
8209 |
|
|
|
8210 |
|
|
else -- otherwise continue sweep
|
8211 |
|
|
|
8212 |
|
|
sig_rsc_state <= s_rsc_flush_datapath;
|
8213 |
|
|
end if;
|
8214 |
|
|
|
8215 |
|
|
sig_dq_pin_ctr <= sig_dq_pin_ctr - 1;
|
8216 |
|
|
|
8217 |
|
|
end if;
|
8218 |
|
|
|
8219 |
|
|
else
|
8220 |
|
|
|
8221 |
|
|
sig_count <= sig_count - 1;
|
8222 |
|
|
|
8223 |
|
|
if sig_count = 1 then
|
8224 |
|
|
sig_test_dq_expired <= '1';
|
8225 |
|
|
end if;
|
8226 |
|
|
|
8227 |
|
|
end if;
|
8228 |
|
|
end if;
|
8229 |
|
|
end if;
|
8230 |
|
|
|
8231 |
|
|
when s_rsc_reset_cdvw =>
|
8232 |
|
|
sig_rsc_state <= s_rsc_rewind_phase;
|
8233 |
|
|
|
8234 |
|
|
-- determine the amount to rewind by (may be wind forward depending on tracking behaviour)
|
8235 |
|
|
if to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift < 0 then
|
8236 |
|
|
sig_num_phase_shifts <= - (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
|
8237 |
|
|
sig_rewind_direction <= c_pll_phs_inc;
|
8238 |
|
|
else
|
8239 |
|
|
sig_num_phase_shifts <= (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
|
8240 |
|
|
sig_rewind_direction <= c_pll_phs_dec;
|
8241 |
|
|
end if;
|
8242 |
|
|
|
8243 |
|
|
-- reset the calibrated phase and size to zero (because un-doing prior calibration here)
|
8244 |
|
|
cal_codvw_phase <= (others => '0');
|
8245 |
|
|
cal_codvw_size <= (others => '0');
|
8246 |
|
|
|
8247 |
|
|
when s_rsc_rewind_phase =>
|
8248 |
|
|
-- rewinds the resync PLL by sig_num_phase_shifts steps and returns to idle state
|
8249 |
|
|
if sig_num_phase_shifts = 0 then
|
8250 |
|
|
-- no more steps to take off, go to next state
|
8251 |
|
|
sig_num_phase_shifts <= c_max_phase_shifts - 1;
|
8252 |
|
|
|
8253 |
|
|
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
|
8254 |
|
|
sig_rsc_state <= s_rsc_wait_iram;
|
8255 |
|
|
else
|
8256 |
|
|
sig_rsc_ack <= '1';
|
8257 |
|
|
sig_rsc_state <= s_rsc_idle;
|
8258 |
|
|
end if;
|
8259 |
|
|
|
8260 |
|
|
else
|
8261 |
|
|
sig_rsc_pll_inc_dec_n <= sig_rewind_direction;
|
8262 |
|
|
|
8263 |
|
|
-- request a phase shift
|
8264 |
|
|
sig_rsc_pll_start_reconfig <= '1';
|
8265 |
|
|
if sig_phs_shft_busy = '1' then
|
8266 |
|
|
-- inhibit a phase shift if phase shift is busy.
|
8267 |
|
|
sig_rsc_pll_start_reconfig <= '0';
|
8268 |
|
|
end if;
|
8269 |
|
|
|
8270 |
|
|
if sig_phs_shft_busy_1t = '1' and sig_phs_shft_busy /= '1' then
|
8271 |
|
|
-- we've just successfully removed a phase step
|
8272 |
|
|
-- decrement counter
|
8273 |
|
|
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
|
8274 |
|
|
sig_rsc_pll_start_reconfig <= '0';
|
8275 |
|
|
end if;
|
8276 |
|
|
end if;
|
8277 |
|
|
|
8278 |
|
|
|
8279 |
|
|
when s_rsc_cdvw_calc =>
|
8280 |
|
|
if sig_rsc_state /= sig_rsc_last_state then
|
8281 |
|
|
if sig_dgrb_state = s_read_mtp then
|
8282 |
|
|
report dgrb_report_prefix & "gathered resync phase samples (for mtp alignment " & natural'image(current_mtp_almt) & ") is DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
|
8283 |
|
|
else
|
8284 |
|
|
report dgrb_report_prefix & "gathered resync phase samples DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
|
8285 |
|
|
end if;
|
8286 |
|
|
sig_rsc_cdvw_calc <= '1'; -- begin calculating result
|
8287 |
|
|
else
|
8288 |
|
|
sig_rsc_state <= s_rsc_cdvw_wait;
|
8289 |
|
|
end if;
|
8290 |
|
|
|
8291 |
|
|
|
8292 |
|
|
when s_rsc_cdvw_wait =>
|
8293 |
|
|
if sig_cdvw_state.status /= calculating then
|
8294 |
|
|
-- a result has been reached.
|
8295 |
|
|
if sig_dgrb_state = s_read_mtp then -- if doing mtp alignment then skip setting phase
|
8296 |
|
|
|
8297 |
|
|
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
|
8298 |
|
|
sig_rsc_state <= s_rsc_wait_iram;
|
8299 |
|
|
else
|
8300 |
|
|
sig_rsc_ack <= '1';
|
8301 |
|
|
sig_rsc_state <= s_rsc_idle;
|
8302 |
|
|
end if;
|
8303 |
|
|
|
8304 |
|
|
else
|
8305 |
|
|
if sig_cdvw_state.status = valid_result then
|
8306 |
|
|
-- calculation successfully found a
|
8307 |
|
|
-- data-valid window to seek to.
|
8308 |
|
|
sig_rsc_state <= s_rsc_seek_cdvw;
|
8309 |
|
|
|
8310 |
|
|
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, sig_rsc_result'length));
|
8311 |
|
|
|
8312 |
|
|
-- If more than one data valid window was seen, then set the result code :
|
8313 |
|
|
if (sig_cdvw_state.windows_seen > 1) then
|
8314 |
|
|
report dgrb_report_prefix & "Warning : multiple data-valid windows found, largest chosen." severity note;
|
8315 |
|
|
codvw_grt_one_dvw <= '1';
|
8316 |
|
|
else
|
8317 |
|
|
report dgrb_report_prefix & "data-valid window found successfully." severity note;
|
8318 |
|
|
end if;
|
8319 |
|
|
|
8320 |
|
|
else
|
8321 |
|
|
-- calculation failed to find a data-valid window.
|
8322 |
|
|
report dgrb_report_prefix & "couldn't find a data-valid window in resync." severity warning;
|
8323 |
|
|
sig_rsc_ack <= '1';
|
8324 |
|
|
sig_rsc_err <= '1';
|
8325 |
|
|
sig_rsc_state <= s_rsc_idle;
|
8326 |
|
|
|
8327 |
|
|
-- set resync result code
|
8328 |
|
|
case sig_cdvw_state.status is
|
8329 |
|
|
when no_invalid_phases =>
|
8330 |
|
|
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
|
8331 |
|
|
when multiple_equal_windows =>
|
8332 |
|
|
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_rsc_result'length));
|
8333 |
|
|
when no_valid_phases =>
|
8334 |
|
|
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
|
8335 |
|
|
when others =>
|
8336 |
|
|
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_rsc_result'length));
|
8337 |
|
|
end case;
|
8338 |
|
|
end if;
|
8339 |
|
|
end if;
|
8340 |
|
|
|
8341 |
|
|
-- signal to write a rrp_sweep result to iram
|
8342 |
|
|
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
|
8343 |
|
|
sig_rsc_push_rrp_seek <= '1';
|
8344 |
|
|
end if;
|
8345 |
|
|
|
8346 |
|
|
end if;
|
8347 |
|
|
|
8348 |
|
|
|
8349 |
|
|
when s_rsc_seek_cdvw =>
|
8350 |
|
|
if sig_rsc_state /= sig_rsc_last_state then
|
8351 |
|
|
-- reset variables we are interested in when we first arrive in this state
|
8352 |
|
|
sig_count <= sig_cdvw_state.largest_window_centre;
|
8353 |
|
|
else
|
8354 |
|
|
if sig_count = 0 then
|
8355 |
|
|
-- ready to transition to next state
|
8356 |
|
|
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
|
8357 |
|
|
sig_rsc_state <= s_rsc_wait_iram;
|
8358 |
|
|
else
|
8359 |
|
|
sig_rsc_ack <= '1';
|
8360 |
|
|
sig_rsc_state <= s_rsc_idle;
|
8361 |
|
|
end if;
|
8362 |
|
|
|
8363 |
|
|
-- return largest window centre and size in the result
|
8364 |
|
|
|
8365 |
|
|
-- perform cal_codvw phase / size update only if a valid result is found
|
8366 |
|
|
if sig_cdvw_state.status = valid_result then
|
8367 |
|
|
|
8368 |
|
|
cal_codvw_phase <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8));
|
8369 |
|
|
cal_codvw_size <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
|
8370 |
|
|
|
8371 |
|
|
end if;
|
8372 |
|
|
|
8373 |
|
|
-- leaving sig_rsc_err or sig_rsc_result at
|
8374 |
|
|
-- their default values (of success)
|
8375 |
|
|
else
|
8376 |
|
|
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
|
8377 |
|
|
|
8378 |
|
|
-- request a phase shift
|
8379 |
|
|
sig_rsc_pll_start_reconfig <= '1';
|
8380 |
|
|
if sig_phs_shft_start = '1' then
|
8381 |
|
|
-- inhibit a phase shift if phase shift is busy
|
8382 |
|
|
sig_rsc_pll_start_reconfig <= '0';
|
8383 |
|
|
end if;
|
8384 |
|
|
|
8385 |
|
|
if sig_phs_shft_end = '1' then
|
8386 |
|
|
-- we've just successfully removed a phase step
|
8387 |
|
|
-- decrement counter
|
8388 |
|
|
sig_count <= sig_count - 1;
|
8389 |
|
|
end if;
|
8390 |
|
|
end if;
|
8391 |
|
|
end if;
|
8392 |
|
|
|
8393 |
|
|
when s_rsc_wait_iram =>
|
8394 |
|
|
|
8395 |
|
|
-- hold off check 1 clock cycle to enable last rsc push operations to start
|
8396 |
|
|
if sig_rsc_state = sig_rsc_last_state then
|
8397 |
|
|
|
8398 |
|
|
if sig_iram_idle = '1' then
|
8399 |
|
|
|
8400 |
|
|
sig_rsc_ack <= '1';
|
8401 |
|
|
sig_rsc_state <= s_rsc_idle;
|
8402 |
|
|
if sig_dgrb_state = s_test_phases or
|
8403 |
|
|
sig_dgrb_state = s_seek_cdvw or
|
8404 |
|
|
sig_dgrb_state = s_read_mtp then
|
8405 |
|
|
|
8406 |
|
|
sig_rsc_push_footer <= '1';
|
8407 |
|
|
|
8408 |
|
|
end if;
|
8409 |
|
|
|
8410 |
|
|
end if;
|
8411 |
|
|
|
8412 |
|
|
end if;
|
8413 |
|
|
|
8414 |
|
|
when others =>
|
8415 |
|
|
null;
|
8416 |
|
|
end case;
|
8417 |
|
|
|
8418 |
|
|
sig_rsc_last_state <= sig_rsc_state;
|
8419 |
|
|
end if;
|
8420 |
|
|
|
8421 |
|
|
end process;
|
8422 |
|
|
|
8423 |
|
|
|
8424 |
|
|
-- write results to the iram
|
8425 |
|
|
|
8426 |
|
|
iram_push: process (clk, rst_n)
|
8427 |
|
|
|
8428 |
|
|
variable v_iram_wds_req : integer; -- words required for a given iram dump (used to locate where to write footer)
|
8429 |
|
|
|
8430 |
|
|
begin
|
8431 |
|
|
|
8432 |
|
|
if rst_n = '0' then
|
8433 |
|
|
|
8434 |
|
|
sig_dgrb_iram <= defaults;
|
8435 |
|
|
sig_iram_idle <= '0';
|
8436 |
|
|
sig_dq_pin_ctr_r <= 0;
|
8437 |
|
|
sig_rsc_curr_phase <= 0;
|
8438 |
|
|
|
8439 |
|
|
v_iram_wds_req := 0;
|
8440 |
|
|
|
8441 |
|
|
|
8442 |
|
|
elsif rising_edge(clk) then
|
8443 |
|
|
|
8444 |
|
|
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
|
8445 |
|
|
|
8446 |
|
|
if sig_dgrb_iram.iram_write = '1' and sig_dgrb_iram.iram_done = '1' then
|
8447 |
|
|
report dgrb_report_prefix & "iram_done and iram_write signals concurrently set - iram contents may be corrupted" severity failure;
|
8448 |
|
|
end if;
|
8449 |
|
|
|
8450 |
|
|
if sig_dgrb_iram.iram_write = '0' and sig_dgrb_iram.iram_done = '0' then
|
8451 |
|
|
sig_iram_idle <= '1';
|
8452 |
|
|
else
|
8453 |
|
|
sig_iram_idle <= '0';
|
8454 |
|
|
end if;
|
8455 |
|
|
|
8456 |
|
|
-- registered sig_dq_pin_ctr to align with rrp_sweep result
|
8457 |
|
|
sig_dq_pin_ctr_r <= sig_dq_pin_ctr;
|
8458 |
|
|
|
8459 |
|
|
-- calculate current phase (registered to align with rrp_sweep result)
|
8460 |
|
|
sig_rsc_curr_phase <= (c_max_phase_shifts - 1) - sig_num_phase_shifts;
|
8461 |
|
|
|
8462 |
|
|
-- serial push of rrp_sweep results into memory
|
8463 |
|
|
if sig_rsc_push_rrp_sweep = '1' then
|
8464 |
|
|
|
8465 |
|
|
-- signal an iram write and track a write pending
|
8466 |
|
|
sig_dgrb_iram.iram_write <= '1';
|
8467 |
|
|
sig_iram_idle <= '0';
|
8468 |
|
|
|
8469 |
|
|
-- if not single_bit_cal then pack pin phase results in MEM_IF_DWIDTH word blocks
|
8470 |
|
|
if single_bit_cal = '1' then
|
8471 |
|
|
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32);
|
8472 |
|
|
v_iram_wds_req := iram_wd_for_one_pin_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
|
8473 |
|
|
else
|
8474 |
|
|
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32) * MEM_IF_DWIDTH;
|
8475 |
|
|
v_iram_wds_req := iram_wd_for_full_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
|
8476 |
|
|
end if;
|
8477 |
|
|
|
8478 |
|
|
-- check if current pin and phase passed:
|
8479 |
|
|
sig_dgrb_iram.iram_pushdata(0) <= sig_rsc_push_rrp_pass;
|
8480 |
|
|
|
8481 |
|
|
-- bit offset is modulo phase
|
8482 |
|
|
sig_dgrb_iram.iram_bitnum <= sig_rsc_curr_phase mod 32;
|
8483 |
|
|
|
8484 |
|
|
end if;
|
8485 |
|
|
|
8486 |
|
|
-- write result of rrp_calc to iram when completed
|
8487 |
|
|
if sig_rsc_push_rrp_seek = '1' then -- a result found
|
8488 |
|
|
|
8489 |
|
|
sig_dgrb_iram.iram_write <= '1';
|
8490 |
|
|
sig_iram_idle <= '0';
|
8491 |
|
|
|
8492 |
|
|
sig_dgrb_iram.iram_wordnum <= 0;
|
8493 |
|
|
v_iram_wds_req := 1; -- note total word requirement
|
8494 |
|
|
|
8495 |
|
|
if sig_cdvw_state.status = valid_result then -- result is valid
|
8496 |
|
|
|
8497 |
|
|
sig_dgrb_iram.iram_pushdata <= x"0000" &
|
8498 |
|
|
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8)) &
|
8499 |
|
|
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
|
8500 |
|
|
|
8501 |
|
|
else -- invalid result
|
8502 |
|
|
|
8503 |
|
|
|
8504 |
|
|
sig_dgrb_iram.iram_pushdata <= x"FFFF" & -- signals an error condition
|
8505 |
|
|
x"0000";
|
8506 |
|
|
|
8507 |
|
|
end if;
|
8508 |
|
|
|
8509 |
|
|
end if;
|
8510 |
|
|
|
8511 |
|
|
-- when stage finished write footer
|
8512 |
|
|
if sig_rsc_push_footer = '1' then
|
8513 |
|
|
|
8514 |
|
|
sig_dgrb_iram.iram_done <= '1';
|
8515 |
|
|
sig_iram_idle <= '0';
|
8516 |
|
|
|
8517 |
|
|
-- set address location of footer
|
8518 |
|
|
sig_dgrb_iram.iram_wordnum <= v_iram_wds_req;
|
8519 |
|
|
|
8520 |
|
|
end if;
|
8521 |
|
|
|
8522 |
|
|
-- if write completed deassert iram_write and done signals
|
8523 |
|
|
if iram_push_done = '1' then
|
8524 |
|
|
|
8525 |
|
|
sig_dgrb_iram.iram_write <= '0';
|
8526 |
|
|
sig_dgrb_iram.iram_done <= '0';
|
8527 |
|
|
|
8528 |
|
|
end if;
|
8529 |
|
|
|
8530 |
|
|
else
|
8531 |
|
|
|
8532 |
|
|
sig_iram_idle <= '0';
|
8533 |
|
|
sig_dq_pin_ctr_r <= 0;
|
8534 |
|
|
sig_rsc_curr_phase <= 0;
|
8535 |
|
|
|
8536 |
|
|
sig_dgrb_iram <= defaults;
|
8537 |
|
|
|
8538 |
|
|
end if;
|
8539 |
|
|
|
8540 |
|
|
end if;
|
8541 |
|
|
|
8542 |
|
|
end process;
|
8543 |
|
|
|
8544 |
|
|
-- concurrently assign sig_dgrb_iram to dgrb_iram
|
8545 |
|
|
dgrb_iram <= sig_dgrb_iram;
|
8546 |
|
|
|
8547 |
|
|
end block; -- resync calculation
|
8548 |
|
|
|
8549 |
|
|
|
8550 |
|
|
tp_match_block : block
|
8551 |
|
|
--
|
8552 |
|
|
-- Ascii Waveforms:
|
8553 |
|
|
--
|
8554 |
|
|
-- ; ; ; ; ; ;
|
8555 |
|
|
-- ____ ____ ____ ____ ____ ____
|
8556 |
|
|
-- delayed_dqs |____| |____| |____| |____| |____| |____| |____|
|
8557 |
|
|
-- ; ; ; ; ; ;
|
8558 |
|
|
-- ; ; ; ; ; ;
|
8559 |
|
|
-- ; _______ ; _______ ; _______ ; _______ ; _______ _______
|
8560 |
|
|
-- XXXXX / \ / \ / \ / \ / \ / \
|
8561 |
|
|
-- c0,c1 XXXXXX A B X C D X E F X G H X I J X L M X captured data
|
8562 |
|
|
-- XXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \_______/
|
8563 |
|
|
-- ; ; ; ; ; ;
|
8564 |
|
|
-- ; ; ; ; ; ;
|
8565 |
|
|
-- ____; ____; ____ ____ ____ ____ ____
|
8566 |
|
|
-- 180-resync_clk |____| |____| |____| |____| |____| |____| | 180deg shift from delayed dqs
|
8567 |
|
|
-- ; ; ; ; ; ;
|
8568 |
|
|
-- ; ; ; ; ; ;
|
8569 |
|
|
-- ; _______ _______ _______ _______ _______ ____
|
8570 |
|
|
-- XXXXXXXXXX / \ / \ / \ / \ / \ /
|
8571 |
|
|
-- 180-r0,r1 XXXXXXXXXXX A B X C D X E F X G H X I J X L resync data
|
8572 |
|
|
-- XXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \____
|
8573 |
|
|
-- ; ; ; ; ; ;
|
8574 |
|
|
-- ; ; ; ; ; ;
|
8575 |
|
|
-- ____ ____ ____ ____ ____ ____
|
8576 |
|
|
-- 360-resync_clk ____| |____| |____| |____| |____| |____| |____|
|
8577 |
|
|
-- ; ; ; ; ; ;
|
8578 |
|
|
-- ; ; ; ; ; ;
|
8579 |
|
|
-- ; ; _______ ; _______ ; _______ ; _______ ; _______
|
8580 |
|
|
-- XXXXXXXXXXXXXXX / \ / \ / \ / \ / \
|
8581 |
|
|
-- 360-r0,r1 XXXXXXXXXXXXXXXX A B X C D X E F X G H X I J X resync data
|
8582 |
|
|
-- XXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/
|
8583 |
|
|
-- ; ; ; ; ; ;
|
8584 |
|
|
-- ; ; ; ; ; ;
|
8585 |
|
|
-- ____ ____ ____ ____ ____ ____ ____
|
8586 |
|
|
-- 540-resync_clk |____| |____| |____| |____| |____| |____| |
|
8587 |
|
|
-- ; ; ; ; ; ;
|
8588 |
|
|
-- ; ; ; ; ; ;
|
8589 |
|
|
-- ; ; _______ _______ _______ _______ ____
|
8590 |
|
|
-- XXXXXXXXXXXXXXXXXXX / \ / \ / \ / \ /
|
8591 |
|
|
-- 540-r0,r1 XXXXXXXXXXXXXXXXXXXX A B X C D X E F X G H X I resync data
|
8592 |
|
|
-- XXXXXXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \____
|
8593 |
|
|
-- ; ; ; ; ; ;
|
8594 |
|
|
-- ; ; ; ; ; ;
|
8595 |
|
|
-- ;____ ____ ____ ____ ____ ____
|
8596 |
|
|
-- phy_clk |____| |____| |____| |____| |____| |____| |____|
|
8597 |
|
|
--
|
8598 |
|
|
-- 0 1 2 3 4 5 6
|
8599 |
|
|
--
|
8600 |
|
|
--
|
8601 |
|
|
-- |<- Aligned Data ->|
|
8602 |
|
|
-- phy_clk 180-r0,r1 540-r0,r1 sig_mtp_match_en (generated from sig_ac_even)
|
8603 |
|
|
-- 0 XXXXXXXX XXXXXXXX '1'
|
8604 |
|
|
-- 1 XXXXXXAB XXXXXXXX '0'
|
8605 |
|
|
-- 2 XXXXABCD XXXXXXAB '1'
|
8606 |
|
|
-- 3 XXABCDEF XXXXABCD '0'
|
8607 |
|
|
-- 4 ABCDEFGH XXABCDEF '1'
|
8608 |
|
|
-- 5 CDEFGHAB ABCDEFGH '0'
|
8609 |
|
|
--
|
8610 |
|
|
-- In DQS-based capture, sweeping resync_clk from 180 degrees to 360
|
8611 |
|
|
-- does not necessarily result in a failure because the setup/hold
|
8612 |
|
|
-- requirements are so small. The data comparison needs to fail when
|
8613 |
|
|
-- the resync_clk is shifted more than 360 degrees. The
|
8614 |
|
|
-- sig_mtp_match_en signal allows the sequencer to blind itself
|
8615 |
|
|
-- training pattern matches that occur above 360 degrees.
|
8616 |
|
|
--
|
8617 |
|
|
--
|
8618 |
|
|
--
|
8619 |
|
|
--
|
8620 |
|
|
--
|
8621 |
|
|
-- Asserts sig_mtp_match.
|
8622 |
|
|
--
|
8623 |
|
|
-- Data comes in from rdata and is pushed into a two-bit wide shift register.
|
8624 |
|
|
-- It is a critical assumption that the rdata comes back byte aligned.
|
8625 |
|
|
--
|
8626 |
|
|
--
|
8627 |
|
|
--sig_mtp_match_valid
|
8628 |
|
|
-- rdata_valid (shift-enable)
|
8629 |
|
|
-- |
|
8630 |
|
|
-- |
|
8631 |
|
|
-- +-----------------------+-----------+------------------+
|
8632 |
|
|
-- ___ | | |
|
8633 |
|
|
-- dq(0) >---| \ | Shift Register |
|
8634 |
|
|
-- dq(1) >---| \ +------+ +------+ +------------------+
|
8635 |
|
|
-- dq(2) >---| )--->| D(0) |-+->| D(1) |-+->...-+->| D(c_cal_mtp_len - 1) |
|
8636 |
|
|
-- ... | / +------+ | +------+ | | +------------------+
|
8637 |
|
|
-- dq(n-1) >---|___/ +-----------++-...-+
|
8638 |
|
|
-- | || +---+
|
8639 |
|
|
-- | (==)--------> sig_mtp_match_0t ---->| |-->sig_mtp_match_1t-->sig_mtp_match
|
8640 |
|
|
-- | || +---+
|
8641 |
|
|
-- | +-----------++...-+
|
8642 |
|
|
-- sig_dq_pin_ctr >-+ +------+ | +------+ | | +------------------+
|
8643 |
|
|
-- | P(0) |-+ | P(1) |-+ ...-+->| P(c_cal_mtp_len - 1) |
|
8644 |
|
|
-- +------+ +------+ +------------------+
|
8645 |
|
|
--
|
8646 |
|
|
--
|
8647 |
|
|
--
|
8648 |
|
|
--
|
8649 |
|
|
signal sig_rdata_current_pin : std_logic_vector(c_cal_mtp_len - 1 downto 0);
|
8650 |
|
|
|
8651 |
|
|
-- A fundamental assumption here is that rdata_valid is all
|
8652 |
|
|
-- ones or all zeros - not both.
|
8653 |
|
|
signal sig_rdata_valid_1t : std_logic; -- rdata_valid delayed by 1 clock period.
|
8654 |
|
|
signal sig_rdata_valid_2t : std_logic; -- rdata_valid delayed by 2 clock periods.
|
8655 |
|
|
|
8656 |
|
|
begin
|
8657 |
|
|
rdata_valid_1t_proc : process (clk, rst_n)
|
8658 |
|
|
begin
|
8659 |
|
|
if rst_n /= '1' then
|
8660 |
|
|
sig_rdata_valid_1t <= '0';
|
8661 |
|
|
sig_rdata_valid_2t <= '0';
|
8662 |
|
|
elsif rising_edge(clk) then
|
8663 |
|
|
sig_rdata_valid_2t <= sig_rdata_valid_1t;
|
8664 |
|
|
sig_rdata_valid_1t <= rdata_valid(0);
|
8665 |
|
|
end if;
|
8666 |
|
|
end process;
|
8667 |
|
|
|
8668 |
|
|
|
8669 |
|
|
-- MUX data into sig_rdata_current_pin shift register.
|
8670 |
|
|
rdata_current_pin_proc: process (clk, rst_n)
|
8671 |
|
|
begin
|
8672 |
|
|
if rst_n /= '1' then
|
8673 |
|
|
sig_rdata_current_pin <= (others => '0');
|
8674 |
|
|
elsif rising_edge(clk) then
|
8675 |
|
|
-- shift old data down the shift register
|
8676 |
|
|
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO downto 0) <=
|
8677 |
|
|
sig_rdata_current_pin(sig_rdata_current_pin'high downto DWIDTH_RATIO);
|
8678 |
|
|
|
8679 |
|
|
-- shift new data into the bottom of the shift register.
|
8680 |
|
|
for i in 0 to DWIDTH_RATIO - 1 loop
|
8681 |
|
|
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO + 1 + i) <= rdata(i*MEM_IF_DWIDTH + sig_dq_pin_ctr);
|
8682 |
|
|
end loop;
|
8683 |
|
|
end if;
|
8684 |
|
|
end process;
|
8685 |
|
|
|
8686 |
|
|
|
8687 |
|
|
|
8688 |
|
|
mtp_match_proc : process (clk, rst_n)
|
8689 |
|
|
begin
|
8690 |
|
|
if rst_n /= '1' then -- * when at least c_max_read_lat clock cycles have passed
|
8691 |
|
|
sig_mtp_match <= '0';
|
8692 |
|
|
elsif rising_edge(clk) then
|
8693 |
|
|
sig_mtp_match <= '0';
|
8694 |
|
|
|
8695 |
|
|
if sig_rdata_current_pin = c_cal_mtp then
|
8696 |
|
|
sig_mtp_match <= '1';
|
8697 |
|
|
end if;
|
8698 |
|
|
end if;
|
8699 |
|
|
end process;
|
8700 |
|
|
|
8701 |
|
|
|
8702 |
|
|
poa_match_proc : process (clk, rst_n)
|
8703 |
|
|
-- poa_match_Calibration Strategy
|
8704 |
|
|
--
|
8705 |
|
|
-- Ascii Waveforms:
|
8706 |
|
|
--
|
8707 |
|
|
-- __ __ __ __ __ __ __ __ __
|
8708 |
|
|
-- clk __| |__| |__| |__| |__| |__| |__| |__| |__| |
|
8709 |
|
|
--
|
8710 |
|
|
-- ; ; ; ;
|
8711 |
|
|
-- _________________
|
8712 |
|
|
-- rdata_valid ________| |___________________________
|
8713 |
|
|
--
|
8714 |
|
|
-- ; ; ; ;
|
8715 |
|
|
-- _____
|
8716 |
|
|
-- poa_match_en ______________________________________| |_______________
|
8717 |
|
|
--
|
8718 |
|
|
-- ; ; ; ;
|
8719 |
|
|
-- _____
|
8720 |
|
|
-- poa_match XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
|
8721 |
|
|
--
|
8722 |
|
|
--
|
8723 |
|
|
-- Notes:
|
8724 |
|
|
-- -poa_match is only valid while poa_match_en is asserted.
|
8725 |
|
|
--
|
8726 |
|
|
--
|
8727 |
|
|
--
|
8728 |
|
|
--
|
8729 |
|
|
--
|
8730 |
|
|
--
|
8731 |
|
|
begin
|
8732 |
|
|
if rst_n /= '1' then
|
8733 |
|
|
|
8734 |
|
|
sig_poa_match_en <= '0';
|
8735 |
|
|
sig_poa_match <= '0';
|
8736 |
|
|
|
8737 |
|
|
elsif rising_edge(clk) then
|
8738 |
|
|
sig_poa_match <= '0';
|
8739 |
|
|
|
8740 |
|
|
sig_poa_match_en <= '0';
|
8741 |
|
|
if sig_rdata_valid_2t = '1' and sig_rdata_valid_1t = '0' then
|
8742 |
|
|
sig_poa_match_en <= '1';
|
8743 |
|
|
end if;
|
8744 |
|
|
|
8745 |
|
|
if DWIDTH_RATIO = 2 then
|
8746 |
|
|
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 6) = "111100" then
|
8747 |
|
|
sig_poa_match <= '1';
|
8748 |
|
|
end if;
|
8749 |
|
|
elsif DWIDTH_RATIO = 4 then
|
8750 |
|
|
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 8) = "11111100" then
|
8751 |
|
|
sig_poa_match <= '1';
|
8752 |
|
|
end if;
|
8753 |
|
|
else
|
8754 |
|
|
report "Unsupported DWIDTH_RATIO" severity failure;
|
8755 |
|
|
end if;
|
8756 |
|
|
|
8757 |
|
|
end if;
|
8758 |
|
|
end process;
|
8759 |
|
|
end block;
|
8760 |
|
|
|
8761 |
|
|
|
8762 |
|
|
poa_block : block
|
8763 |
|
|
-- Postamble Calibration Strategy
|
8764 |
|
|
--
|
8765 |
|
|
-- Ascii Waveforms:
|
8766 |
|
|
--
|
8767 |
|
|
-- c_read_burst_t c_read_burst_t
|
8768 |
|
|
-- ;<------->; ;<------->;
|
8769 |
|
|
-- ; ; ; ;
|
8770 |
|
|
-- __ / / __
|
8771 |
|
|
-- mem_dq[0] ___________| |_____\ \________| |___
|
8772 |
|
|
--
|
8773 |
|
|
-- ; ; ; ;
|
8774 |
|
|
-- ; ; ; ;
|
8775 |
|
|
-- _________ / / _________
|
8776 |
|
|
-- poa_enable ______| |___\ \_| |___
|
8777 |
|
|
-- ; ; ; ;
|
8778 |
|
|
-- ; ; ; ;
|
8779 |
|
|
-- __ / / ______
|
8780 |
|
|
-- rdata[0] ___________| |______\ \_______|
|
8781 |
|
|
-- ; ; ; ;
|
8782 |
|
|
-- ; ; ; ;
|
8783 |
|
|
-- ; ; ; ;
|
8784 |
|
|
-- _ / / _
|
8785 |
|
|
-- poa_match_en _____________| |___\ \___________| |_
|
8786 |
|
|
-- ; ; ; ; ; ;
|
8787 |
|
|
-- ; ; ; ; ; ;
|
8788 |
|
|
-- ; ; ; ; ; ;
|
8789 |
|
|
-- / / _
|
8790 |
|
|
-- poa_match ___________________\ \___________| |_
|
8791 |
|
|
-- ; ; ; ; ; ;
|
8792 |
|
|
-- ; ; ; ; ; ;
|
8793 |
|
|
-- ; ; ; ; ; ;
|
8794 |
|
|
-- _ / /
|
8795 |
|
|
-- seq_poa_lat_dec _______________| |_\ \_______________
|
8796 |
|
|
-- ; ; ; ; ; ;
|
8797 |
|
|
-- ; ; ; ; ; ;
|
8798 |
|
|
-- ; ; ; ; ; ;
|
8799 |
|
|
-- / /
|
8800 |
|
|
-- seq_poa_lat_inc ___________________\ \_______________
|
8801 |
|
|
-- ; ; ; ; ; ;
|
8802 |
|
|
-- ; ; ; ; ; ;
|
8803 |
|
|
--
|
8804 |
|
|
-- (1) (2)
|
8805 |
|
|
--
|
8806 |
|
|
--
|
8807 |
|
|
-- (1) poa_enable signal is late, and the zeros on mem_dq after (1)
|
8808 |
|
|
-- are captured.
|
8809 |
|
|
-- (2) poa_enable signal is aligned. Zeros following (2) are not
|
8810 |
|
|
-- captured rdata remains at '1'.
|
8811 |
|
|
--
|
8812 |
|
|
-- The DQS capture circuit wth the dqs enable asynchronous set.
|
8813 |
|
|
--
|
8814 |
|
|
--
|
8815 |
|
|
--
|
8816 |
|
|
-- dqs_en_async_preset ----------+
|
8817 |
|
|
-- |
|
8818 |
|
|
-- v
|
8819 |
|
|
-- +---------+
|
8820 |
|
|
-- +--|Q SET D|----------- gnd
|
8821 |
|
|
-- | | <O---+
|
8822 |
|
|
-- | +---------+ |
|
8823 |
|
|
-- | |
|
8824 |
|
|
-- | |
|
8825 |
|
|
-- +--+---. |
|
8826 |
|
|
-- |AND )--------+------- dqs_bus
|
8827 |
|
|
-- delayed_dqs -----+---^
|
8828 |
|
|
--
|
8829 |
|
|
--
|
8830 |
|
|
--
|
8831 |
|
|
-- _____ _____ _____ _____
|
8832 |
|
|
-- dqs ____| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
|
8833 |
|
|
-- ; ; ; ; ;
|
8834 |
|
|
-- ; ; ; ;
|
8835 |
|
|
-- _____ _____ _____ _____
|
8836 |
|
|
-- delayed_dqs _______| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
|
8837 |
|
|
--
|
8838 |
|
|
-- ; ; ; ; ;
|
8839 |
|
|
-- ; ______________________________________________________________
|
8840 |
|
|
-- dqs_en_async_ _____________________________| |_____
|
8841 |
|
|
-- preset
|
8842 |
|
|
-- ; ; ; ; ;
|
8843 |
|
|
-- ; ; ; ; ;
|
8844 |
|
|
-- _____ _____ _____
|
8845 |
|
|
-- dqs_bus _______| |_________________| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
|
8846 |
|
|
--
|
8847 |
|
|
-- ; ;
|
8848 |
|
|
-- (1) (2)
|
8849 |
|
|
--
|
8850 |
|
|
--
|
8851 |
|
|
-- Notes:
|
8852 |
|
|
-- (1) The dqs_bus pulse here comes because the last value of Q
|
8853 |
|
|
-- is '1' until the first DQS pulse clocks gnd into the FF,
|
8854 |
|
|
-- brings low the AND gate, and disables dqs_bus. A training
|
8855 |
|
|
-- pattern could potentially match at this point even though
|
8856 |
|
|
-- between (1) and (2) there are no dqs_bus triggers. Data
|
8857 |
|
|
-- is frozen on rdata while awaiting the dqs_bus pulses at
|
8858 |
|
|
-- (2). For this reason, wait until the first match of the
|
8859 |
|
|
-- training pattern, and continue reducing latency until it
|
8860 |
|
|
-- TP no longer matches, then increase latency by one. In
|
8861 |
|
|
-- this case, dqs_en_async_preset will have its latency
|
8862 |
|
|
-- reduced by three until the training pattern is not matched,
|
8863 |
|
|
-- then latency is increased by one.
|
8864 |
|
|
--
|
8865 |
|
|
--
|
8866 |
|
|
--
|
8867 |
|
|
--
|
8868 |
|
|
|
8869 |
|
|
-- Postamble calibration state
|
8870 |
|
|
type t_poa_state is (
|
8871 |
|
|
s_poa_rewind_to_pass,
|
8872 |
|
|
s_poa_done
|
8873 |
|
|
);
|
8874 |
|
|
|
8875 |
|
|
constant c_poa_lat_cmd_wait : natural := 10; -- Number of clock cycles to wait for lat_inc/lat_dec signal to take effect.
|
8876 |
|
|
constant c_poa_max_lat : natural := 100; -- Maximum number of allowable latency changes.
|
8877 |
|
|
signal sig_poa_adjust_count : integer range 0 to 2**8 - 1;
|
8878 |
|
|
|
8879 |
|
|
signal sig_poa_state : t_poa_state;
|
8880 |
|
|
|
8881 |
|
|
|
8882 |
|
|
begin
|
8883 |
|
|
|
8884 |
|
|
poa_proc : process (clk, rst_n)
|
8885 |
|
|
begin
|
8886 |
|
|
if rst_n = '0' then
|
8887 |
|
|
sig_poa_ack <= '0';
|
8888 |
|
|
seq_poa_lat_dec_1x <= (others => '0');
|
8889 |
|
|
seq_poa_lat_inc_1x <= (others => '0');
|
8890 |
|
|
sig_poa_adjust_count <= 0;
|
8891 |
|
|
|
8892 |
|
|
sig_poa_state <= s_poa_rewind_to_pass;
|
8893 |
|
|
|
8894 |
|
|
elsif rising_edge(clk) then
|
8895 |
|
|
sig_poa_ack <= '0';
|
8896 |
|
|
seq_poa_lat_inc_1x <= (others => '0');
|
8897 |
|
|
seq_poa_lat_dec_1x <= (others => '0');
|
8898 |
|
|
|
8899 |
|
|
if sig_dgrb_state = s_poa_cal then
|
8900 |
|
|
case sig_poa_state is
|
8901 |
|
|
when s_poa_rewind_to_pass =>
|
8902 |
|
|
-- In postamble calibration
|
8903 |
|
|
--
|
8904 |
|
|
-- Normally, must wait for sig_dimm_driving_dq to be '1'
|
8905 |
|
|
-- before reading, but by this point in calibration
|
8906 |
|
|
-- rdata_valid is assumed to be set up properly. The
|
8907 |
|
|
-- sig_poa_match_en (derived from rdata_valid) is used
|
8908 |
|
|
-- here rather than sig_dimm_driving_dq.
|
8909 |
|
|
if sig_poa_match_en = '1' then
|
8910 |
|
|
if sig_poa_match = '1' then
|
8911 |
|
|
sig_poa_state <= s_poa_done;
|
8912 |
|
|
else
|
8913 |
|
|
seq_poa_lat_dec_1x <= (others => '1');
|
8914 |
|
|
end if;
|
8915 |
|
|
|
8916 |
|
|
sig_poa_adjust_count <= sig_poa_adjust_count + 1;
|
8917 |
|
|
end if;
|
8918 |
|
|
|
8919 |
|
|
|
8920 |
|
|
when s_poa_done =>
|
8921 |
|
|
sig_poa_ack <= '1';
|
8922 |
|
|
end case;
|
8923 |
|
|
else
|
8924 |
|
|
sig_poa_state <= s_poa_rewind_to_pass;
|
8925 |
|
|
sig_poa_adjust_count <= 0;
|
8926 |
|
|
end if;
|
8927 |
|
|
|
8928 |
|
|
|
8929 |
|
|
assert sig_poa_adjust_count <= c_poa_max_lat
|
8930 |
|
|
report dgrb_report_prefix & "Maximum number of postamble latency adjustments exceeded."
|
8931 |
|
|
severity failure;
|
8932 |
|
|
end if;
|
8933 |
|
|
end process;
|
8934 |
|
|
|
8935 |
|
|
end block;
|
8936 |
|
|
|
8937 |
|
|
-- ------------------------------------------------------------------
|
8938 |
|
|
-- code block for tracking signal generation
|
8939 |
|
|
-- ------------------------------------------------------------------
|
8940 |
|
|
trk_block : block
|
8941 |
|
|
type t_tracking_state is (
|
8942 |
|
|
s_trk_init,
|
8943 |
|
|
s_trk_idle,
|
8944 |
|
|
s_trk_mimic_sample,
|
8945 |
|
|
s_trk_next_phase,
|
8946 |
|
|
s_trk_cdvw_calc,
|
8947 |
|
|
s_trk_cdvw_wait,
|
8948 |
|
|
s_trk_cdvw_drift,
|
8949 |
|
|
s_trk_adjust_resync,
|
8950 |
|
|
s_trk_complete
|
8951 |
|
|
);
|
8952 |
|
|
|
8953 |
|
|
signal sig_mmc_seq_done : std_logic;
|
8954 |
|
|
signal sig_mmc_seq_done_1t : std_logic;
|
8955 |
|
|
|
8956 |
|
|
signal sig_mmc_start : std_logic;
|
8957 |
|
|
|
8958 |
|
|
signal sig_trk_state : t_tracking_state;
|
8959 |
|
|
signal sig_trk_last_state : t_tracking_state;
|
8960 |
|
|
|
8961 |
|
|
signal sig_rsc_drift : integer range -MAX_RSC_DRIFT_IN_PHASES to MAX_RSC_DRIFT_IN_PHASES; -- stores total change in rsc phase from first calibration
|
8962 |
|
|
signal sig_req_rsc_shift : integer range -MAX_RSC_DRIFT_IN_PHASES to MAX_RSC_DRIFT_IN_PHASES; -- stores required shift in rsc phase instantaneously
|
8963 |
|
|
signal sig_mimic_cdv_found : std_logic;
|
8964 |
|
|
signal sig_mimic_cdv : integer range 0 to PLL_STEPS_PER_CYCLE; -- centre of data valid window calculated from first mimic-cycle
|
8965 |
|
|
signal sig_mimic_delta : integer range -PLL_STEPS_PER_CYCLE to PLL_STEPS_PER_CYCLE;
|
8966 |
|
|
signal sig_large_drift_seen : std_logic;
|
8967 |
|
|
|
8968 |
|
|
begin
|
8969 |
|
|
|
8970 |
|
|
-- advertise the codvw phase shift
|
8971 |
|
|
process (sig_req_rsc_shift, sig_mimic_cdv_found)
|
8972 |
|
|
variable v_length : integer;
|
8973 |
|
|
begin
|
8974 |
|
|
|
8975 |
|
|
if sig_mimic_cdv_found = '1' then
|
8976 |
|
|
v_length := codvw_trk_shift'length;
|
8977 |
|
|
-- ensure bounded at range of codvw_phase_tracking_shift signal
|
8978 |
|
|
if sig_req_rsc_shift < -2**(v_length-1) then
|
8979 |
|
|
codvw_trk_shift <= std_logic_vector(to_signed(-2**(v_length-1), v_length));
|
8980 |
|
|
elsif sig_req_rsc_shift > 2**(v_length-1)-1 then
|
8981 |
|
|
codvw_trk_shift <= std_logic_vector(to_signed(2**(v_length-1)-1, v_length));
|
8982 |
|
|
else
|
8983 |
|
|
codvw_trk_shift <= std_logic_vector(to_signed(sig_req_rsc_shift, v_length));
|
8984 |
|
|
end if;
|
8985 |
|
|
else
|
8986 |
|
|
codvw_trk_shift <= (others => '0');
|
8987 |
|
|
end if;
|
8988 |
|
|
end process;
|
8989 |
|
|
|
8990 |
|
|
-- request a mimic sample
|
8991 |
|
|
mimic_sample_req : process (clk, rst_n)
|
8992 |
|
|
variable v_echo : std_logic;
|
8993 |
|
|
begin
|
8994 |
|
|
if rst_n = '0' then
|
8995 |
|
|
seq_mmc_start <= '0';
|
8996 |
|
|
v_echo := '0';
|
8997 |
|
|
elsif rising_edge(clk) then
|
8998 |
|
|
-- extend sig_mmc_start by one clock cycle
|
8999 |
|
|
if sig_mmc_start = '1' then
|
9000 |
|
|
seq_mmc_start <= '1';
|
9001 |
|
|
v_echo := '1';
|
9002 |
|
|
elsif v_echo = '1' then
|
9003 |
|
|
seq_mmc_start <= '1';
|
9004 |
|
|
v_echo := '0';
|
9005 |
|
|
else
|
9006 |
|
|
seq_mmc_start <= '0';
|
9007 |
|
|
end if;
|
9008 |
|
|
end if;
|
9009 |
|
|
end process;
|
9010 |
|
|
|
9011 |
|
|
|
9012 |
|
|
-- metastability hardening of async mmc_seq_done signal
|
9013 |
|
|
mmc_seq_req_sync : process (clk, rst_n)
|
9014 |
|
|
variable v_mmc_seq_done_1r : std_logic;
|
9015 |
|
|
variable v_mmc_seq_done_2r : std_logic;
|
9016 |
|
|
variable v_mmc_seq_done_3r : std_logic;
|
9017 |
|
|
begin
|
9018 |
|
|
if rst_n = '0' then
|
9019 |
|
|
sig_mmc_seq_done <= '0';
|
9020 |
|
|
sig_mmc_seq_done_1t <= '0';
|
9021 |
|
|
|
9022 |
|
|
v_mmc_seq_done_1r := '0';
|
9023 |
|
|
v_mmc_seq_done_2r := '0';
|
9024 |
|
|
v_mmc_seq_done_3r := '0';
|
9025 |
|
|
elsif rising_edge(clk) then
|
9026 |
|
|
sig_mmc_seq_done_1t <= v_mmc_seq_done_3r;
|
9027 |
|
|
sig_mmc_seq_done <= v_mmc_seq_done_2r;
|
9028 |
|
|
|
9029 |
|
|
v_mmc_seq_done_3r := v_mmc_seq_done_2r;
|
9030 |
|
|
v_mmc_seq_done_2r := v_mmc_seq_done_1r;
|
9031 |
|
|
v_mmc_seq_done_1r := mmc_seq_done;
|
9032 |
|
|
end if;
|
9033 |
|
|
end process;
|
9034 |
|
|
|
9035 |
|
|
|
9036 |
|
|
-- collect mimic samples as they arrive
|
9037 |
|
|
shift_in_mmc_seq_value : process (clk, rst_n)
|
9038 |
|
|
begin
|
9039 |
|
|
if rst_n = '0' then
|
9040 |
|
|
sig_trk_cdvw_shift_in <= '0';
|
9041 |
|
|
sig_trk_cdvw_phase <= '0';
|
9042 |
|
|
elsif rising_edge(clk) then
|
9043 |
|
|
sig_trk_cdvw_shift_in <= '0';
|
9044 |
|
|
sig_trk_cdvw_phase <= '0';
|
9045 |
|
|
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
|
9046 |
|
|
sig_trk_cdvw_shift_in <= '1';
|
9047 |
|
|
sig_trk_cdvw_phase <= mmc_seq_value;
|
9048 |
|
|
end if;
|
9049 |
|
|
end if;
|
9050 |
|
|
end process;
|
9051 |
|
|
|
9052 |
|
|
|
9053 |
|
|
-- main tracking state machine
|
9054 |
|
|
trk_proc : process (clk, rst_n)
|
9055 |
|
|
variable v_remaining_samples : natural range 0 to 2**8 - 1;
|
9056 |
|
|
begin
|
9057 |
|
|
if rst_n = '0' then
|
9058 |
|
|
sig_trk_state <= s_trk_init;
|
9059 |
|
|
sig_trk_last_state <= s_trk_init;
|
9060 |
|
|
|
9061 |
|
|
sig_trk_result <= (others => '0');
|
9062 |
|
|
sig_trk_err <= '0';
|
9063 |
|
|
sig_mmc_start <= '0';
|
9064 |
|
|
|
9065 |
|
|
sig_trk_pll_select <= (others => '0');
|
9066 |
|
|
|
9067 |
|
|
sig_req_rsc_shift <= -MAX_RSC_DRIFT_IN_PHASES;
|
9068 |
|
|
sig_rsc_drift <= -MAX_RSC_DRIFT_IN_PHASES;
|
9069 |
|
|
sig_mimic_delta <= -PLL_STEPS_PER_CYCLE;
|
9070 |
|
|
|
9071 |
|
|
sig_mimic_cdv_found <= '0';
|
9072 |
|
|
sig_mimic_cdv <= 0;
|
9073 |
|
|
|
9074 |
|
|
sig_large_drift_seen <= '0';
|
9075 |
|
|
|
9076 |
|
|
sig_trk_cdvw_calc <= '0';
|
9077 |
|
|
|
9078 |
|
|
v_remaining_samples := 0;
|
9079 |
|
|
|
9080 |
|
|
sig_trk_pll_start_reconfig <= '0';
|
9081 |
|
|
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
|
9082 |
|
|
|
9083 |
|
|
sig_trk_ack <= '0';
|
9084 |
|
|
|
9085 |
|
|
elsif rising_edge(clk) then
|
9086 |
|
|
sig_trk_pll_select <= pll_measure_clk_index;
|
9087 |
|
|
sig_trk_pll_start_reconfig <= '0';
|
9088 |
|
|
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
|
9089 |
|
|
sig_large_drift_seen <= '0';
|
9090 |
|
|
|
9091 |
|
|
sig_trk_cdvw_calc <= '0';
|
9092 |
|
|
|
9093 |
|
|
sig_trk_ack <= '0';
|
9094 |
|
|
sig_trk_err <= '0';
|
9095 |
|
|
sig_trk_result <= (others => '0');
|
9096 |
|
|
|
9097 |
|
|
sig_mmc_start <= '0';
|
9098 |
|
|
|
9099 |
|
|
-- if no cdv found then reset tracking results
|
9100 |
|
|
if sig_mimic_cdv_found = '0' then
|
9101 |
|
|
sig_rsc_drift <= 0;
|
9102 |
|
|
sig_req_rsc_shift <= 0;
|
9103 |
|
|
sig_mimic_delta <= 0;
|
9104 |
|
|
end if;
|
9105 |
|
|
|
9106 |
|
|
if sig_dgrb_state = s_track then
|
9107 |
|
|
|
9108 |
|
|
-- resync state machine
|
9109 |
|
|
case sig_trk_state is
|
9110 |
|
|
when s_trk_init =>
|
9111 |
|
|
sig_trk_state <= s_trk_idle;
|
9112 |
|
|
sig_mimic_cdv_found <= '0';
|
9113 |
|
|
sig_rsc_drift <= 0;
|
9114 |
|
|
sig_req_rsc_shift <= 0;
|
9115 |
|
|
sig_mimic_delta <= 0;
|
9116 |
|
|
|
9117 |
|
|
|
9118 |
|
|
when s_trk_idle =>
|
9119 |
|
|
v_remaining_samples := PLL_STEPS_PER_CYCLE; -- ensure a 360 degrees sweep
|
9120 |
|
|
sig_trk_state <= s_trk_mimic_sample;
|
9121 |
|
|
|
9122 |
|
|
|
9123 |
|
|
when s_trk_mimic_sample =>
|
9124 |
|
|
if v_remaining_samples = 0 then
|
9125 |
|
|
sig_trk_state <= s_trk_cdvw_calc;
|
9126 |
|
|
else
|
9127 |
|
|
if sig_trk_state /= sig_trk_last_state then
|
9128 |
|
|
-- request a sample as soon as we arrive in this state.
|
9129 |
|
|
-- the default value of sig_mmc_start is zero!
|
9130 |
|
|
sig_mmc_start <= '1';
|
9131 |
|
|
end if;
|
9132 |
|
|
|
9133 |
|
|
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
|
9134 |
|
|
-- a sample has been collected, go to next PLL phase
|
9135 |
|
|
v_remaining_samples := v_remaining_samples - 1;
|
9136 |
|
|
sig_trk_state <= s_trk_next_phase;
|
9137 |
|
|
end if;
|
9138 |
|
|
end if;
|
9139 |
|
|
|
9140 |
|
|
|
9141 |
|
|
when s_trk_next_phase =>
|
9142 |
|
|
sig_trk_pll_start_reconfig <= '1';
|
9143 |
|
|
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
|
9144 |
|
|
|
9145 |
|
|
if sig_phs_shft_start = '1' then
|
9146 |
|
|
sig_trk_pll_start_reconfig <= '0';
|
9147 |
|
|
end if;
|
9148 |
|
|
|
9149 |
|
|
if sig_phs_shft_end = '1' then
|
9150 |
|
|
sig_trk_state <= s_trk_mimic_sample;
|
9151 |
|
|
end if;
|
9152 |
|
|
|
9153 |
|
|
|
9154 |
|
|
when s_trk_cdvw_calc =>
|
9155 |
|
|
if sig_trk_state /= sig_trk_last_state then
|
9156 |
|
|
-- reset variables we are interested in when we first arrive in this state
|
9157 |
|
|
sig_trk_cdvw_calc <= '1';
|
9158 |
|
|
report dgrb_report_prefix & "gathered mimic phase samples DGRB_MIMIC_SAMPLES: " & str(sig_cdvw_state.working_window(sig_cdvw_state.working_window'high downto sig_cdvw_state.working_window'length - PLL_STEPS_PER_CYCLE)) severity note;
|
9159 |
|
|
else
|
9160 |
|
|
sig_trk_state <= s_trk_cdvw_wait;
|
9161 |
|
|
end if;
|
9162 |
|
|
|
9163 |
|
|
|
9164 |
|
|
when s_trk_cdvw_wait =>
|
9165 |
|
|
if sig_cdvw_state.status /= calculating then
|
9166 |
|
|
if sig_cdvw_state.status = valid_result then
|
9167 |
|
|
report dgrb_report_prefix & "mimic window successfully found." severity note;
|
9168 |
|
|
if sig_mimic_cdv_found = '0' then -- first run of tracking operation
|
9169 |
|
|
sig_mimic_cdv_found <= '1';
|
9170 |
|
|
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
|
9171 |
|
|
sig_trk_state <= s_trk_complete;
|
9172 |
|
|
else -- subsequent tracking operation runs
|
9173 |
|
|
sig_mimic_delta <= sig_mimic_cdv - sig_cdvw_state.largest_window_centre;
|
9174 |
|
|
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
|
9175 |
|
|
sig_trk_state <= s_trk_cdvw_drift;
|
9176 |
|
|
end if;
|
9177 |
|
|
else
|
9178 |
|
|
report dgrb_report_prefix & "couldn't find a data-valid window for tracking." severity warning;
|
9179 |
|
|
sig_trk_ack <= '1';
|
9180 |
|
|
sig_trk_err <= '1';
|
9181 |
|
|
sig_trk_state <= s_trk_idle;
|
9182 |
|
|
|
9183 |
|
|
-- set resync result code
|
9184 |
|
|
case sig_cdvw_state.status is
|
9185 |
|
|
when no_invalid_phases =>
|
9186 |
|
|
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_INVALID_PHASES, sig_trk_result'length));
|
9187 |
|
|
when multiple_equal_windows =>
|
9188 |
|
|
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_trk_result'length));
|
9189 |
|
|
when no_valid_phases =>
|
9190 |
|
|
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_trk_result'length));
|
9191 |
|
|
when others =>
|
9192 |
|
|
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_trk_result'length));
|
9193 |
|
|
end case;
|
9194 |
|
|
end if;
|
9195 |
|
|
end if;
|
9196 |
|
|
|
9197 |
|
|
when s_trk_cdvw_drift => -- calculate the drift in rsc phase
|
9198 |
|
|
-- pipeline stage 1
|
9199 |
|
|
if abs(sig_mimic_delta) > PLL_STEPS_PER_CYCLE/2 then
|
9200 |
|
|
sig_large_drift_seen <= '1';
|
9201 |
|
|
else
|
9202 |
|
|
sig_large_drift_seen <= '0';
|
9203 |
|
|
end if;
|
9204 |
|
|
|
9205 |
|
|
--pipeline stage 2
|
9206 |
|
|
if sig_trk_state = sig_trk_last_state then
|
9207 |
|
|
if sig_large_drift_seen = '1' then
|
9208 |
|
|
if sig_mimic_delta < 0 then -- anti-clockwise movement
|
9209 |
|
|
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta + PLL_STEPS_PER_CYCLE;
|
9210 |
|
|
else -- clockwise movement
|
9211 |
|
|
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta - PLL_STEPS_PER_CYCLE;
|
9212 |
|
|
end if;
|
9213 |
|
|
else
|
9214 |
|
|
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta;
|
9215 |
|
|
end if;
|
9216 |
|
|
sig_trk_state <= s_trk_adjust_resync;
|
9217 |
|
|
end if;
|
9218 |
|
|
|
9219 |
|
|
when s_trk_adjust_resync =>
|
9220 |
|
|
sig_trk_pll_select <= pll_resync_clk_index;
|
9221 |
|
|
|
9222 |
|
|
sig_trk_pll_start_reconfig <= '1';
|
9223 |
|
|
|
9224 |
|
|
if sig_trk_state /= sig_trk_last_state then
|
9225 |
|
|
if sig_req_rsc_shift < 0 then
|
9226 |
|
|
sig_trk_pll_inc_dec_n <= '1';
|
9227 |
|
|
sig_req_rsc_shift <= sig_req_rsc_shift + 1;
|
9228 |
|
|
sig_rsc_drift <= sig_rsc_drift + 1;
|
9229 |
|
|
elsif sig_req_rsc_shift > 0 then
|
9230 |
|
|
sig_trk_pll_inc_dec_n <= '0';
|
9231 |
|
|
sig_req_rsc_shift <= sig_req_rsc_shift - 1;
|
9232 |
|
|
sig_rsc_drift <= sig_rsc_drift - 1;
|
9233 |
|
|
else
|
9234 |
|
|
sig_trk_state <= s_trk_complete;
|
9235 |
|
|
sig_trk_pll_start_reconfig <= '0';
|
9236 |
|
|
end if;
|
9237 |
|
|
else
|
9238 |
|
|
sig_trk_pll_inc_dec_n <= sig_trk_pll_inc_dec_n; -- maintain previous value
|
9239 |
|
|
end if;
|
9240 |
|
|
|
9241 |
|
|
if abs(sig_rsc_drift) = MAX_RSC_DRIFT_IN_PHASES then
|
9242 |
|
|
report dgrb_report_prefix & " a maximum absolute change in resync_clk of " & integer'image(sig_rsc_drift) & " phases has " & LF &
|
9243 |
|
|
" occurred (since read resynch phase calibration) during tracking" severity failure;
|
9244 |
|
|
sig_trk_err <= '1';
|
9245 |
|
|
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_MAX_TRK_SHFT_EXCEEDED, sig_trk_result'length));
|
9246 |
|
|
end if;
|
9247 |
|
|
|
9248 |
|
|
if sig_phs_shft_start = '1' then
|
9249 |
|
|
sig_trk_pll_start_reconfig <= '0';
|
9250 |
|
|
end if;
|
9251 |
|
|
|
9252 |
|
|
if sig_phs_shft_end = '1' then
|
9253 |
|
|
sig_trk_state <= s_trk_complete;
|
9254 |
|
|
end if;
|
9255 |
|
|
|
9256 |
|
|
|
9257 |
|
|
when s_trk_complete =>
|
9258 |
|
|
sig_trk_ack <= '1';
|
9259 |
|
|
|
9260 |
|
|
end case;
|
9261 |
|
|
|
9262 |
|
|
sig_trk_last_state <= sig_trk_state;
|
9263 |
|
|
else
|
9264 |
|
|
sig_trk_state <= s_trk_idle;
|
9265 |
|
|
sig_trk_last_state <= s_trk_idle;
|
9266 |
|
|
end if;
|
9267 |
|
|
end if;
|
9268 |
|
|
|
9269 |
|
|
end process;
|
9270 |
|
|
|
9271 |
|
|
|
9272 |
|
|
rsc_drift: process (sig_rsc_drift)
|
9273 |
|
|
begin
|
9274 |
|
|
sig_trk_rsc_drift <= sig_rsc_drift; -- communicate tracking shift to rsc process
|
9275 |
|
|
end process;
|
9276 |
|
|
|
9277 |
|
|
|
9278 |
|
|
end block; -- tracking signals
|
9279 |
|
|
|
9280 |
|
|
-- ------------------------------------------------------------------
|
9281 |
|
|
-- write-datapath (WDP) ` and on-chip-termination (OCT) signal
|
9282 |
|
|
-- ------------------------------------------------------------------
|
9283 |
|
|
wdp_oct : process(clk,rst_n)
|
9284 |
|
|
begin
|
9285 |
|
|
if rst_n = '0' then
|
9286 |
|
|
seq_oct_value <= c_set_oct_to_rs;
|
9287 |
|
|
dgrb_wdp_ovride <= '0';
|
9288 |
|
|
elsif rising_edge(clk) then
|
9289 |
|
|
if ((sig_dgrb_state = s_idle) or (EN_OCT = 0)) then
|
9290 |
|
|
seq_oct_value <= c_set_oct_to_rs;
|
9291 |
|
|
dgrb_wdp_ovride <= '0';
|
9292 |
|
|
else
|
9293 |
|
|
seq_oct_value <= c_set_oct_to_rt;
|
9294 |
|
|
dgrb_wdp_ovride <= '1';
|
9295 |
|
|
end if;
|
9296 |
|
|
end if;
|
9297 |
|
|
end process;
|
9298 |
|
|
|
9299 |
|
|
|
9300 |
|
|
-- ------------------------------------------------------------------
|
9301 |
|
|
-- handles handshaking for access to address/command
|
9302 |
|
|
-- ------------------------------------------------------------------
|
9303 |
|
|
ac_handshake_proc : process(rst_n, clk)
|
9304 |
|
|
begin
|
9305 |
|
|
if rst_n = '0' then
|
9306 |
|
|
dgrb_ctrl <= defaults;
|
9307 |
|
|
elsif rising_edge(clk) then
|
9308 |
|
|
dgrb_ctrl <= defaults;
|
9309 |
|
|
|
9310 |
|
|
if sig_dgrb_state = s_wait_admin and sig_dgrb_last_state = s_idle then
|
9311 |
|
|
dgrb_ctrl.command_ack <= '1';
|
9312 |
|
|
end if;
|
9313 |
|
|
|
9314 |
|
|
|
9315 |
|
|
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
|
9316 |
|
|
case sig_dgrb_state is
|
9317 |
|
|
when s_seek_cdvw =>
|
9318 |
|
|
dgrb_ctrl.command_err <= sig_rsc_err;
|
9319 |
|
|
dgrb_ctrl.command_result <= sig_rsc_result;
|
9320 |
|
|
when s_track =>
|
9321 |
|
|
dgrb_ctrl.command_err <= sig_trk_err;
|
9322 |
|
|
dgrb_ctrl.command_result <= sig_trk_result;
|
9323 |
|
|
when others => -- from main state machine
|
9324 |
|
|
dgrb_ctrl.command_err <= sig_cmd_err;
|
9325 |
|
|
dgrb_ctrl.command_result <= sig_cmd_result;
|
9326 |
|
|
end case;
|
9327 |
|
|
end if;
|
9328 |
|
|
|
9329 |
|
|
if ctrl_dgrb_r.command = cmd_read_mtp then -- check against command because aligned with command done not command_err
|
9330 |
|
|
dgrb_ctrl.command_err <= '0';
|
9331 |
|
|
dgrb_ctrl.command_result <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size,dgrb_ctrl.command_result'length));
|
9332 |
|
|
end if;
|
9333 |
|
|
|
9334 |
|
|
if sig_dgrb_state = s_idle and sig_dgrb_last_state = s_release_admin then
|
9335 |
|
|
dgrb_ctrl.command_done <= '1';
|
9336 |
|
|
end if;
|
9337 |
|
|
end if;
|
9338 |
|
|
end process;
|
9339 |
|
|
|
9340 |
|
|
|
9341 |
|
|
-- ------------------------------------------------------------------
|
9342 |
|
|
-- address/command state machine
|
9343 |
|
|
-- process is commanded to begin reading training patterns.
|
9344 |
|
|
-- ------------------------------------------------------------------
|
9345 |
|
|
ac_block : block
|
9346 |
|
|
|
9347 |
|
|
-- override the calibration burst length for DDR3 device support
|
9348 |
|
|
-- (requires BL8 / on the fly setting in MR in admin block)
|
9349 |
|
|
function set_read_bl ( memtype: in string ) return natural is
|
9350 |
|
|
begin
|
9351 |
|
|
|
9352 |
|
|
if memtype = "DDR3" then
|
9353 |
|
|
return 8;
|
9354 |
|
|
elsif memtype = "DDR" or memtype = "DDR2" then
|
9355 |
|
|
return c_cal_burst_len;
|
9356 |
|
|
else
|
9357 |
|
|
report dgrb_report_prefix & " a calibration burst length choice has not been set for memory type " & memtype severity failure;
|
9358 |
|
|
end if;
|
9359 |
|
|
|
9360 |
|
|
return 0;
|
9361 |
|
|
|
9362 |
|
|
end function;
|
9363 |
|
|
|
9364 |
|
|
-- parameterisation of the read algorithm by burst length
|
9365 |
|
|
constant c_poa_addr_width : natural := 6;
|
9366 |
|
|
constant c_cal_read_burst_len : natural := set_read_bl(MEM_IF_MEMTYPE);
|
9367 |
|
|
constant c_bursts_per_btp : natural := c_cal_mtp_len / c_cal_read_burst_len;
|
9368 |
|
|
constant c_read_burst_t : natural := c_cal_read_burst_len / DWIDTH_RATIO;
|
9369 |
|
|
constant c_max_rdata_valid_lat : natural := 50*(c_cal_read_burst_len / DWIDTH_RATIO); -- maximum latency that rdata_valid can ever have with respect to doing_rd
|
9370 |
|
|
constant c_rdv_ones_rd_clks : natural := (c_max_rdata_valid_lat + c_read_burst_t) / c_read_burst_t; -- number of cycles to read ones for before a pulse of zeros
|
9371 |
|
|
|
9372 |
|
|
-- array of burst training pattern addresses
|
9373 |
|
|
-- here the MTP is used in this addressing
|
9374 |
|
|
subtype t_btp_addr is natural range 0 to 2 ** MEM_IF_ADDR_WIDTH - 1;
|
9375 |
|
|
type t_btp_addr_array is array (0 to c_bursts_per_btp - 1) of t_btp_addr;
|
9376 |
|
|
|
9377 |
|
|
-- default values
|
9378 |
|
|
function defaults return t_btp_addr_array is
|
9379 |
|
|
variable v_btp_array : t_btp_addr_array;
|
9380 |
|
|
begin
|
9381 |
|
|
for i in 0 to c_bursts_per_btp - 1 loop
|
9382 |
|
|
v_btp_array(i) := 0;
|
9383 |
|
|
end loop;
|
9384 |
|
|
return v_btp_array;
|
9385 |
|
|
end function;
|
9386 |
|
|
|
9387 |
|
|
-- load btp array addresses
|
9388 |
|
|
-- Note: this scales to burst lengths of 2, 4 and 8
|
9389 |
|
|
-- the settings here are specific to the choice of training pattern and need updating if the pattern changes
|
9390 |
|
|
function set_btp_addr (mtp_almt : natural ) return t_btp_addr_array is
|
9391 |
|
|
variable v_addr_array : t_btp_addr_array;
|
9392 |
|
|
begin
|
9393 |
|
|
for i in 0 to 8/c_cal_read_burst_len - 1 loop
|
9394 |
|
|
|
9395 |
|
|
-- set addresses for xF5 data
|
9396 |
|
|
v_addr_array((c_bursts_per_btp - 1) - i) := MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + i*c_cal_read_burst_len;
|
9397 |
|
|
|
9398 |
|
|
-- set addresses for x30 data (based on mtp alignment)
|
9399 |
|
|
if mtp_almt = 0 then
|
9400 |
|
|
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + i*c_cal_read_burst_len;
|
9401 |
|
|
else
|
9402 |
|
|
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + i*c_cal_read_burst_len;
|
9403 |
|
|
end if;
|
9404 |
|
|
|
9405 |
|
|
end loop;
|
9406 |
|
|
|
9407 |
|
|
return v_addr_array;
|
9408 |
|
|
|
9409 |
|
|
end function;
|
9410 |
|
|
|
9411 |
|
|
|
9412 |
|
|
function find_poa_cycle_period return natural is
|
9413 |
|
|
-- Returns the period over which the postamble reads
|
9414 |
|
|
-- repeat in c_read_burst_t units.
|
9415 |
|
|
variable v_num_bursts : natural;
|
9416 |
|
|
begin
|
9417 |
|
|
v_num_bursts := 2 ** c_poa_addr_width / c_read_burst_t;
|
9418 |
|
|
if v_num_bursts * c_read_burst_t < 2**c_poa_addr_width then
|
9419 |
|
|
v_num_bursts := v_num_bursts + 1;
|
9420 |
|
|
end if;
|
9421 |
|
|
|
9422 |
|
|
v_num_bursts := v_num_bursts + c_bursts_per_btp + 1;
|
9423 |
|
|
|
9424 |
|
|
return v_num_bursts;
|
9425 |
|
|
end function;
|
9426 |
|
|
|
9427 |
|
|
|
9428 |
|
|
function get_poa_burst_addr(burst_count : in natural; mtp_almt : in natural) return t_btp_addr is
|
9429 |
|
|
variable v_addr : t_btp_addr;
|
9430 |
|
|
begin
|
9431 |
|
|
if burst_count = 0 then
|
9432 |
|
|
if mtp_almt = 0 then
|
9433 |
|
|
v_addr := c_cal_ofs_x30_almt_1;
|
9434 |
|
|
elsif mtp_almt = 1 then
|
9435 |
|
|
v_addr := c_cal_ofs_x30_almt_0;
|
9436 |
|
|
else
|
9437 |
|
|
report "Unsupported mtp_almt " & natural'image(mtp_almt) severity failure;
|
9438 |
|
|
end if;
|
9439 |
|
|
|
9440 |
|
|
-- address gets incremented by four if in burst-length four.
|
9441 |
|
|
v_addr := v_addr + (8 - c_cal_read_burst_len);
|
9442 |
|
|
else
|
9443 |
|
|
v_addr := c_cal_ofs_zeros;
|
9444 |
|
|
end if;
|
9445 |
|
|
|
9446 |
|
|
return v_addr;
|
9447 |
|
|
end function;
|
9448 |
|
|
|
9449 |
|
|
|
9450 |
|
|
signal btp_addr_array : t_btp_addr_array; -- burst training pattern addresses
|
9451 |
|
|
|
9452 |
|
|
signal sig_addr_cmd_state : t_ac_state;
|
9453 |
|
|
signal sig_addr_cmd_last_state : t_ac_state;
|
9454 |
|
|
|
9455 |
|
|
signal sig_doing_rd_count : integer range 0 to c_read_burst_t - 1;
|
9456 |
|
|
signal sig_count : integer range 0 to 2**8 - 1;
|
9457 |
|
|
signal sig_setup : integer range c_max_read_lat downto 0;
|
9458 |
|
|
signal sig_burst_count : integer range 0 to c_read_burst_t;
|
9459 |
|
|
|
9460 |
|
|
begin
|
9461 |
|
|
-- handles counts for when to begin burst-reads (sig_burst_count)
|
9462 |
|
|
-- sets sig_dimm_driving_dq
|
9463 |
|
|
-- sets dgrb_ac_access_req
|
9464 |
|
|
dimm_driving_dq_proc : process(rst_n, clk)
|
9465 |
|
|
begin
|
9466 |
|
|
if rst_n /= '1' then
|
9467 |
|
|
sig_dimm_driving_dq <= '1';
|
9468 |
|
|
sig_setup <= c_max_read_lat;
|
9469 |
|
|
sig_burst_count <= 0;
|
9470 |
|
|
dgrb_ac_access_req <= '0';
|
9471 |
|
|
sig_ac_even <= '0';
|
9472 |
|
|
elsif rising_edge(clk) then
|
9473 |
|
|
sig_dimm_driving_dq <= '0';
|
9474 |
|
|
|
9475 |
|
|
if sig_addr_cmd_state /= s_ac_idle and sig_addr_cmd_state /= s_ac_relax then
|
9476 |
|
|
dgrb_ac_access_req <= '1';
|
9477 |
|
|
else
|
9478 |
|
|
dgrb_ac_access_req <= '0';
|
9479 |
|
|
end if;
|
9480 |
|
|
|
9481 |
|
|
case sig_addr_cmd_state is
|
9482 |
|
|
when s_ac_read_mtp | s_ac_read_rdv | s_ac_read_wd_lat | s_ac_read_poa_mtp =>
|
9483 |
|
|
sig_ac_even <= not sig_ac_even;
|
9484 |
|
|
|
9485 |
|
|
-- a counter that keeps track of when we are ready
|
9486 |
|
|
-- to issue a burst read. Issue burst read eigvery
|
9487 |
|
|
-- time we are at zero.
|
9488 |
|
|
if sig_burst_count = 0 then
|
9489 |
|
|
sig_burst_count <= c_read_burst_t - 1;
|
9490 |
|
|
else
|
9491 |
|
|
sig_burst_count <= sig_burst_count - 1;
|
9492 |
|
|
end if;
|
9493 |
|
|
|
9494 |
|
|
|
9495 |
|
|
if dgrb_ac_access_gnt /= '1' then
|
9496 |
|
|
sig_setup <= c_max_read_lat;
|
9497 |
|
|
else
|
9498 |
|
|
-- primes reads
|
9499 |
|
|
-- signal that dimms are driving dq pins after
|
9500 |
|
|
-- at least c_max_read_lat clock cycles have passed.
|
9501 |
|
|
--
|
9502 |
|
|
if sig_setup = 0 then
|
9503 |
|
|
sig_dimm_driving_dq <= '1';
|
9504 |
|
|
elsif dgrb_ac_access_gnt = '1' then
|
9505 |
|
|
sig_setup <= sig_setup - 1;
|
9506 |
|
|
end if;
|
9507 |
|
|
end if;
|
9508 |
|
|
|
9509 |
|
|
|
9510 |
|
|
when s_ac_relax =>
|
9511 |
|
|
sig_dimm_driving_dq <= '1';
|
9512 |
|
|
sig_burst_count <= 0;
|
9513 |
|
|
sig_ac_even <= '0';
|
9514 |
|
|
|
9515 |
|
|
|
9516 |
|
|
when others =>
|
9517 |
|
|
sig_burst_count <= 0;
|
9518 |
|
|
sig_ac_even <= '0';
|
9519 |
|
|
|
9520 |
|
|
end case;
|
9521 |
|
|
end if;
|
9522 |
|
|
end process;
|
9523 |
|
|
|
9524 |
|
|
|
9525 |
|
|
ac_proc : process(rst_n, clk)
|
9526 |
|
|
begin
|
9527 |
|
|
if rst_n = '0' then
|
9528 |
|
|
sig_count <= 0;
|
9529 |
|
|
sig_addr_cmd_state <= s_ac_idle;
|
9530 |
|
|
sig_addr_cmd_last_state <= s_ac_idle;
|
9531 |
|
|
sig_doing_rd_count <= 0;
|
9532 |
|
|
|
9533 |
|
|
sig_addr_cmd <= reset(c_seq_addr_cmd_config);
|
9534 |
|
|
|
9535 |
|
|
btp_addr_array <= defaults;
|
9536 |
|
|
sig_doing_rd <= (others => '0');
|
9537 |
|
|
|
9538 |
|
|
elsif rising_edge(clk) then
|
9539 |
|
|
assert c_cal_mtp_len mod c_cal_read_burst_len = 0 report dgrb_report_prefix & "burst-training pattern length must be a multiple of burst-length." severity failure;
|
9540 |
|
|
assert MEM_IF_CAL_BANK < 2**MEM_IF_BANKADDR_WIDTH report dgrb_report_prefix & "MEM_IF_CAL_BANK out of range." severity failure;
|
9541 |
|
|
assert MEM_IF_CAL_BASE_COL < 2**MEM_IF_ADDR_WIDTH - 1 - C_CAL_DATA_LEN report dgrb_report_prefix & "MEM_IF_CAL_BASE_COL out of range." severity failure;
|
9542 |
|
|
|
9543 |
|
|
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
|
9544 |
|
|
|
9545 |
|
|
if sig_ac_req /= sig_addr_cmd_state and sig_addr_cmd_state /= s_ac_idle then
|
9546 |
|
|
-- and dgrb_ac_access_gnt = '1'
|
9547 |
|
|
sig_addr_cmd_state <= s_ac_relax;
|
9548 |
|
|
else
|
9549 |
|
|
sig_addr_cmd_state <= sig_ac_req;
|
9550 |
|
|
end if;
|
9551 |
|
|
|
9552 |
|
|
if sig_doing_rd_count /= 0 then
|
9553 |
|
|
sig_doing_rd <= (others => '1');
|
9554 |
|
|
sig_doing_rd_count <= sig_doing_rd_count - 1;
|
9555 |
|
|
else
|
9556 |
|
|
sig_doing_rd <= (others => '0');
|
9557 |
|
|
end if;
|
9558 |
|
|
|
9559 |
|
|
case sig_addr_cmd_state is
|
9560 |
|
|
when s_ac_idle =>
|
9561 |
|
|
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
|
9562 |
|
|
|
9563 |
|
|
|
9564 |
|
|
when s_ac_relax =>
|
9565 |
|
|
-- waits at least c_max_read_lat before returning to s_ac_idle state
|
9566 |
|
|
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
|
9567 |
|
|
sig_count <= c_max_read_lat;
|
9568 |
|
|
else
|
9569 |
|
|
if sig_count = 0 then
|
9570 |
|
|
sig_addr_cmd_state <= s_ac_idle;
|
9571 |
|
|
else
|
9572 |
|
|
sig_count <= sig_count - 1;
|
9573 |
|
|
end if;
|
9574 |
|
|
end if;
|
9575 |
|
|
|
9576 |
|
|
when s_ac_read_mtp =>
|
9577 |
|
|
-- reads 'more'-training pattern
|
9578 |
|
|
-- issue read commands for proper addresses
|
9579 |
|
|
|
9580 |
|
|
-- set burst training pattern (mtp in this case) addresses
|
9581 |
|
|
btp_addr_array <= set_btp_addr(current_mtp_almt);
|
9582 |
|
|
|
9583 |
|
|
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
|
9584 |
|
|
sig_count <= c_bursts_per_btp - 1; -- counts number of bursts in a training pattern
|
9585 |
|
|
else
|
9586 |
|
|
sig_doing_rd <= (others => '1');
|
9587 |
|
|
|
9588 |
|
|
-- issue a read command every c_read_burst_t clock cycles
|
9589 |
|
|
if sig_burst_count = 0 then
|
9590 |
|
|
|
9591 |
|
|
-- decide which read command to issue
|
9592 |
|
|
for i in 0 to c_bursts_per_btp - 1 loop
|
9593 |
|
|
|
9594 |
|
|
if sig_count = i then
|
9595 |
|
|
|
9596 |
|
|
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
|
9597 |
|
|
sig_addr_cmd, -- previous value
|
9598 |
|
|
MEM_IF_CAL_BANK, -- bank
|
9599 |
|
|
btp_addr_array(i), -- column address
|
9600 |
|
|
2**current_cs, -- rank
|
9601 |
|
|
c_cal_read_burst_len, -- burst length
|
9602 |
|
|
false);
|
9603 |
|
|
end if;
|
9604 |
|
|
|
9605 |
|
|
end loop;
|
9606 |
|
|
|
9607 |
|
|
-- Set next value of count
|
9608 |
|
|
if sig_count = 0 then
|
9609 |
|
|
sig_count <= c_bursts_per_btp - 1;
|
9610 |
|
|
else
|
9611 |
|
|
sig_count <= sig_count - 1;
|
9612 |
|
|
end if;
|
9613 |
|
|
|
9614 |
|
|
end if;
|
9615 |
|
|
|
9616 |
|
|
end if;
|
9617 |
|
|
|
9618 |
|
|
when s_ac_read_poa_mtp =>
|
9619 |
|
|
-- Postamble rdata/rdata_valid Activity:
|
9620 |
|
|
--
|
9621 |
|
|
--
|
9622 |
|
|
-- (0) (1) (2)
|
9623 |
|
|
-- ; ; ; ;
|
9624 |
|
|
-- _________ __ ____________ _____________ _______ _________
|
9625 |
|
|
-- \ / \ / \ \ \ / \ /
|
9626 |
|
|
-- (a) rdata[0] 00000000 X 11 X 0000000000 / / 0000000000 X MTP X 00000000
|
9627 |
|
|
-- _________/ \__/ \____________\ \____________/ \_______/ \_________
|
9628 |
|
|
-- ; ; ; ;
|
9629 |
|
|
-- ; ; ; ;
|
9630 |
|
|
-- _________ / / _________
|
9631 |
|
|
-- rdata_valid ____| |_____________\ \_____________| |__________
|
9632 |
|
|
--
|
9633 |
|
|
-- ;<- (b) ->;<------------(c)------------>; ;
|
9634 |
|
|
-- ; ; ; ;
|
9635 |
|
|
--
|
9636 |
|
|
--
|
9637 |
|
|
-- This block must issue reads and drive doing_rd to place the above pattern on
|
9638 |
|
|
-- the rdata and rdata_valid ports. MTP will most likely come back corrupted but
|
9639 |
|
|
-- the postamble block (poa_block) will make the necessary adjustments to improve
|
9640 |
|
|
-- matters.
|
9641 |
|
|
--
|
9642 |
|
|
-- (a) Read zeros followed by two ones. The two will be at the end of a burst.
|
9643 |
|
|
-- Assert rdata_valid only during the burst containing the ones.
|
9644 |
|
|
-- (b) c_read_burst_t clock cycles.
|
9645 |
|
|
-- (c) Must be greater than but NOT equal to maximum postamble latency clock
|
9646 |
|
|
-- cycles. Another way: c_min = (max_poa_lat + 1) phy clock cycles. This
|
9647 |
|
|
-- must also be long enough to allow the postamble block to respond to a
|
9648 |
|
|
-- the seq_poa_lat_dec_1x signal, but this requirement is less stringent
|
9649 |
|
|
-- than the first so that we can ignore it.
|
9650 |
|
|
--
|
9651 |
|
|
-- The find_poa_cycle_period function should return (b+c)/c_read_burst_t
|
9652 |
|
|
-- rounded up to the next largest integer.
|
9653 |
|
|
--
|
9654 |
|
|
--
|
9655 |
|
|
|
9656 |
|
|
-- set burst training pattern (mtp in this case) addresses
|
9657 |
|
|
btp_addr_array <= set_btp_addr(current_mtp_almt);
|
9658 |
|
|
|
9659 |
|
|
-- issue read commands for proper addresses
|
9660 |
|
|
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
|
9661 |
|
|
--sig_count <= 2*c_bursts_per_btp - 1; -- counts number of bursts in a training pattern
|
9662 |
|
|
sig_count <= find_poa_cycle_period - 1; -- length of read patter in bursts.
|
9663 |
|
|
elsif dgrb_ac_access_gnt = '1' then
|
9664 |
|
|
-- only begin operation once dgrb_ac_access_gnt has been issued
|
9665 |
|
|
-- otherwise rdata_valid may be asserted when rdasta is not
|
9666 |
|
|
-- valid.
|
9667 |
|
|
--
|
9668 |
|
|
-- *** WARNING: BE SAFE. DON'T LET THIS HAPPEN TO YOU: ***
|
9669 |
|
|
--
|
9670 |
|
|
-- ; ; ; ; ; ;
|
9671 |
|
|
-- ; _______ ; ; _______ ; ; _______
|
9672 |
|
|
-- XXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX
|
9673 |
|
|
-- addr/cmd XXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX
|
9674 |
|
|
-- XXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX
|
9675 |
|
|
-- ; ; ; ; ; ;
|
9676 |
|
|
-- ; ; ; ; ; ;
|
9677 |
|
|
-- ; ; ; ; ; ; _______
|
9678 |
|
|
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX / \
|
9679 |
|
|
-- rdata XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX MTP X
|
9680 |
|
|
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX \_______/
|
9681 |
|
|
-- ; ; ; ; ; ;
|
9682 |
|
|
-- ; ; ; ; ; ;
|
9683 |
|
|
-- _________ _________ _________
|
9684 |
|
|
-- doing_rd ____| |_________| |_________| |__________
|
9685 |
|
|
-- ; ; ; ; ; ;
|
9686 |
|
|
-- ; ; ; ; ; ;
|
9687 |
|
|
-- __________________________________________________
|
9688 |
|
|
-- ac_accesss_gnt ______________|
|
9689 |
|
|
-- ; ; ; ; ; ;
|
9690 |
|
|
-- ; ; ; ; ; ;
|
9691 |
|
|
-- _________ _________
|
9692 |
|
|
-- rdata_valid __________________________________| |_________| |
|
9693 |
|
|
-- ; ; ; ; ; ;
|
9694 |
|
|
--
|
9695 |
|
|
-- (0) (1) (2)
|
9696 |
|
|
--
|
9697 |
|
|
--
|
9698 |
|
|
-- Cmmand and doing_rd issued at (0). The doing_rd signal enters the
|
9699 |
|
|
-- rdata_valid pipe here so that it will return on rdata_valid with the
|
9700 |
|
|
-- expected latency (at this point in calibration, rdata_valid and adv_rd_lat
|
9701 |
|
|
-- should be properly calibrated). Unlike doing_rd, since ac_access_gnt is not
|
9702 |
|
|
-- asserted the READ command at (0) is never actually issued. This results
|
9703 |
|
|
-- in the situation at (2) where rdata is undefined yet rdata_valid indicates
|
9704 |
|
|
-- valid data. The moral of this story is to wait for ac_access_gnt = '1'
|
9705 |
|
|
-- before issuing commands when it is important that rdata_valid be accurate.
|
9706 |
|
|
--
|
9707 |
|
|
--
|
9708 |
|
|
--
|
9709 |
|
|
--
|
9710 |
|
|
|
9711 |
|
|
if sig_burst_count = 0 then
|
9712 |
|
|
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
|
9713 |
|
|
sig_addr_cmd, -- previous value
|
9714 |
|
|
MEM_IF_CAL_BANK, -- bank
|
9715 |
|
|
get_poa_burst_addr(sig_count, current_mtp_almt),-- column address
|
9716 |
|
|
2**current_cs, -- rank
|
9717 |
|
|
c_cal_read_burst_len, -- burst length
|
9718 |
|
|
false);
|
9719 |
|
|
|
9720 |
|
|
|
9721 |
|
|
-- Set doing_rd
|
9722 |
|
|
if sig_count = 0 then
|
9723 |
|
|
sig_doing_rd <= (others => '1');
|
9724 |
|
|
sig_doing_rd_count <= c_read_burst_t - 1; -- Extend doing_rd pulse by this many phy_clk cycles.
|
9725 |
|
|
end if;
|
9726 |
|
|
|
9727 |
|
|
|
9728 |
|
|
-- Set next value of count
|
9729 |
|
|
if sig_count = 0 then
|
9730 |
|
|
sig_count <= find_poa_cycle_period - 1; -- read for one period then relax (no read) for same time period
|
9731 |
|
|
else
|
9732 |
|
|
sig_count <= sig_count - 1;
|
9733 |
|
|
end if;
|
9734 |
|
|
end if;
|
9735 |
|
|
end if;
|
9736 |
|
|
|
9737 |
|
|
|
9738 |
|
|
when s_ac_read_rdv =>
|
9739 |
|
|
assert c_max_rdata_valid_lat mod c_read_burst_t = 0 report dgrb_report_prefix & "c_max_rdata_valid_lat must be a multiple of c_read_burst_t." severity failure;
|
9740 |
|
|
|
9741 |
|
|
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
|
9742 |
|
|
sig_count <= c_rdv_ones_rd_clks - 1;
|
9743 |
|
|
else
|
9744 |
|
|
if sig_burst_count = 0 then
|
9745 |
|
|
if sig_count = 0 then
|
9746 |
|
|
-- expecting to read ZEROS
|
9747 |
|
|
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
|
9748 |
|
|
sig_addr_cmd, -- previous valid
|
9749 |
|
|
MEM_IF_CAL_BANK, -- bank
|
9750 |
|
|
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ZEROS, -- column
|
9751 |
|
|
2**current_cs, -- rank
|
9752 |
|
|
c_cal_read_burst_len, -- burst length
|
9753 |
|
|
false);
|
9754 |
|
|
|
9755 |
|
|
else
|
9756 |
|
|
-- expecting to read ONES
|
9757 |
|
|
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
|
9758 |
|
|
sig_addr_cmd, -- previous value
|
9759 |
|
|
MEM_IF_CAL_BANK, -- bank
|
9760 |
|
|
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ONES, -- column address
|
9761 |
|
|
2**current_cs, -- rank
|
9762 |
|
|
c_cal_read_burst_len, -- op length
|
9763 |
|
|
false);
|
9764 |
|
|
end if;
|
9765 |
|
|
|
9766 |
|
|
if sig_count = 0 then
|
9767 |
|
|
sig_count <= c_rdv_ones_rd_clks - 1;
|
9768 |
|
|
else
|
9769 |
|
|
sig_count <= sig_count - 1;
|
9770 |
|
|
end if;
|
9771 |
|
|
end if;
|
9772 |
|
|
|
9773 |
|
|
if (sig_count = c_rdv_ones_rd_clks - 1 and sig_burst_count = 1) or
|
9774 |
|
|
(sig_count = 0 and c_read_burst_t = 1) then
|
9775 |
|
|
-- the last burst read- that was issued was supposed to read only zeros
|
9776 |
|
|
-- a burst read command will be issued on the next clock cycle
|
9777 |
|
|
--
|
9778 |
|
|
-- A long (>= maximim rdata_valid latency) series of burst reads are
|
9779 |
|
|
-- issued for ONES.
|
9780 |
|
|
-- Into this stream a single burst read for ZEROs is issued. After
|
9781 |
|
|
-- the ZERO read command is issued, rdata_valid needs to come back
|
9782 |
|
|
-- high one clock cycle before the next read command (reading ONES
|
9783 |
|
|
-- again) is issued. Since the rdata_valid is just a delayed
|
9784 |
|
|
-- version of doing_rd, doing_rd needs to exhibit the same behaviour.
|
9785 |
|
|
--
|
9786 |
|
|
-- for FR (burst length 4): require that doing_rd high 1 clock cycle after cs_n is low
|
9787 |
|
|
-- ____ ____ ____ ____ ____ ____ ____ ____ ____
|
9788 |
|
|
-- clk ____| |____| |____| |____| |____| |____| |____| |____| |____|
|
9789 |
|
|
--
|
9790 |
|
|
-- ___ _______ _______ _______ _______
|
9791 |
|
|
-- \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXX
|
9792 |
|
|
-- addr XXXXXXXXXXX ONES XXXXXXXXXXX ONES XXXXXXXXXXX ZEROS XXXXXXXXXXX ONES XXXXX--> Repeat
|
9793 |
|
|
-- ___/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXX
|
9794 |
|
|
--
|
9795 |
|
|
-- _________ _________ _________ _________ ____
|
9796 |
|
|
-- cs_n ____| |_________| |_________| |_________| |_________|
|
9797 |
|
|
--
|
9798 |
|
|
-- _________
|
9799 |
|
|
-- doing_rd ________________________________________________________________| |______________
|
9800 |
|
|
--
|
9801 |
|
|
--
|
9802 |
|
|
-- for HR: require that doing_rd high in the same clock cycle as cs_n is low
|
9803 |
|
|
--
|
9804 |
|
|
|
9805 |
|
|
sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) <= '1';
|
9806 |
|
|
|
9807 |
|
|
end if;
|
9808 |
|
|
end if;
|
9809 |
|
|
|
9810 |
|
|
|
9811 |
|
|
when s_ac_read_wd_lat =>
|
9812 |
|
|
-- continuously issues reads on the memory locations
|
9813 |
|
|
-- containing write latency addr=[2*c_cal_burst_len - (3*c_cal_burst_len - 1)]
|
9814 |
|
|
|
9815 |
|
|
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
|
9816 |
|
|
-- no initialization required here. Must still wait
|
9817 |
|
|
-- a clock cycle before beginning operations so that
|
9818 |
|
|
-- we are properly synchronized with
|
9819 |
|
|
-- dimm_driving_dq_proc.
|
9820 |
|
|
else
|
9821 |
|
|
if sig_burst_count = 0 then
|
9822 |
|
|
if sig_dimm_driving_dq = '1' then
|
9823 |
|
|
sig_doing_rd <= (others => '1');
|
9824 |
|
|
end if;
|
9825 |
|
|
|
9826 |
|
|
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
|
9827 |
|
|
sig_addr_cmd, -- previous value
|
9828 |
|
|
MEM_IF_CAL_BANK, -- bank
|
9829 |
|
|
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- column
|
9830 |
|
|
2**current_cs, -- rank
|
9831 |
|
|
c_cal_read_burst_len,
|
9832 |
|
|
false);
|
9833 |
|
|
end if;
|
9834 |
|
|
end if;
|
9835 |
|
|
|
9836 |
|
|
|
9837 |
|
|
when others =>
|
9838 |
|
|
report dgrb_report_prefix & "undefined state in addr_cmd_proc" severity error;
|
9839 |
|
|
sig_addr_cmd_state <= s_ac_idle;
|
9840 |
|
|
end case;
|
9841 |
|
|
|
9842 |
|
|
-- mask odt signal
|
9843 |
|
|
for i in 0 to (DWIDTH_RATIO/2)-1 loop
|
9844 |
|
|
sig_addr_cmd(i).odt <= odt_settings(current_cs).read;
|
9845 |
|
|
end loop;
|
9846 |
|
|
|
9847 |
|
|
sig_addr_cmd_last_state <= sig_addr_cmd_state;
|
9848 |
|
|
end if;
|
9849 |
|
|
|
9850 |
|
|
end process;
|
9851 |
|
|
|
9852 |
|
|
end block ac_block;
|
9853 |
|
|
|
9854 |
|
|
end architecture struct;
|
9855 |
|
|
|
9856 |
|
|
--
|
9857 |
|
|
|
9858 |
|
|
-- -----------------------------------------------------------------------------
|
9859 |
|
|
-- Abstract : data gatherer (write bias) [dgwb] block for the non-levelling
|
9860 |
|
|
-- AFI PHY sequencer
|
9861 |
|
|
-- -----------------------------------------------------------------------------
|
9862 |
|
|
|
9863 |
|
|
|
9864 |
|
|
library ieee;
|
9865 |
|
|
use ieee.std_logic_1164.all;
|
9866 |
|
|
use ieee.numeric_std.all;
|
9867 |
|
|
|
9868 |
|
|
|
9869 |
|
|
library work;
|
9870 |
|
|
|
9871 |
|
|
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
|
9872 |
|
|
-- thoughout the sequencer and will not change (for constants which may change between sequencer
|
9873 |
|
|
-- instances generics are used)
|
9874 |
|
|
--
|
9875 |
|
|
use work.altera_ddr_phy_alt_mem_phy_constants_pkg.all;
|
9876 |
|
|
|
9877 |
|
|
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
|
9878 |
|
|
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
|
9879 |
|
|
-- for the stages of DRAM memory calibration.
|
9880 |
|
|
--
|
9881 |
|
|
use work.altera_ddr_phy_alt_mem_phy_record_pkg.all;
|
9882 |
|
|
|
9883 |
|
|
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
|
9884 |
|
|
-- and command signals in one record and unify the functions operating on this record.
|
9885 |
|
|
--
|
9886 |
|
|
use work.altera_ddr_phy_alt_mem_phy_addr_cmd_pkg.all;
|
9887 |
|
|
|
9888 |
|
|
--
|
9889 |
|
|
entity altera_ddr_phy_alt_mem_phy_dgwb is
|
9890 |
|
|
generic (
|
9891 |
|
|
-- Physical IF width definitions
|
9892 |
|
|
MEM_IF_DQS_WIDTH : natural := 9;
|
9893 |
|
|
MEM_IF_DQ_PER_DQS : natural := 8;
|
9894 |
|
|
MEM_IF_DWIDTH : natural := 72;
|
9895 |
|
|
MEM_IF_DM_WIDTH : natural := 9;
|
9896 |
|
|
DWIDTH_RATIO : natural := 4;
|
9897 |
|
|
MEM_IF_ADDR_WIDTH : natural := 13;
|
9898 |
|
|
MEM_IF_BANKADDR_WIDTH : natural := 3;
|
9899 |
|
|
MEM_IF_NUM_RANKS : natural := 1; -- The sequencer outputs memory control signals of width num_ranks
|
9900 |
|
|
MEM_IF_MEMTYPE : string := "DDR2";
|
9901 |
|
|
ADV_LAT_WIDTH : natural := 5;
|
9902 |
|
|
MEM_IF_CAL_BANK : natural := 0; -- Bank to which calibration data is written
|
9903 |
|
|
-- Base column address to which calibration data is written.
|
9904 |
|
|
-- Memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
|
9905 |
|
|
-- is assumed to contain the proper data.
|
9906 |
|
|
MEM_IF_CAL_BASE_COL : natural := 0
|
9907 |
|
|
);
|
9908 |
|
|
port (
|
9909 |
|
|
-- CLK Reset
|
9910 |
|
|
clk : in std_logic;
|
9911 |
|
|
rst_n : in std_logic;
|
9912 |
|
|
|
9913 |
|
|
parameterisation_rec : in t_algm_paramaterisation;
|
9914 |
|
|
|
9915 |
|
|
-- Control interface :
|
9916 |
|
|
dgwb_ctrl : out t_ctrl_stat;
|
9917 |
|
|
ctrl_dgwb : in t_ctrl_command;
|
9918 |
|
|
|
9919 |
|
|
-- iRAM 'push' interface :
|
9920 |
|
|
dgwb_iram : out t_iram_push;
|
9921 |
|
|
iram_push_done : in std_logic;
|
9922 |
|
|
|
9923 |
|
|
-- Admin block req/gnt interface.
|
9924 |
|
|
dgwb_ac_access_req : out std_logic;
|
9925 |
|
|
dgwb_ac_access_gnt : in std_logic;
|
9926 |
|
|
|
9927 |
|
|
-- WDP interface
|
9928 |
|
|
dgwb_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
|
9929 |
|
|
dgwb_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
|
9930 |
|
|
dgwb_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
|
9931 |
|
|
dgwb_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
|
9932 |
|
|
dgwb_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
|
9933 |
|
|
dgwb_wdp_ovride : out std_logic;
|
9934 |
|
|
|
9935 |
|
|
-- addr/cmd output for write commands.
|
9936 |
|
|
dgwb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
|
9937 |
|
|
|
9938 |
|
|
dgwb_sc : out t_sc_int_ctrl;
|
9939 |
|
|
sc_dgwb_ack : in std_logic;
|
9940 |
|
|
|
9941 |
|
|
bypassed_rdata : in std_logic_vector(MEM_IF_DWIDTH-1 downto 0);
|
9942 |
|
|
|
9943 |
|
|
-- odt settings per chip select
|
9944 |
|
|
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1)
|
9945 |
|
|
|
9946 |
|
|
);
|
9947 |
|
|
|
9948 |
|
|
end entity;
|
9949 |
|
|
|
9950 |
|
|
--
|
9951 |
|
|
architecture rtl of altera_ddr_phy_alt_mem_phy_dgwb is
|
9952 |
|
|
|
9953 |
|
|
type t_dgwb_state is (
|
9954 |
|
|
s_idle,
|
9955 |
|
|
s_wait_admin,
|
9956 |
|
|
|
9957 |
|
|
s_write_btp, -- Writes bit-training pattern
|
9958 |
|
|
s_write_ones, -- Writes ones
|
9959 |
|
|
s_write_zeros, -- Writes zeros
|
9960 |
|
|
s_write_mtp, -- Write more training patterns (requires read to check allignment)
|
9961 |
|
|
s_write_01_pairs, -- Writes 01 pairs
|
9962 |
|
|
s_write_1100_step,-- Write step function (half zeros, half ones)
|
9963 |
|
|
s_write_0011_step,-- Write reversed step function (half ones, half zeros)
|
9964 |
|
|
s_write_wlat, -- Writes the write latency into a memory address.
|
9965 |
|
|
|
9966 |
|
|
s_release_admin
|
9967 |
|
|
);
|
9968 |
|
|
|
9969 |
|
|
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
|
9970 |
|
|
|
9971 |
|
|
-- a prefix for all report signals to identify phy and sequencer block
|
9972 |
|
|
--
|
9973 |
|
|
constant dgwb_report_prefix : string := "altera_ddr_phy_alt_mem_phy_seq (dgwb) : ";
|
9974 |
|
|
|
9975 |
|
|
function dqs_pattern return std_logic_vector is
|
9976 |
|
|
variable dqs : std_logic_vector( DWIDTH_RATIO - 1 downto 0);
|
9977 |
|
|
begin
|
9978 |
|
|
if DWIDTH_RATIO = 2 then
|
9979 |
|
|
dqs := "10";
|
9980 |
|
|
elsif DWIDTH_RATIO = 4 then
|
9981 |
|
|
dqs := "1100";
|
9982 |
|
|
else
|
9983 |
|
|
report dgwb_report_prefix & "unsupported DWIDTH_RATIO in function dqs_pattern." severity failure;
|
9984 |
|
|
end if;
|
9985 |
|
|
return dqs;
|
9986 |
|
|
end;
|
9987 |
|
|
|
9988 |
|
|
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
|
9989 |
|
|
|
9990 |
|
|
signal sig_dgwb_state : t_dgwb_state;
|
9991 |
|
|
signal sig_dgwb_last_state : t_dgwb_state;
|
9992 |
|
|
signal access_complete : std_logic;
|
9993 |
|
|
|
9994 |
|
|
signal generate_wdata : std_logic; -- for s_write_wlat only
|
9995 |
|
|
|
9996 |
|
|
-- current chip select being processed
|
9997 |
|
|
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS-1;
|
9998 |
|
|
|
9999 |
|
|
begin
|
10000 |
|
|
dgwb_ac <= sig_addr_cmd;
|
10001 |
|
|
|
10002 |
|
|
-- Set IRAM interface to defaults
|
10003 |
|
|
dgwb_iram <= defaults;
|
10004 |
|
|
|
10005 |
|
|
-- Set scanchain control to defaults
|
10006 |
|
|
dgwb_sc <= defaults;
|
10007 |
|
|
|
10008 |
|
|
|
10009 |
|
|
-- Master state machine. Generates state transitions.
|
10010 |
|
|
master_dgwb_state_block : if True generate
|
10011 |
|
|
signal sig_ctrl_dgwb : t_ctrl_command; -- registers ctrl_dgwb input.
|
10012 |
|
|
begin
|
10013 |
|
|
-- generate the current_cs signal to track which cs accessed by PHY at any instance
|
10014 |
|
|
current_cs_proc : process (clk, rst_n)
|
10015 |
|
|
begin
|
10016 |
|
|
if rst_n = '0' then
|
10017 |
|
|
current_cs <= 0;
|
10018 |
|
|
elsif rising_edge(clk) then
|
10019 |
|
|
if sig_ctrl_dgwb.command_req = '1' then
|
10020 |
|
|
current_cs <= sig_ctrl_dgwb.command_op.current_cs;
|
10021 |
|
|
end if;
|
10022 |
|
|
end if;
|
10023 |
|
|
end process;
|
10024 |
|
|
|
10025 |
|
|
|
10026 |
|
|
master_dgwb_state_proc : process(rst_n, clk)
|
10027 |
|
|
begin
|
10028 |
|
|
if rst_n = '0' then
|
10029 |
|
|
sig_dgwb_state <= s_idle;
|
10030 |
|
|
sig_dgwb_last_state <= s_idle;
|
10031 |
|
|
sig_ctrl_dgwb <= defaults;
|
10032 |
|
|
elsif rising_edge(clk) then
|
10033 |
|
|
case sig_dgwb_state is
|
10034 |
|
|
when s_idle =>
|
10035 |
|
|
if sig_ctrl_dgwb.command_req = '1' then
|
10036 |
|
|
if (curr_active_block(sig_ctrl_dgwb.command) = dgwb) then
|
10037 |
|
|
sig_dgwb_state <= s_wait_admin;
|
10038 |
|
|
end if;
|
10039 |
|
|
end if;
|
10040 |
|
|
|
10041 |
|
|
|
10042 |
|
|
when s_wait_admin =>
|
10043 |
|
|
case sig_ctrl_dgwb.command is
|
10044 |
|
|
when cmd_write_btp => sig_dgwb_state <= s_write_btp;
|
10045 |
|
|
when cmd_write_mtp => sig_dgwb_state <= s_write_mtp;
|
10046 |
|
|
when cmd_was => sig_dgwb_state <= s_write_wlat;
|
10047 |
|
|
|
10048 |
|
|
when others =>
|
10049 |
|
|
report dgwb_report_prefix & "unknown command" severity error;
|
10050 |
|
|
end case;
|
10051 |
|
|
|
10052 |
|
|
if dgwb_ac_access_gnt /= '1' then
|
10053 |
|
|
sig_dgwb_state <= s_wait_admin;
|
10054 |
|
|
end if;
|
10055 |
|
|
|
10056 |
|
|
|
10057 |
|
|
when s_write_btp =>
|
10058 |
|
|
sig_dgwb_state <= s_write_zeros;
|
10059 |
|
|
|
10060 |
|
|
|
10061 |
|
|
when s_write_zeros =>
|
10062 |
|
|
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
|
10063 |
|
|
sig_dgwb_state <= s_write_ones;
|
10064 |
|
|
end if;
|
10065 |
|
|
|
10066 |
|
|
|
10067 |
|
|
when s_write_ones =>
|
10068 |
|
|
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
|
10069 |
|
|
sig_dgwb_state <= s_release_admin;
|
10070 |
|
|
end if;
|
10071 |
|
|
|
10072 |
|
|
|
10073 |
|
|
when s_write_mtp =>
|
10074 |
|
|
sig_dgwb_state <= s_write_01_pairs;
|
10075 |
|
|
|
10076 |
|
|
|
10077 |
|
|
when s_write_01_pairs =>
|
10078 |
|
|
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
|
10079 |
|
|
sig_dgwb_state <= s_write_1100_step;
|
10080 |
|
|
end if;
|
10081 |
|
|
|
10082 |
|
|
when s_write_1100_step =>
|
10083 |
|
|
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
|
10084 |
|
|
sig_dgwb_state <= s_write_0011_step;
|
10085 |
|
|
end if;
|
10086 |
|
|
|
10087 |
|
|
|
10088 |
|
|
when s_write_0011_step =>
|
10089 |
|
|
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
|
10090 |
|
|
sig_dgwb_state <= s_release_admin;
|
10091 |
|
|
end if;
|
10092 |
|
|
|
10093 |
|
|
|
10094 |
|
|
when s_write_wlat =>
|
10095 |
|
|
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
|
10096 |
|
|
sig_dgwb_state <= s_release_admin;
|
10097 |
|
|
end if;
|
10098 |
|
|
|
10099 |
|
|
|
10100 |
|
|
when s_release_admin =>
|
10101 |
|
|
if dgwb_ac_access_gnt = '0' then
|
10102 |
|
|
sig_dgwb_state <= s_idle;
|
10103 |
|
|
end if;
|
10104 |
|
|
|
10105 |
|
|
|
10106 |
|
|
when others =>
|
10107 |
|
|
report dgwb_report_prefix & "undefined state in addr_cmd_proc" severity error;
|
10108 |
|
|
sig_dgwb_state <= s_idle;
|
10109 |
|
|
end case;
|
10110 |
|
|
|
10111 |
|
|
sig_dgwb_last_state <= sig_dgwb_state;
|
10112 |
|
|
sig_ctrl_dgwb <= ctrl_dgwb;
|
10113 |
|
|
end if;
|
10114 |
|
|
end process;
|
10115 |
|
|
end generate;
|
10116 |
|
|
|
10117 |
|
|
|
10118 |
|
|
-- Generates writes
|
10119 |
|
|
ac_write_block : if True generate
|
10120 |
|
|
|
10121 |
|
|
constant C_BURST_T : natural := C_CAL_BURST_LEN / DWIDTH_RATIO; -- Number of phy-clock cycles per burst
|
10122 |
|
|
constant C_MAX_WLAT : natural := 2**ADV_LAT_WIDTH-1; -- Maximum latency in clock cycles
|
10123 |
|
|
constant C_MAX_COUNT : natural := C_MAX_WLAT + C_BURST_T + 4*12 - 1; -- up to 12 consecutive writes at 4 cycle intervals
|
10124 |
|
|
|
10125 |
|
|
-- The following function sets the width over which
|
10126 |
|
|
-- write latency should be repeated on the dq bus
|
10127 |
|
|
-- the default value is MEM_IF_DQ_PER_DQS
|
10128 |
|
|
function set_wlat_dq_rep_width return natural is
|
10129 |
|
|
begin
|
10130 |
|
|
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
|
10131 |
|
|
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
|
10132 |
|
|
return i*MEM_IF_DQ_PER_DQS;
|
10133 |
|
|
end if;
|
10134 |
|
|
end loop;
|
10135 |
|
|
report dgwb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
|
10136 |
|
|
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
|
10137 |
|
|
return MEM_IF_DQ_PER_DQS;
|
10138 |
|
|
end function;
|
10139 |
|
|
|
10140 |
|
|
constant C_WLAT_DQ_REP_WIDTH : natural := set_wlat_dq_rep_width;
|
10141 |
|
|
|
10142 |
|
|
signal sig_count : natural range 0 to 2**8 - 1;
|
10143 |
|
|
begin
|
10144 |
|
|
ac_write_proc : process(rst_n, clk)
|
10145 |
|
|
begin
|
10146 |
|
|
if rst_n = '0' then
|
10147 |
|
|
dgwb_wdp_ovride <= '0';
|
10148 |
|
|
dgwb_dqs <= (others => '0');
|
10149 |
|
|
dgwb_dm <= (others => '1');
|
10150 |
|
|
dgwb_wdata <= (others => '0');
|
10151 |
|
|
dgwb_dqs_burst <= (others => '0');
|
10152 |
|
|
dgwb_wdata_valid <= (others => '0');
|
10153 |
|
|
generate_wdata <= '0'; -- for s_write_wlat only
|
10154 |
|
|
sig_count <= 0;
|
10155 |
|
|
sig_addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
|
10156 |
|
|
access_complete <= '0';
|
10157 |
|
|
|
10158 |
|
|
elsif rising_edge(clk) then
|
10159 |
|
|
dgwb_wdp_ovride <= '0';
|
10160 |
|
|
dgwb_dqs <= (others => '0');
|
10161 |
|
|
dgwb_dm <= (others => '1');
|
10162 |
|
|
dgwb_wdata <= (others => '0');
|
10163 |
|
|
dgwb_dqs_burst <= (others => '0');
|
10164 |
|
|
dgwb_wdata_valid <= (others => '0');
|
10165 |
|
|
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
|
10166 |
|
|
access_complete <= '0';
|
10167 |
|
|
generate_wdata <= '0'; -- for s_write_wlat only
|
10168 |
|
|
|
10169 |
|
|
case sig_dgwb_state is
|
10170 |
|
|
|
10171 |
|
|
when s_idle =>
|
10172 |
|
|
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
|
10173 |
|
|
|
10174 |
|
|
-- require ones in locations:
|
10175 |
|
|
-- 1. c_cal_ofs_ones (8 locations)
|
10176 |
|
|
-- 2. 2nd half of location c_cal_ofs_xF5 (4 locations)
|
10177 |
|
|
when s_write_ones =>
|
10178 |
|
|
dgwb_wdp_ovride <= '1';
|
10179 |
|
|
dgwb_dqs <= dqs_pattern;
|
10180 |
|
|
dgwb_dm <= (others => '0');
|
10181 |
|
|
dgwb_dqs_burst <= (others => '1');
|
10182 |
|
|
|
10183 |
|
|
-- Write ONES to DQ pins
|
10184 |
|
|
dgwb_wdata <= (others => '1');
|
10185 |
|
|
dgwb_wdata_valid <= (others => '1');
|
10186 |
|
|
|
10187 |
|
|
-- Issue write command
|
10188 |
|
|
if sig_dgwb_state /= sig_dgwb_last_state then
|
10189 |
|
|
sig_count <= 0;
|
10190 |
|
|
else
|
10191 |
|
|
|
10192 |
|
|
-- ensure safe intervals for DDRx memory writes (min 4 mem clk cycles between writes for BC4 DDR3)
|
10193 |
|
|
if sig_count = 0 then
|
10194 |
|
|
sig_addr_cmd <= write(c_seq_addr_cmd_config,
|
10195 |
|
|
sig_addr_cmd,
|
10196 |
|
|
MEM_IF_CAL_BANK, -- bank
|
10197 |
|
|
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones, -- address
|
10198 |
|
|
2**current_cs, -- rank
|
10199 |
|
|
4, -- burst length (fixed at BC4)
|
10200 |
|
|
false); -- auto-precharge
|
10201 |
|
|
elsif sig_count = 4 then
|
10202 |
|
|
sig_addr_cmd <= write(c_seq_addr_cmd_config,
|
10203 |
|
|
sig_addr_cmd,
|
10204 |
|
|
MEM_IF_CAL_BANK, -- bank
|
10205 |
|
|
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones + 4, -- address
|
10206 |
|
|
2**current_cs, -- rank
|
10207 |
|
|
4, -- burst length (fixed at BC4)
|
10208 |
|
|
false); -- auto-precharge
|
10209 |
|
|
elsif sig_count = 8 then
|
10210 |
|
|
sig_addr_cmd <= write(c_seq_addr_cmd_config,
|
10211 |
|
|
sig_addr_cmd,
|
10212 |
|
|
MEM_IF_CAL_BANK, -- bank
|
10213 |
|
|
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + 4, -- address
|
10214 |
|
|
2**current_cs, -- rank
|
10215 |
|
|
4, -- burst length (fixed at BC4)
|
10216 |
|
|
false); -- auto-precharge
|
10217 |
|
|
end if;
|
10218 |
|
|
sig_count <= sig_count + 1;
|
10219 |
|
|
end if;
|
10220 |
|
|
|
10221 |
|
|
if sig_count = C_MAX_COUNT - 1 then
|
10222 |
|
|
access_complete <= '1';
|
10223 |
|
|
end if;
|
10224 |
|
|
|
10225 |
|
|
-- require zeros in locations:
|
10226 |
|
|
-- 1. c_cal_ofs_zeros (8 locations)
|
10227 |
|
|
-- 2. 1st half of c_cal_ofs_x30_almt_0 (4 locations)
|
10228 |
|
|
-- 3. 1st half of c_cal_ofs_x30_almt_1 (4 locations)
|
10229 |
|
|
when s_write_zeros =>
|
10230 |
|
|
dgwb_wdp_ovride <= '1';
|
10231 |
|
|
dgwb_dqs <= dqs_pattern;
|
10232 |
|
|
dgwb_dm <= (others => '0');
|
10233 |
|
|
dgwb_dqs_burst <= (others => '1');
|
10234 |
|
|
|
10235 |
|
|
-- Write ZEROS to DQ pins
|
10236 |
|
|
dgwb_wdata <= (others => '0');
|
10237 |
|
|
dgwb_wdata_valid <= (others => '1');
|
10238 |
|
|
|
10239 |
|
|
-- Issue write command
|
10240 |
|
|
if sig_dgwb_state /= sig_dgwb_last_state then
|
10241 |
|
|
sig_count <= 0;
|
10242 |
|
|
else
|
10243 |
|
|
|
10244 |
|
|
if sig_count = 0 then
|
10245 |
|
|
sig_addr_cmd <= write(c_seq_addr_cmd_config,
|
10246 |
|
|
sig_addr_cmd,
|
10247 |
|
|
MEM_IF_CAL_BANK, -- bank
|
10248 |
|
|
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros, -- address
|
10249 |
|
|
2**current_cs, -- rank
|
10250 |
|
|
4, -- burst length (fixed at BC4)
|
10251 |
|
|
false); -- auto-precharge
|
10252 |
|
|
elsif sig_count = 4 then
|
10253 |
|
|
sig_addr_cmd <= write(c_seq_addr_cmd_config,
|
10254 |
|
|
sig_addr_cmd,
|
10255 |
|
|
MEM_IF_CAL_BANK, -- bank
|
10256 |
|
|
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros + 4, -- address
|
10257 |
|
|
2**current_cs, -- rank
|
10258 |
|
|
4, -- burst length (fixed at BC4)
|
10259 |
|
|
false); -- auto-precharge
|
10260 |
|
|
elsif sig_count = 8 then
|
10261 |
|
|
sig_addr_cmd <= write(c_seq_addr_cmd_config,
|
10262 |
|
|
sig_addr_cmd,
|
10263 |
|
|
MEM_IF_CAL_BANK, -- bank
|
10264 |
|
|
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0, -- address
|
10265 |
|
|
2**current_cs, -- rank
|
10266 |
|
|
4, -- burst length (fixed at BC4)
|
10267 |
|
|
false); -- auto-precharge
|
10268 |
|
|
elsif sig_count = 12 then
|
10269 |
|
|
sig_addr_cmd <= write(c_seq_addr_cmd_config,
|
10270 |
|
|
sig_addr_cmd,
|
10271 |
|
|
MEM_IF_CAL_BANK, -- bank
|
10272 |
|
|
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1, -- address
|
10273 |
|
|
2**current_cs, -- rank
|
10274 |
|
|
4, -- burst length (fixed at BC4)
|
10275 |
|
|
false); -- auto-precharge
|
10276 |
|
|
end if;
|
10277 |
|
|
sig_count <= sig_count + 1;
|
10278 |
|
|
end if;
|
10279 |
|
|
|
10280 |
|
|
|
10281 |
|
|
if sig_count = C_MAX_COUNT - 1 then
|
10282 |
|
|
access_complete <= '1';
|
10283 |
|
|
end if;
|
10284 |
|
|
|
10285 |
|
|
-- require 0101 pattern in locations:
|
10286 |
|
|
-- 1. 1st half of location c_cal_ofs_xF5 (4 locations)
|
10287 |
|
|
when s_write_01_pairs =>
|
10288 |
|
|
dgwb_wdp_ovride <= '1';
|
10289 |
|
|
dgwb_dqs <= dqs_pattern;
|
10290 |
|
|
dgwb_dm <= (others => '0');
|
10291 |
|
|
dgwb_dqs_burst <= (others => '1');
|
10292 |
|
|
|
10293 |
|
|
dgwb_wdata_valid <= (others => '1');
|
10294 |
|
|
|
10295 |
|
|
-- Issue write command
|
10296 |
|
|
if sig_dgwb_state /= sig_dgwb_last_state then
|
10297 |
|
|
sig_count <= 0;
|
10298 |
|
|
else
|
10299 |
|
|
if sig_count = 0 then
|
10300 |
|
|
sig_addr_cmd <= write(c_seq_addr_cmd_config,
|
10301 |
|
|
sig_addr_cmd,
|
10302 |
|
|
MEM_IF_CAL_BANK, -- bank
|
10303 |
|
|
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5, -- address
|
10304 |
|
|
2**current_cs, -- rank
|
10305 |
|
|
4, -- burst length
|
10306 |
|
|
false); -- auto-precharge
|
10307 |
|
|
end if;
|
10308 |
|
|
sig_count <= sig_count + 1;
|
10309 |
|
|
end if;
|
10310 |
|
|
|
10311 |
|
|
|
10312 |
|
|
if sig_count = C_MAX_COUNT - 1 then
|
10313 |
|
|
access_complete <= '1';
|
10314 |
|
|
end if;
|
10315 |
|
|
|
10316 |
|
|
-- Write 01 to pairs of memory addresses
|
10317 |
|
|
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
|
10318 |
|
|
if i mod 2 = 0 then
|
10319 |
|
|
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
|
10320 |
|
|
else
|
10321 |
|
|
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
|
10322 |
|
|
end if;
|
10323 |
|
|
end loop;
|
10324 |
|
|
|
10325 |
|
|
-- require pattern "0011" (or "1100") in locations:
|
10326 |
|
|
-- 1. 2nd half of c_cal_ofs_x30_almt_0 (4 locations)
|
10327 |
|
|
when s_write_0011_step =>
|
10328 |
|
|
dgwb_wdp_ovride <= '1';
|
10329 |
|
|
dgwb_dqs <= dqs_pattern;
|
10330 |
|
|
dgwb_dm <= (others => '0');
|
10331 |
|
|
dgwb_dqs_burst <= (others => '1');
|
10332 |
|
|
|
10333 |
|
|
dgwb_wdata_valid <= (others => '1');
|
10334 |
|
|
|
10335 |
|
|
-- Issue write command
|
10336 |
|
|
if sig_dgwb_state /= sig_dgwb_last_state then
|
10337 |
|
|
sig_addr_cmd <= write(c_seq_addr_cmd_config,
|
10338 |
|
|
sig_addr_cmd,
|
10339 |
|
|
MEM_IF_CAL_BANK, -- bank
|
10340 |
|
|
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + 4, -- address
|
10341 |
|
|
2**current_cs, -- rank
|
10342 |
|
|
4, -- burst length
|
10343 |
|
|
false); -- auto-precharge
|
10344 |
|
|
sig_count <= 0;
|
10345 |
|
|
else
|
10346 |
|
|
sig_count <= sig_count + 1;
|
10347 |
|
|
end if;
|
10348 |
|
|
|
10349 |
|
|
|
10350 |
|
|
if sig_count = C_MAX_COUNT - 1 then
|
10351 |
|
|
access_complete <= '1';
|
10352 |
|
|
end if;
|
10353 |
|
|
|
10354 |
|
|
-- Write 0011 step to column addresses. Note that
|
10355 |
|
|
-- it cannot be determined which at this point. The
|
10356 |
|
|
-- strategy is to write both alignments and see which
|
10357 |
|
|
-- one is correct later on.
|
10358 |
|
|
|
10359 |
|
|
-- this calculation has 2 parts:
|
10360 |
|
|
-- a) sig_count mod C_BURST_T is a timewise iterator of repetition of the pattern
|
10361 |
|
|
-- b) i represents the temporal iterator of the pattern
|
10362 |
|
|
-- it is required to sum a and b and switch the pattern between 0 and 1 every 2 locations in each dimension
|
10363 |
|
|
-- Note: the same formulae is used below for the 1100 pattern
|
10364 |
|
|
|
10365 |
|
|
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
|
10366 |
|
|
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
|
10367 |
|
|
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
|
10368 |
|
|
else
|
10369 |
|
|
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
|
10370 |
|
|
end if;
|
10371 |
|
|
end loop;
|
10372 |
|
|
|
10373 |
|
|
-- require pattern "1100" (or "0011") in locations:
|
10374 |
|
|
-- 1. 2nd half of c_cal_ofs_x30_almt_1 (4 locations)
|
10375 |
|
|
when s_write_1100_step =>
|
10376 |
|
|
dgwb_wdp_ovride <= '1';
|
10377 |
|
|
dgwb_dqs <= dqs_pattern;
|
10378 |
|
|
dgwb_dm <= (others => '0');
|
10379 |
|
|
dgwb_dqs_burst <= (others => '1');
|
10380 |
|
|
|
10381 |
|
|
dgwb_wdata_valid <= (others => '1');
|
10382 |
|
|
|
10383 |
|
|
-- Issue write command
|
10384 |
|
|
if sig_dgwb_state /= sig_dgwb_last_state then
|
10385 |
|
|
sig_addr_cmd <= write(c_seq_addr_cmd_config,
|
10386 |
|
|
sig_addr_cmd,
|
10387 |
|
|
MEM_IF_CAL_BANK, -- bank
|
10388 |
|
|
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + 4, -- address
|
10389 |
|
|
2**current_cs, -- rank
|
10390 |
|
|
4, -- burst length
|
10391 |
|
|
false); -- auto-precharge
|
10392 |
|
|
sig_count <= 0;
|
10393 |
|
|
else
|
10394 |
|
|
sig_count <= sig_count + 1;
|
10395 |
|
|
end if;
|
10396 |
|
|
|
10397 |
|
|
|
10398 |
|
|
if sig_count = C_MAX_COUNT - 1 then
|
10399 |
|
|
access_complete <= '1';
|
10400 |
|
|
end if;
|
10401 |
|
|
|
10402 |
|
|
-- Write 1100 step to column addresses. Note that
|
10403 |
|
|
-- it cannot be determined which at this point. The
|
10404 |
|
|
-- strategy is to write both alignments and see which
|
10405 |
|
|
-- one is correct later on.
|
10406 |
|
|
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
|
10407 |
|
|
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
|
10408 |
|
|
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
|
10409 |
|
|
else
|
10410 |
|
|
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
|
10411 |
|
|
end if;
|
10412 |
|
|
end loop;
|
10413 |
|
|
|
10414 |
|
|
|
10415 |
|
|
when s_write_wlat =>
|
10416 |
|
|
-- Effect:
|
10417 |
|
|
-- *Writes the memory latency to an array formed
|
10418 |
|
|
-- from memory addr=[2*C_CAL_BURST_LEN-(3*C_CAL_BURST_LEN-1)].
|
10419 |
|
|
-- The write latency is written to pairs of addresses
|
10420 |
|
|
-- across the given range.
|
10421 |
|
|
--
|
10422 |
|
|
-- Example
|
10423 |
|
|
-- C_CAL_BURST_LEN = 4
|
10424 |
|
|
-- addr 8 - 9 [WLAT] size = 2*MEM_IF_DWIDTH bits
|
10425 |
|
|
-- addr 10 - 11 [WLAT] size = 2*MEM_IF_DWIDTH bits
|
10426 |
|
|
--
|
10427 |
|
|
|
10428 |
|
|
dgwb_wdp_ovride <= '1';
|
10429 |
|
|
dgwb_dqs <= dqs_pattern;
|
10430 |
|
|
dgwb_dm <= (others => '0');
|
10431 |
|
|
dgwb_wdata <= (others => '0');
|
10432 |
|
|
dgwb_dqs_burst <= (others => '1');
|
10433 |
|
|
dgwb_wdata_valid <= (others => '1');
|
10434 |
|
|
|
10435 |
|
|
if sig_dgwb_state /= sig_dgwb_last_state then
|
10436 |
|
|
sig_addr_cmd <= write(c_seq_addr_cmd_config, -- A/C configuration
|
10437 |
|
|
sig_addr_cmd,
|
10438 |
|
|
MEM_IF_CAL_BANK, -- bank
|
10439 |
|
|
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- address
|
10440 |
|
|
2**current_cs, -- rank
|
10441 |
|
|
8, -- burst length (8 for DDR3 and 4 for DDR/DDR2)
|
10442 |
|
|
false); -- auto-precharge
|
10443 |
|
|
sig_count <= 0;
|
10444 |
|
|
else
|
10445 |
|
|
-- hold wdata_valid and wdata 2 clock cycles
|
10446 |
|
|
-- 1 - because ac signal registered at top level of sequencer
|
10447 |
|
|
-- 2 - because want time to dqs_burst edge which occurs 1 cycle earlier
|
10448 |
|
|
-- than wdata_valid in an AFI compliant controller
|
10449 |
|
|
generate_wdata <= '1';
|
10450 |
|
|
end if;
|
10451 |
|
|
|
10452 |
|
|
if generate_wdata = '1' then
|
10453 |
|
|
for i in 0 to dgwb_wdata'length/C_WLAT_DQ_REP_WIDTH - 1 loop
|
10454 |
|
|
dgwb_wdata((i+1)*C_WLAT_DQ_REP_WIDTH - 1 downto i*C_WLAT_DQ_REP_WIDTH) <= std_logic_vector(to_unsigned(sig_count, C_WLAT_DQ_REP_WIDTH));
|
10455 |
|
|
end loop;
|
10456 |
|
|
|
10457 |
|
|
-- delay by 1 clock cycle to account for 1 cycle discrepancy
|
10458 |
|
|
-- between dqs_burst and wdata_valid
|
10459 |
|
|
if sig_count = C_MAX_COUNT then
|
10460 |
|
|
access_complete <= '1';
|
10461 |
|
|
end if;
|
10462 |
|
|
|
10463 |
|
|
sig_count <= sig_count + 1;
|
10464 |
|
|
end if;
|
10465 |
|
|
|
10466 |
|
|
when others =>
|
10467 |
|
|
null;
|
10468 |
|
|
end case;
|
10469 |
|
|
|
10470 |
|
|
-- mask odt signal
|
10471 |
|
|
for i in 0 to (DWIDTH_RATIO/2)-1 loop
|
10472 |
|
|
sig_addr_cmd(i).odt <= odt_settings(current_cs).write;
|
10473 |
|
|
end loop;
|
10474 |
|
|
|
10475 |
|
|
end if;
|
10476 |
|
|
end process;
|
10477 |
|
|
end generate;
|
10478 |
|
|
|
10479 |
|
|
|
10480 |
|
|
-- Handles handshaking for access to address/command
|
10481 |
|
|
ac_handshake_proc : process(rst_n, clk)
|
10482 |
|
|
begin
|
10483 |
|
|
if rst_n = '0' then
|
10484 |
|
|
dgwb_ctrl <= defaults;
|
10485 |
|
|
dgwb_ac_access_req <= '0';
|
10486 |
|
|
elsif rising_edge(clk) then
|
10487 |
|
|
dgwb_ctrl <= defaults;
|
10488 |
|
|
dgwb_ac_access_req <= '0';
|
10489 |
|
|
|
10490 |
|
|
if sig_dgwb_state /= s_idle and sig_dgwb_state /= s_release_admin then
|
10491 |
|
|
dgwb_ac_access_req <= '1';
|
10492 |
|
|
elsif sig_dgwb_state = s_idle or sig_dgwb_state = s_release_admin then
|
10493 |
|
|
dgwb_ac_access_req <= '0';
|
10494 |
|
|
else
|
10495 |
|
|
report dgwb_report_prefix & "unexpected state in ac_handshake_proc so haven't requested access to address/command." severity warning;
|
10496 |
|
|
end if;
|
10497 |
|
|
|
10498 |
|
|
if sig_dgwb_state = s_wait_admin and sig_dgwb_last_state = s_idle then
|
10499 |
|
|
dgwb_ctrl.command_ack <= '1';
|
10500 |
|
|
end if;
|
10501 |
|
|
|
10502 |
|
|
if sig_dgwb_state = s_idle and sig_dgwb_last_state = s_release_admin then
|
10503 |
|
|
dgwb_ctrl.command_done <= '1';
|
10504 |
|
|
end if;
|
10505 |
|
|
end if;
|
10506 |
|
|
end process;
|
10507 |
|
|
|
10508 |
|
|
end architecture rtl;
|
10509 |
|
|
--
|
10510 |
|
|
|
10511 |
|
|
-- -----------------------------------------------------------------------------
|
10512 |
|
|
-- Abstract : ctrl block for the non-levelling AFI PHY sequencer
|
10513 |
|
|
-- This block is the central control unit for the sequencer. The method
|
10514 |
|
|
-- of control is to issue commands (prefixed cmd_) to each of the other
|
10515 |
|
|
-- sequencer blocks to execute. Each command corresponds to a stage of
|
10516 |
|
|
-- the AFI PHY calibaration stage, and in turn each state represents a
|
10517 |
|
|
-- command or a supplimentary flow control operation. In addition to
|
10518 |
|
|
-- controlling the sequencer this block also checks for time out
|
10519 |
|
|
-- conditions which occur when a different system block is faulty.
|
10520 |
|
|
-- -----------------------------------------------------------------------------
|
10521 |
|
|
|
10522 |
|
|
library ieee;
|
10523 |
|
|
use ieee.std_logic_1164.all;
|
10524 |
|
|
use ieee.numeric_std.all;
|
10525 |
|
|
|
10526 |
|
|
library work;
|
10527 |
|
|
|
10528 |
|
|
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
|
10529 |
|
|
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
|
10530 |
|
|
-- for the stages of DRAM memory calibration.
|
10531 |
|
|
--
|
10532 |
|
|
use work.altera_ddr_phy_alt_mem_phy_record_pkg.all;
|
10533 |
|
|
|
10534 |
|
|
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
|
10535 |
|
|
-- for iram writes during calibration
|
10536 |
|
|
--
|
10537 |
|
|
use work.altera_ddr_phy_alt_mem_phy_iram_addr_pkg.all;
|
10538 |
|
|
|
10539 |
|
|
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
|
10540 |
|
|
-- thoughout the sequencer and will not change (for constants which may change between sequencer
|
10541 |
|
|
-- instances generics are used)
|
10542 |
|
|
--
|
10543 |
|
|
use work.altera_ddr_phy_alt_mem_phy_constants_pkg.all;
|
10544 |
|
|
|
10545 |
|
|
--
|
10546 |
|
|
entity altera_ddr_phy_alt_mem_phy_ctrl is
|
10547 |
|
|
generic (
|
10548 |
|
|
MEM_IF_DLL_LOCK_COUNT : natural := 640;
|
10549 |
|
|
MEM_IF_MEMTYPE : string := "DDR2";
|
10550 |
|
|
DWIDTH_RATIO : natural := 2;
|
10551 |
|
|
IRAM_ADDRESSING : t_base_hdr_addresses := defaults;
|
10552 |
|
|
MEM_IF_CLK_PS : natural := 2500;
|
10553 |
|
|
TRACKING_INTERVAL_IN_MS : natural := 128;
|
10554 |
|
|
MEM_IF_NUM_RANKS : natural := 1;
|
10555 |
|
|
MEM_IF_DQS_WIDTH : natural := 9;
|
10556 |
|
|
|
10557 |
|
|
GENERATE_ADDITIONAL_DBG_RTL : natural := 1;
|
10558 |
|
|
SIM_TIME_REDUCTIONS : natural := 0; -- if 0 null, if 1 skip rrp, if 2 rrp for 1 dqs group and 1 cs
|
10559 |
|
|
|
10560 |
|
|
ACK_SEVERITY : severity_level := warning
|
10561 |
|
|
);
|
10562 |
|
|
port (
|
10563 |
|
|
-- clk / reset
|
10564 |
|
|
clk : in std_logic;
|
10565 |
|
|
rst_n : in std_logic;
|
10566 |
|
|
|
10567 |
|
|
-- calibration status and redo request
|
10568 |
|
|
ctl_init_success : out std_logic;
|
10569 |
|
|
ctl_init_fail : out std_logic;
|
10570 |
|
|
ctl_recalibrate_req : in std_logic; -- acts as a synchronous reset
|
10571 |
|
|
|
10572 |
|
|
-- status signals from iram
|
10573 |
|
|
iram_status : in t_iram_stat;
|
10574 |
|
|
iram_push_done : in std_logic;
|
10575 |
|
|
|
10576 |
|
|
-- standard control signal to all blocks
|
10577 |
|
|
ctrl_op_rec : out t_ctrl_command;
|
10578 |
|
|
|
10579 |
|
|
-- standardised response from all system blocks
|
10580 |
|
|
admin_ctrl : in t_ctrl_stat;
|
10581 |
|
|
dgrb_ctrl : in t_ctrl_stat;
|
10582 |
|
|
dgwb_ctrl : in t_ctrl_stat;
|
10583 |
|
|
|
10584 |
|
|
-- mmi to ctrl interface
|
10585 |
|
|
mmi_ctrl : in t_mmi_ctrl;
|
10586 |
|
|
ctrl_mmi : out t_ctrl_mmi;
|
10587 |
|
|
|
10588 |
|
|
-- byte lane select
|
10589 |
|
|
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
|
10590 |
|
|
|
10591 |
|
|
-- signals to control the ac_nt setting
|
10592 |
|
|
dgrb_ctrl_ac_nt_good : in std_logic;
|
10593 |
|
|
int_ac_nt : out std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0); -- width of 1 for DWIDTH_RATIO =2,4 and 2 for DWIDTH_RATIO = 8
|
10594 |
|
|
|
10595 |
|
|
-- the following signals are reserved for future use
|
10596 |
|
|
ctrl_iram_ihi_write : out std_logic;
|
10597 |
|
|
ctrl_iram_push : out t_ctrl_iram;
|
10598 |
|
|
sc_init_done : in std_logic;
|
10599 |
|
|
proc_ctrl : in t_ctrl_stat;
|
10600 |
|
|
setup_ctrl : in t_ctrl_stat
|
10601 |
|
|
|
10602 |
|
|
);
|
10603 |
|
|
end entity;
|
10604 |
|
|
|
10605 |
|
|
|
10606 |
|
|
--
|
10607 |
|
|
architecture struct of altera_ddr_phy_alt_mem_phy_ctrl is
|
10608 |
|
|
|
10609 |
|
|
-- a prefix for all report signals to identify phy and sequencer block
|
10610 |
|
|
--
|
10611 |
|
|
constant ctrl_report_prefix : string := "altera_ddr_phy_alt_mem_phy_seq (ctrl) : ";
|
10612 |
|
|
|
10613 |
|
|
-- decoder to find the relevant disable bit (from mmi registers) for a given state
|
10614 |
|
|
function find_dis_bit
|
10615 |
|
|
(
|
10616 |
|
|
state : t_master_sm_state;
|
10617 |
|
|
mmi_ctrl : t_mmi_ctrl
|
10618 |
|
|
) return std_logic is
|
10619 |
|
|
variable v_dis : std_logic;
|
10620 |
|
|
begin
|
10621 |
|
|
case state is
|
10622 |
|
|
when s_phy_initialise => v_dis := mmi_ctrl.hl_css.phy_initialise_dis;
|
10623 |
|
|
when s_init_dram => v_dis := mmi_ctrl.hl_css.init_dram_dis;
|
10624 |
|
|
when s_write_ihi => v_dis := mmi_ctrl.hl_css.write_ihi_dis;
|
10625 |
|
|
when s_cal => v_dis := mmi_ctrl.hl_css.cal_dis;
|
10626 |
|
|
when s_write_btp => v_dis := mmi_ctrl.hl_css.write_btp_dis;
|
10627 |
|
|
when s_write_mtp => v_dis := mmi_ctrl.hl_css.write_mtp_dis;
|
10628 |
|
|
when s_read_mtp => v_dis := mmi_ctrl.hl_css.read_mtp_dis;
|
10629 |
|
|
when s_rrp_reset => v_dis := mmi_ctrl.hl_css.rrp_reset_dis;
|
10630 |
|
|
when s_rrp_sweep => v_dis := mmi_ctrl.hl_css.rrp_sweep_dis;
|
10631 |
|
|
when s_rrp_seek => v_dis := mmi_ctrl.hl_css.rrp_seek_dis;
|
10632 |
|
|
when s_rdv => v_dis := mmi_ctrl.hl_css.rdv_dis;
|
10633 |
|
|
when s_poa => v_dis := mmi_ctrl.hl_css.poa_dis;
|
10634 |
|
|
when s_was => v_dis := mmi_ctrl.hl_css.was_dis;
|
10635 |
|
|
when s_adv_rd_lat => v_dis := mmi_ctrl.hl_css.adv_rd_lat_dis;
|
10636 |
|
|
when s_adv_wr_lat => v_dis := mmi_ctrl.hl_css.adv_wr_lat_dis;
|
10637 |
|
|
when s_prep_customer_mr_setup => v_dis := mmi_ctrl.hl_css.prep_customer_mr_setup_dis;
|
10638 |
|
|
when s_tracking_setup |
|
10639 |
|
|
s_tracking => v_dis := mmi_ctrl.hl_css.tracking_dis;
|
10640 |
|
|
when others => v_dis := '1'; -- default change stage
|
10641 |
|
|
end case;
|
10642 |
|
|
return v_dis;
|
10643 |
|
|
end function;
|
10644 |
|
|
|
10645 |
|
|
-- decoder to find the relevant command for a given state
|
10646 |
|
|
function find_cmd
|
10647 |
|
|
(
|
10648 |
|
|
state : t_master_sm_state
|
10649 |
|
|
) return t_ctrl_cmd_id is
|
10650 |
|
|
begin
|
10651 |
|
|
case state is
|
10652 |
|
|
when s_phy_initialise => return cmd_phy_initialise;
|
10653 |
|
|
when s_init_dram => return cmd_init_dram;
|
10654 |
|
|
when s_write_ihi => return cmd_write_ihi;
|
10655 |
|
|
when s_cal => return cmd_idle;
|
10656 |
|
|
when s_write_btp => return cmd_write_btp;
|
10657 |
|
|
when s_write_mtp => return cmd_write_mtp;
|
10658 |
|
|
when s_read_mtp => return cmd_read_mtp;
|
10659 |
|
|
when s_rrp_reset => return cmd_rrp_reset;
|
10660 |
|
|
when s_rrp_sweep => return cmd_rrp_sweep;
|
10661 |
|
|
when s_rrp_seek => return cmd_rrp_seek;
|
10662 |
|
|
when s_rdv => return cmd_rdv;
|
10663 |
|
|
when s_poa => return cmd_poa;
|
10664 |
|
|
when s_was => return cmd_was;
|
10665 |
|
|
when s_adv_rd_lat => return cmd_prep_adv_rd_lat;
|
10666 |
|
|
when s_adv_wr_lat => return cmd_prep_adv_wr_lat;
|
10667 |
|
|
when s_prep_customer_mr_setup => return cmd_prep_customer_mr_setup;
|
10668 |
|
|
when s_tracking_setup |
|
10669 |
|
|
s_tracking => return cmd_tr_due;
|
10670 |
|
|
when others => return cmd_idle;
|
10671 |
|
|
end case;
|
10672 |
|
|
end function;
|
10673 |
|
|
|
10674 |
|
|
function mcs_rw_state -- returns true for multiple cs read/write states
|
10675 |
|
|
(
|
10676 |
|
|
state : t_master_sm_state
|
10677 |
|
|
) return boolean is
|
10678 |
|
|
begin
|
10679 |
|
|
case state is
|
10680 |
|
|
|
10681 |
|
|
when s_write_btp | s_write_mtp | s_rrp_sweep =>
|
10682 |
|
|
return true;
|
10683 |
|
|
|
10684 |
|
|
when s_reset | s_phy_initialise | s_init_dram | s_write_ihi | s_cal |
|
10685 |
|
|
s_read_mtp | s_rrp_reset | s_rrp_seek | s_rdv | s_poa |
|
10686 |
|
|
s_was | s_adv_rd_lat | s_adv_wr_lat | s_prep_customer_mr_setup |
|
10687 |
|
|
s_tracking_setup | s_tracking | s_operational | s_non_operational =>
|
10688 |
|
|
|
10689 |
|
|
return false;
|
10690 |
|
|
|
10691 |
|
|
when others =>
|
10692 |
|
|
--
|
10693 |
|
|
return false;
|
10694 |
|
|
|
10695 |
|
|
end case;
|
10696 |
|
|
|
10697 |
|
|
end function;
|
10698 |
|
|
|
10699 |
|
|
-- timing parameters
|
10700 |
|
|
constant c_done_timeout_count : natural := 32768;
|
10701 |
|
|
constant c_ack_timeout_count : natural := 1000;
|
10702 |
|
|
constant c_ticks_per_ms : natural := 1000000000/(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
|
10703 |
|
|
constant c_ticks_per_10us : natural := 10000000 /(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
|
10704 |
|
|
|
10705 |
|
|
-- local copy of calibration fail/success signals
|
10706 |
|
|
signal int_ctl_init_fail : std_logic;
|
10707 |
|
|
signal int_ctl_init_success : std_logic;
|
10708 |
|
|
|
10709 |
|
|
-- state machine (master for sequencer)
|
10710 |
|
|
signal state : t_master_sm_state;
|
10711 |
|
|
signal last_state : t_master_sm_state;
|
10712 |
|
|
|
10713 |
|
|
-- flow control signals for state machine
|
10714 |
|
|
signal dis_state : std_logic; -- disable state
|
10715 |
|
|
signal hold_state : std_logic; -- hold in state for 1 clock cycle
|
10716 |
|
|
|
10717 |
|
|
signal master_ctrl_op_rec : t_ctrl_command; -- master command record to all sequencer blocks
|
10718 |
|
|
signal master_ctrl_iram_push : t_ctrl_iram; -- record indicating control details for pushes
|
10719 |
|
|
|
10720 |
|
|
signal dll_lock_counter : natural range MEM_IF_DLL_LOCK_COUNT - 1 downto 0; -- to wait for dll to lock
|
10721 |
|
|
signal iram_init_complete : std_logic;
|
10722 |
|
|
|
10723 |
|
|
-- timeout signals to check if a block has 'hung'
|
10724 |
|
|
signal timeout_counter : natural range c_done_timeout_count - 1 downto 0;
|
10725 |
|
|
signal timeout_counter_stop : std_logic;
|
10726 |
|
|
signal timeout_counter_enable : std_logic;
|
10727 |
|
|
signal timeout_counter_clear : std_logic;
|
10728 |
|
|
|
10729 |
|
|
signal cmd_req_asserted : std_logic; -- a command has been issued
|
10730 |
|
|
|
10731 |
|
|
signal flag_ack_timeout : std_logic; -- req -> ack timed out
|
10732 |
|
|
signal flag_done_timeout : std_logic; -- reg -> done timed out
|
10733 |
|
|
|
10734 |
|
|
signal waiting_for_ack : std_logic; -- command issued
|
10735 |
|
|
signal cmd_ack_seen : std_logic; -- command completed
|
10736 |
|
|
|
10737 |
|
|
signal curr_ctrl : t_ctrl_stat; -- response for current active block
|
10738 |
|
|
signal curr_cmd : t_ctrl_cmd_id;
|
10739 |
|
|
|
10740 |
|
|
-- store state information based on issued command
|
10741 |
|
|
signal int_ctrl_prev_stage : t_ctrl_cmd_id;
|
10742 |
|
|
signal int_ctrl_current_stage : t_ctrl_cmd_id;
|
10743 |
|
|
|
10744 |
|
|
-- multiple chip select counter
|
10745 |
|
|
signal cs_counter : natural range 0 to MEM_IF_NUM_RANKS - 1;
|
10746 |
|
|
signal reissue_cmd_req : std_logic; -- reissue command request for multiple cs
|
10747 |
|
|
|
10748 |
|
|
signal cal_cs_enabled : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
|
10749 |
|
|
|
10750 |
|
|
-- signals to check the ac_nt setting
|
10751 |
|
|
signal ac_nt_almts_checked : natural range 0 to DWIDTH_RATIO/2-1;
|
10752 |
|
|
signal ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
|
10753 |
|
|
|
10754 |
|
|
-- track the mtp alignment setting
|
10755 |
|
|
signal mtp_almts_checked : natural range 0 to 2;
|
10756 |
|
|
signal mtp_correct_almt : natural range 0 to 1;
|
10757 |
|
|
signal mtp_no_valid_almt : std_logic;
|
10758 |
|
|
signal mtp_both_valid_almt : std_logic;
|
10759 |
|
|
signal mtp_err : std_logic;
|
10760 |
|
|
|
10761 |
|
|
-- tracking timing
|
10762 |
|
|
signal milisecond_tick_gen_count : natural range 0 to c_ticks_per_ms -1 := c_ticks_per_ms -1;
|
10763 |
|
|
signal tracking_ms_counter : natural range 0 to 255;
|
10764 |
|
|
signal tracking_update_due : std_logic;
|
10765 |
|
|
|
10766 |
|
|
begin -- architecture struct
|
10767 |
|
|
|
10768 |
|
|
-------------------------------------------------------------------------------
|
10769 |
|
|
-- check if chip selects are enabled
|
10770 |
|
|
-- this only effects reactive stages (i,e, those requiring memory reads)
|
10771 |
|
|
-------------------------------------------------------------------------------
|
10772 |
|
|
|
10773 |
|
|
process(ctl_cal_byte_lanes)
|
10774 |
|
|
variable v_cs_enabled : std_logic;
|
10775 |
|
|
begin
|
10776 |
|
|
|
10777 |
|
|
for i in 0 to MEM_IF_NUM_RANKS - 1 loop
|
10778 |
|
|
|
10779 |
|
|
-- check if any bytes enabled
|
10780 |
|
|
v_cs_enabled := '0';
|
10781 |
|
|
for j in 0 to MEM_IF_DQS_WIDTH - 1 loop
|
10782 |
|
|
v_cs_enabled := v_cs_enabled or ctl_cal_byte_lanes(i*MEM_IF_DQS_WIDTH + j);
|
10783 |
|
|
end loop;
|
10784 |
|
|
|
10785 |
|
|
-- if any byte enabled set cs as enabled else not
|
10786 |
|
|
cal_cs_enabled(i) <= v_cs_enabled;
|
10787 |
|
|
|
10788 |
|
|
-- sanity checking:
|
10789 |
|
|
if i = 0 and v_cs_enabled = '0' then
|
10790 |
|
|
report ctrl_report_prefix & " disabling of chip select 0 is unsupported by the sequencer," & LF &
|
10791 |
|
|
"-> if this is your intention then please remap CS pins such that CS 0 is not disabled" severity failure;
|
10792 |
|
|
end if;
|
10793 |
|
|
|
10794 |
|
|
end loop;
|
10795 |
|
|
|
10796 |
|
|
end process;
|
10797 |
|
|
|
10798 |
|
|
-- -----------------------------------------------------------------------------
|
10799 |
|
|
-- dll lock counter
|
10800 |
|
|
-- -----------------------------------------------------------------------------
|
10801 |
|
|
|
10802 |
|
|
process(clk, rst_n)
|
10803 |
|
|
begin
|
10804 |
|
|
if rst_n = '0' then
|
10805 |
|
|
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
|
10806 |
|
|
|
10807 |
|
|
elsif rising_edge(clk) then
|
10808 |
|
|
if ctl_recalibrate_req = '1' then
|
10809 |
|
|
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
|
10810 |
|
|
|
10811 |
|
|
elsif dll_lock_counter /= 0 then
|
10812 |
|
|
dll_lock_counter <= dll_lock_counter - 1;
|
10813 |
|
|
end if;
|
10814 |
|
|
end if;
|
10815 |
|
|
end process;
|
10816 |
|
|
|
10817 |
|
|
-- -----------------------------------------------------------------------------
|
10818 |
|
|
-- timeout counter : this counter is used to determine if an ack, or done has
|
10819 |
|
|
-- not been received within the expected number of clock cycles of a req being
|
10820 |
|
|
-- asserted.
|
10821 |
|
|
-- -----------------------------------------------------------------------------
|
10822 |
|
|
|
10823 |
|
|
process(clk, rst_n)
|
10824 |
|
|
begin
|
10825 |
|
|
if rst_n = '0' then
|
10826 |
|
|
timeout_counter <= c_done_timeout_count - 1;
|
10827 |
|
|
|
10828 |
|
|
elsif rising_edge(clk) then
|
10829 |
|
|
if timeout_counter_clear = '1' then
|
10830 |
|
|
timeout_counter <= c_done_timeout_count - 1;
|
10831 |
|
|
|
10832 |
|
|
elsif timeout_counter_enable = '1' and state /= s_init_dram then
|
10833 |
|
|
if timeout_counter /= 0 then
|
10834 |
|
|
timeout_counter <= timeout_counter - 1;
|
10835 |
|
|
end if;
|
10836 |
|
|
end if;
|
10837 |
|
|
end if;
|
10838 |
|
|
|
10839 |
|
|
end process;
|
10840 |
|
|
|
10841 |
|
|
-- -----------------------------------------------------------------------------
|
10842 |
|
|
-- register current ctrl signal based on current command
|
10843 |
|
|
-- -----------------------------------------------------------------------------
|
10844 |
|
|
|
10845 |
|
|
process(clk, rst_n)
|
10846 |
|
|
begin
|
10847 |
|
|
if rst_n = '0' then
|
10848 |
|
|
|
10849 |
|
|
curr_ctrl <= defaults;
|
10850 |
|
|
curr_cmd <= cmd_idle;
|
10851 |
|
|
|
10852 |
|
|
elsif rising_edge(clk) then
|
10853 |
|
|
|
10854 |
|
|
case curr_active_block(curr_cmd) is
|
10855 |
|
|
when admin => curr_ctrl <= admin_ctrl;
|
10856 |
|
|
when dgrb => curr_ctrl <= dgrb_ctrl;
|
10857 |
|
|
when dgwb => curr_ctrl <= dgwb_ctrl;
|
10858 |
|
|
when others => curr_ctrl <= defaults;
|
10859 |
|
|
end case;
|
10860 |
|
|
|
10861 |
|
|
curr_cmd <= master_ctrl_op_rec.command;
|
10862 |
|
|
|
10863 |
|
|
end if;
|
10864 |
|
|
|
10865 |
|
|
end process;
|
10866 |
|
|
|
10867 |
|
|
-- -----------------------------------------------------------------------------
|
10868 |
|
|
-- generation of cmd_ack_seen
|
10869 |
|
|
-- -----------------------------------------------------------------------------
|
10870 |
|
|
|
10871 |
|
|
process (curr_ctrl)
|
10872 |
|
|
begin
|
10873 |
|
|
cmd_ack_seen <= curr_ctrl.command_ack;
|
10874 |
|
|
end process;
|
10875 |
|
|
|
10876 |
|
|
-------------------------------------------------------------------------------
|
10877 |
|
|
-- generation of waiting_for_ack flag (to determine whether ack has timed out)
|
10878 |
|
|
-------------------------------------------------------------------------------
|
10879 |
|
|
|
10880 |
|
|
process(clk, rst_n)
|
10881 |
|
|
begin
|
10882 |
|
|
if rst_n = '0' then
|
10883 |
|
|
waiting_for_ack <= '0';
|
10884 |
|
|
|
10885 |
|
|
elsif rising_edge(clk) then
|
10886 |
|
|
if cmd_req_asserted = '1' then
|
10887 |
|
|
waiting_for_ack <= '1';
|
10888 |
|
|
|
10889 |
|
|
elsif cmd_ack_seen = '1' then
|
10890 |
|
|
waiting_for_ack <= '0';
|
10891 |
|
|
end if;
|
10892 |
|
|
end if;
|
10893 |
|
|
|
10894 |
|
|
end process;
|
10895 |
|
|
|
10896 |
|
|
-- -----------------------------------------------------------------------------
|
10897 |
|
|
-- generation of timeout flags
|
10898 |
|
|
-- -----------------------------------------------------------------------------
|
10899 |
|
|
|
10900 |
|
|
process(clk, rst_n)
|
10901 |
|
|
begin
|
10902 |
|
|
if rst_n = '0' then
|
10903 |
|
|
flag_ack_timeout <= '0';
|
10904 |
|
|
flag_done_timeout <= '0';
|
10905 |
|
|
|
10906 |
|
|
elsif rising_edge(clk) then
|
10907 |
|
|
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
|
10908 |
|
|
flag_ack_timeout <= '0';
|
10909 |
|
|
|
10910 |
|
|
elsif timeout_counter = 0 and waiting_for_ack = '1' then
|
10911 |
|
|
flag_ack_timeout <= '1';
|
10912 |
|
|
end if;
|
10913 |
|
|
|
10914 |
|
|
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
|
10915 |
|
|
flag_done_timeout <= '0';
|
10916 |
|
|
|
10917 |
|
|
elsif timeout_counter = 0 and
|
10918 |
|
|
state /= s_rrp_sweep and -- rrp can take enough cycles to overflow counter so don't timeout
|
10919 |
|
|
state /= s_init_dram and -- init_dram takes about 200 us, so don't timeout
|
10920 |
|
|
timeout_counter_clear /= '1' then -- check if currently clearing the timeout (i.e. command_done asserted for s_init_dram or s_rrp_sweep)
|
10921 |
|
|
|
10922 |
|
|
flag_done_timeout <= '1';
|
10923 |
|
|
end if;
|
10924 |
|
|
end if;
|
10925 |
|
|
|
10926 |
|
|
end process;
|
10927 |
|
|
|
10928 |
|
|
-- generation of timeout_counter_stop
|
10929 |
|
|
timeout_counter_stop <= curr_ctrl.command_done;
|
10930 |
|
|
|
10931 |
|
|
-- -----------------------------------------------------------------------------
|
10932 |
|
|
-- generation of timeout_counter_enable and timeout_counter_clear
|
10933 |
|
|
-- -----------------------------------------------------------------------------
|
10934 |
|
|
|
10935 |
|
|
process(clk, rst_n)
|
10936 |
|
|
begin
|
10937 |
|
|
if rst_n = '0' then
|
10938 |
|
|
|
10939 |
|
|
timeout_counter_enable <= '0';
|
10940 |
|
|
timeout_counter_clear <= '0';
|
10941 |
|
|
|
10942 |
|
|
elsif rising_edge(clk) then
|
10943 |
|
|
if cmd_req_asserted = '1' then
|
10944 |
|
|
timeout_counter_enable <= '1';
|
10945 |
|
|
timeout_counter_clear <= '0';
|
10946 |
|
|
|
10947 |
|
|
elsif timeout_counter_stop = '1'
|
10948 |
|
|
or state = s_operational
|
10949 |
|
|
or state = s_non_operational
|
10950 |
|
|
or state = s_reset then
|
10951 |
|
|
timeout_counter_enable <= '0';
|
10952 |
|
|
timeout_counter_clear <= '1';
|
10953 |
|
|
end if;
|
10954 |
|
|
end if;
|
10955 |
|
|
|
10956 |
|
|
end process;
|
10957 |
|
|
|
10958 |
|
|
-------------------------------------------------------------------------------
|
10959 |
|
|
-- assignment to ctrl_mmi record
|
10960 |
|
|
-------------------------------------------------------------------------------
|
10961 |
|
|
|
10962 |
|
|
process (clk, rst_n)
|
10963 |
|
|
variable v_ctrl_mmi : t_ctrl_mmi;
|
10964 |
|
|
begin
|
10965 |
|
|
if rst_n = '0' then
|
10966 |
|
|
|
10967 |
|
|
v_ctrl_mmi := defaults;
|
10968 |
|
|
ctrl_mmi <= defaults;
|
10969 |
|
|
int_ctrl_prev_stage <= cmd_idle;
|
10970 |
|
|
int_ctrl_current_stage <= cmd_idle;
|
10971 |
|
|
|
10972 |
|
|
elsif rising_edge(clk) then
|
10973 |
|
|
|
10974 |
|
|
ctrl_mmi <= v_ctrl_mmi;
|
10975 |
|
|
|
10976 |
|
|
v_ctrl_mmi.ctrl_calibration_success := '0';
|
10977 |
|
|
v_ctrl_mmi.ctrl_calibration_fail := '0';
|
10978 |
|
|
|
10979 |
|
|
if (curr_ctrl.command_ack = '1') then
|
10980 |
|
|
case state is
|
10981 |
|
|
when s_init_dram => v_ctrl_mmi.ctrl_cal_stage_ack_seen.init_dram := '1';
|
10982 |
|
|
when s_write_btp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_btp := '1';
|
10983 |
|
|
when s_write_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_mtp := '1';
|
10984 |
|
|
when s_read_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.read_mtp := '1';
|
10985 |
|
|
when s_rrp_reset => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_reset := '1';
|
10986 |
|
|
when s_rrp_sweep => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_sweep := '1';
|
10987 |
|
|
when s_rrp_seek => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_seek := '1';
|
10988 |
|
|
when s_rdv => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rdv := '1';
|
10989 |
|
|
when s_poa => v_ctrl_mmi.ctrl_cal_stage_ack_seen.poa := '1';
|
10990 |
|
|
when s_was => v_ctrl_mmi.ctrl_cal_stage_ack_seen.was := '1';
|
10991 |
|
|
when s_adv_rd_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_rd_lat := '1';
|
10992 |
|
|
when s_adv_wr_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_wr_lat := '1';
|
10993 |
|
|
when s_prep_customer_mr_setup => v_ctrl_mmi.ctrl_cal_stage_ack_seen.prep_customer_mr_setup := '1';
|
10994 |
|
|
when s_tracking_setup |
|
10995 |
|
|
s_tracking => v_ctrl_mmi.ctrl_cal_stage_ack_seen.tracking_setup := '1';
|
10996 |
|
|
when others => null;
|
10997 |
|
|
end case;
|
10998 |
|
|
end if;
|
10999 |
|
|
|
11000 |
|
|
-- special 'ack' (actually finished) triggers for phy_initialise, writing iram header info and s_cal
|
11001 |
|
|
if state = s_phy_initialise then
|
11002 |
|
|
if iram_status.init_done = '1' and dll_lock_counter = 0 then
|
11003 |
|
|
v_ctrl_mmi.ctrl_cal_stage_ack_seen.phy_initialise := '1';
|
11004 |
|
|
end if;
|
11005 |
|
|
end if;
|
11006 |
|
|
|
11007 |
|
|
if state = s_write_ihi then
|
11008 |
|
|
if iram_push_done = '1' then
|
11009 |
|
|
v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_ihi := '1';
|
11010 |
|
|
end if;
|
11011 |
|
|
end if;
|
11012 |
|
|
|
11013 |
|
|
if state = s_cal and find_dis_bit(state, mmi_ctrl) = '0' then -- if cal state and calibration not disabled acknowledge
|
11014 |
|
|
v_ctrl_mmi.ctrl_cal_stage_ack_seen.cal := '1';
|
11015 |
|
|
end if;
|
11016 |
|
|
|
11017 |
|
|
|
11018 |
|
|
if state = s_operational then
|
11019 |
|
|
v_ctrl_mmi.ctrl_calibration_success := '1';
|
11020 |
|
|
end if;
|
11021 |
|
|
|
11022 |
|
|
if state = s_non_operational then
|
11023 |
|
|
v_ctrl_mmi.ctrl_calibration_fail := '1';
|
11024 |
|
|
end if;
|
11025 |
|
|
|
11026 |
|
|
if state /= s_non_operational then
|
11027 |
|
|
v_ctrl_mmi.ctrl_current_active_block := master_ctrl_iram_push.active_block;
|
11028 |
|
|
v_ctrl_mmi.ctrl_current_stage := master_ctrl_op_rec.command;
|
11029 |
|
|
else
|
11030 |
|
|
v_ctrl_mmi.ctrl_current_active_block := v_ctrl_mmi.ctrl_current_active_block;
|
11031 |
|
|
v_ctrl_mmi.ctrl_current_stage := v_ctrl_mmi.ctrl_current_stage;
|
11032 |
|
|
end if;
|
11033 |
|
|
|
11034 |
|
|
int_ctrl_prev_stage <= int_ctrl_current_stage;
|
11035 |
|
|
int_ctrl_current_stage <= v_ctrl_mmi.ctrl_current_stage;
|
11036 |
|
|
|
11037 |
|
|
if int_ctrl_prev_stage /= int_ctrl_current_stage then
|
11038 |
|
|
v_ctrl_mmi.ctrl_current_stage_done := '0';
|
11039 |
|
|
|
11040 |
|
|
else
|
11041 |
|
|
if curr_ctrl.command_done = '1' then
|
11042 |
|
|
v_ctrl_mmi.ctrl_current_stage_done := '1';
|
11043 |
|
|
end if;
|
11044 |
|
|
end if;
|
11045 |
|
|
|
11046 |
|
|
v_ctrl_mmi.master_state_r := last_state;
|
11047 |
|
|
|
11048 |
|
|
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
|
11049 |
|
|
v_ctrl_mmi := defaults;
|
11050 |
|
|
ctrl_mmi <= defaults;
|
11051 |
|
|
end if;
|
11052 |
|
|
|
11053 |
|
|
-- assert error codes here
|
11054 |
|
|
if curr_ctrl.command_err = '1' then
|
11055 |
|
|
v_ctrl_mmi.ctrl_err_code := curr_ctrl.command_result;
|
11056 |
|
|
elsif flag_ack_timeout = '1' then
|
11057 |
|
|
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_ack_timeout, v_ctrl_mmi.ctrl_err_code'length));
|
11058 |
|
|
elsif flag_done_timeout = '1' then
|
11059 |
|
|
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_done_timeout, v_ctrl_mmi.ctrl_err_code'length));
|
11060 |
|
|
elsif mtp_err = '1' then
|
11061 |
|
|
if mtp_no_valid_almt = '1' then
|
11062 |
|
|
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_NO_VALID_ALMT, v_ctrl_mmi.ctrl_err_code'length));
|
11063 |
|
|
elsif mtp_both_valid_almt = '1' then
|
11064 |
|
|
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_BOTH_ALMT_PASS, v_ctrl_mmi.ctrl_err_code'length));
|
11065 |
|
|
end if;
|
11066 |
|
|
end if;
|
11067 |
|
|
|
11068 |
|
|
end if;
|
11069 |
|
|
|
11070 |
|
|
end process;
|
11071 |
|
|
|
11072 |
|
|
-- check if iram finished init
|
11073 |
|
|
process(iram_status)
|
11074 |
|
|
begin
|
11075 |
|
|
if GENERATE_ADDITIONAL_DBG_RTL = 0 then
|
11076 |
|
|
iram_init_complete <= '1';
|
11077 |
|
|
else
|
11078 |
|
|
iram_init_complete <= iram_status.init_done;
|
11079 |
|
|
end if;
|
11080 |
|
|
end process;
|
11081 |
|
|
|
11082 |
|
|
-- -----------------------------------------------------------------------------
|
11083 |
|
|
-- master state machine
|
11084 |
|
|
-- (this controls the operation of the entire sequencer)
|
11085 |
|
|
-- the states are summarised as follows:
|
11086 |
|
|
-- s_reset
|
11087 |
|
|
-- s_phy_initialise - wait for dll lock and init done flag from iram
|
11088 |
|
|
-- s_init_dram - dram initialisation (in admin block)
|
11089 |
|
|
-- s_write_ihi - write header information in iRAM
|
11090 |
|
|
-- s_cal - check if calibration to be executed
|
11091 |
|
|
-- s_write_btp - write burst training pattern
|
11092 |
|
|
-- s_write_mtp - write more training pattern
|
11093 |
|
|
-- s_rrp_reset - read resync phase setup - reset initial conditions
|
11094 |
|
|
-- s_rrp_sweep - read resync phase setup - sweep phases per chip select
|
11095 |
|
|
-- s_read_mtp - read training patterns to find correct alignment for 1100 burst
|
11096 |
|
|
-- (this is a special case of s_rrp_seek with no resych phase setting)
|
11097 |
|
|
-- s_rrp_seek - read resync phase setup - seek correct alignment
|
11098 |
|
|
-- s_rdv - read data valid setup
|
11099 |
|
|
-- s_poa - calibrate the postamble
|
11100 |
|
|
-- s_was - write datapath setup (ac to write data timing)
|
11101 |
|
|
-- s_adv_rd_lat - advertise read latency
|
11102 |
|
|
-- s_adv_wr_lat - advertise write latency
|
11103 |
|
|
-- s_tracking_setup - perform tracking (1st pass to setup mimic window)
|
11104 |
|
|
-- s_prep_customer_mr_setup - apply user mode register settings (in admin block)
|
11105 |
|
|
-- s_tracking - perform tracking (subsequent passes in user mode)
|
11106 |
|
|
-- s_operational - calibration successful and in user mode
|
11107 |
|
|
-- s_non_operational - calibration unsuccessful and in user mode
|
11108 |
|
|
-- -----------------------------------------------------------------------------
|
11109 |
|
|
|
11110 |
|
|
process(clk, rst_n)
|
11111 |
|
|
variable v_seen_ack : boolean;
|
11112 |
|
|
variable v_dis : std_logic; -- disable bit
|
11113 |
|
|
begin
|
11114 |
|
|
if rst_n = '0' then
|
11115 |
|
|
|
11116 |
|
|
state <= s_reset;
|
11117 |
|
|
last_state <= s_reset;
|
11118 |
|
|
int_ctl_init_success <= '0';
|
11119 |
|
|
int_ctl_init_fail <= '0';
|
11120 |
|
|
v_seen_ack := false;
|
11121 |
|
|
hold_state <= '0';
|
11122 |
|
|
cs_counter <= 0;
|
11123 |
|
|
mtp_almts_checked <= 0;
|
11124 |
|
|
ac_nt <= (others => '1');
|
11125 |
|
|
ac_nt_almts_checked <= 0;
|
11126 |
|
|
reissue_cmd_req <= '0';
|
11127 |
|
|
|
11128 |
|
|
dis_state <= '0';
|
11129 |
|
|
|
11130 |
|
|
elsif rising_edge(clk) then
|
11131 |
|
|
last_state <= state;
|
11132 |
|
|
|
11133 |
|
|
-- check if state_tx required
|
11134 |
|
|
if curr_ctrl.command_ack = '1' then
|
11135 |
|
|
v_seen_ack := true;
|
11136 |
|
|
end if;
|
11137 |
|
|
|
11138 |
|
|
-- find disable bit for current state (do once to avoid exit mid-state)
|
11139 |
|
|
if state /= last_state then
|
11140 |
|
|
dis_state <= find_dis_bit(state, mmi_ctrl);
|
11141 |
|
|
end if;
|
11142 |
|
|
|
11143 |
|
|
-- Set special conditions:
|
11144 |
|
|
|
11145 |
|
|
if state = s_reset or
|
11146 |
|
|
state = s_operational or
|
11147 |
|
|
state = s_non_operational then
|
11148 |
|
|
dis_state <= '1';
|
11149 |
|
|
end if;
|
11150 |
|
|
|
11151 |
|
|
-- override to ensure execution of next state logic
|
11152 |
|
|
if (state = s_cal) then
|
11153 |
|
|
dis_state <= '1';
|
11154 |
|
|
end if;
|
11155 |
|
|
|
11156 |
|
|
-- if header writing in iram check finished
|
11157 |
|
|
if (state = s_write_ihi) then
|
11158 |
|
|
if iram_push_done = '1' or mmi_ctrl.hl_css.write_ihi_dis = '1' then
|
11159 |
|
|
dis_state <= '1';
|
11160 |
|
|
else
|
11161 |
|
|
dis_state <= '0';
|
11162 |
|
|
end if;
|
11163 |
|
|
end if;
|
11164 |
|
|
|
11165 |
|
|
-- Special condition for initialisation
|
11166 |
|
|
if (state = s_phy_initialise) then
|
11167 |
|
|
if ((dll_lock_counter = 0) and (iram_init_complete = '1')) or
|
11168 |
|
|
(mmi_ctrl.hl_css.phy_initialise_dis = '1') then
|
11169 |
|
|
dis_state <= '1';
|
11170 |
|
|
else
|
11171 |
|
|
dis_state <= '0';
|
11172 |
|
|
end if;
|
11173 |
|
|
end if;
|
11174 |
|
|
|
11175 |
|
|
if dis_state = '1' then
|
11176 |
|
|
v_seen_ack := false;
|
11177 |
|
|
elsif curr_ctrl.command_done = '1' then
|
11178 |
|
|
if v_seen_ack = false then
|
11179 |
|
|
report ctrl_report_prefix & "have not seen ack but have seen command done from " & t_ctrl_active_block'image(curr_active_block(master_ctrl_op_rec.command)) & "_block in state " & t_master_sm_state'image(state) severity warning;
|
11180 |
|
|
end if;
|
11181 |
|
|
v_seen_ack := false;
|
11182 |
|
|
end if;
|
11183 |
|
|
|
11184 |
|
|
-- default do not reissue command request
|
11185 |
|
|
reissue_cmd_req <= '0';
|
11186 |
|
|
|
11187 |
|
|
if (hold_state = '1') then
|
11188 |
|
|
hold_state <= '0';
|
11189 |
|
|
else
|
11190 |
|
|
if ((dis_state = '1') or
|
11191 |
|
|
(curr_ctrl.command_done = '1') or
|
11192 |
|
|
((cal_cs_enabled(cs_counter) = '0') and (mcs_rw_state(state) = True))) then -- current chip select is disabled and read/write
|
11193 |
|
|
|
11194 |
|
|
hold_state <= '1';
|
11195 |
|
|
|
11196 |
|
|
-- Only reset the below if making state change
|
11197 |
|
|
int_ctl_init_success <= '0';
|
11198 |
|
|
int_ctl_init_fail <= '0';
|
11199 |
|
|
|
11200 |
|
|
case state is
|
11201 |
|
|
when s_reset => state <= s_phy_initialise;
|
11202 |
|
|
cs_counter <= 0;
|
11203 |
|
|
|
11204 |
|
|
when s_phy_initialise => state <= s_init_dram;
|
11205 |
|
|
cs_counter <= 0; -- s_init_dram is always performed to all CS
|
11206 |
|
|
|
11207 |
|
|
when s_init_dram => if cs_counter = MEM_IF_NUM_RANKS - 1 then
|
11208 |
|
|
|
11209 |
|
|
-- if no debug interface don't write iram header
|
11210 |
|
|
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
|
11211 |
|
|
state <= s_write_ihi;
|
11212 |
|
|
else
|
11213 |
|
|
state <= s_cal;
|
11214 |
|
|
end if;
|
11215 |
|
|
|
11216 |
|
|
else
|
11217 |
|
|
|
11218 |
|
|
cs_counter <= cs_counter + 1;
|
11219 |
|
|
reissue_cmd_req <= '1';
|
11220 |
|
|
|
11221 |
|
|
end if;
|
11222 |
|
|
|
11223 |
|
|
when s_write_ihi => state <= s_cal;
|
11224 |
|
|
|
11225 |
|
|
when s_cal => if mmi_ctrl.hl_css.cal_dis = '0' then
|
11226 |
|
|
state <= s_write_btp;
|
11227 |
|
|
else
|
11228 |
|
|
state <= s_tracking_setup;
|
11229 |
|
|
end if;
|
11230 |
|
|
|
11231 |
|
|
-- always enter s_cal before calibration so reset some variables here
|
11232 |
|
|
cs_counter <= 0;
|
11233 |
|
|
mtp_almts_checked <= 0;
|
11234 |
|
|
ac_nt <= (others => '1');
|
11235 |
|
|
ac_nt_almts_checked <= 0;
|
11236 |
|
|
|
11237 |
|
|
when s_write_btp => if cs_counter = MEM_IF_NUM_RANKS-1 or
|
11238 |
|
|
SIM_TIME_REDUCTIONS = 2 then
|
11239 |
|
|
|
11240 |
|
|
state <= s_write_mtp;
|
11241 |
|
|
cs_counter <= 0;
|
11242 |
|
|
|
11243 |
|
|
else
|
11244 |
|
|
cs_counter <= cs_counter + 1;
|
11245 |
|
|
|
11246 |
|
|
-- only reissue command if current chip select enabled
|
11247 |
|
|
if cal_cs_enabled(cs_counter + 1) = '1' then
|
11248 |
|
|
reissue_cmd_req <= '1';
|
11249 |
|
|
end if;
|
11250 |
|
|
|
11251 |
|
|
end if;
|
11252 |
|
|
|
11253 |
|
|
when s_write_mtp => if cs_counter = MEM_IF_NUM_RANKS - 1 or
|
11254 |
|
|
SIM_TIME_REDUCTIONS = 2 then
|
11255 |
|
|
|
11256 |
|
|
if SIM_TIME_REDUCTIONS = 1 then
|
11257 |
|
|
state <= s_rdv;
|
11258 |
|
|
else
|
11259 |
|
|
state <= s_rrp_reset;
|
11260 |
|
|
end if;
|
11261 |
|
|
|
11262 |
|
|
cs_counter <= 0;
|
11263 |
|
|
|
11264 |
|
|
else
|
11265 |
|
|
cs_counter <= cs_counter + 1;
|
11266 |
|
|
|
11267 |
|
|
-- only reissue command if current chip select enabled
|
11268 |
|
|
if cal_cs_enabled(cs_counter + 1) = '1' then
|
11269 |
|
|
reissue_cmd_req <= '1';
|
11270 |
|
|
end if;
|
11271 |
|
|
|
11272 |
|
|
end if;
|
11273 |
|
|
|
11274 |
|
|
when s_rrp_reset => state <= s_rrp_sweep;
|
11275 |
|
|
cs_counter <= 0;
|
11276 |
|
|
|
11277 |
|
|
when s_rrp_sweep => if cs_counter = MEM_IF_NUM_RANKS - 1 or
|
11278 |
|
|
mtp_almts_checked /= 2 or
|
11279 |
|
|
SIM_TIME_REDUCTIONS = 2 then
|
11280 |
|
|
|
11281 |
|
|
if mtp_almts_checked /= 2 then
|
11282 |
|
|
state <= s_read_mtp;
|
11283 |
|
|
else
|
11284 |
|
|
state <= s_rrp_seek;
|
11285 |
|
|
end if;
|
11286 |
|
|
|
11287 |
|
|
else
|
11288 |
|
|
cs_counter <= cs_counter + 1;
|
11289 |
|
|
|
11290 |
|
|
-- only reissue command if current chip select enabled
|
11291 |
|
|
if cal_cs_enabled(cs_counter + 1) = '1' then
|
11292 |
|
|
reissue_cmd_req <= '1';
|
11293 |
|
|
end if;
|
11294 |
|
|
|
11295 |
|
|
end if;
|
11296 |
|
|
|
11297 |
|
|
when s_read_mtp => if mtp_almts_checked /= 2 then
|
11298 |
|
|
mtp_almts_checked <= mtp_almts_checked + 1;
|
11299 |
|
|
end if;
|
11300 |
|
|
state <= s_rrp_reset;
|
11301 |
|
|
|
11302 |
|
|
when s_rrp_seek => state <= s_rdv;
|
11303 |
|
|
cs_counter <= 0;
|
11304 |
|
|
|
11305 |
|
|
when s_rdv => state <= s_was;
|
11306 |
|
|
when s_was => state <= s_adv_rd_lat;
|
11307 |
|
|
when s_adv_rd_lat => state <= s_adv_wr_lat;
|
11308 |
|
|
|
11309 |
|
|
when s_adv_wr_lat => if dgrb_ctrl_ac_nt_good = '1' then
|
11310 |
|
|
state <= s_poa;
|
11311 |
|
|
else
|
11312 |
|
|
if ac_nt_almts_checked = (DWIDTH_RATIO/2 - 1) then
|
11313 |
|
|
state <= s_non_operational;
|
11314 |
|
|
else
|
11315 |
|
|
-- switch alignment and restart calibration
|
11316 |
|
|
ac_nt <= std_logic_vector(unsigned(ac_nt) + 1);
|
11317 |
|
|
ac_nt_almts_checked <= ac_nt_almts_checked + 1;
|
11318 |
|
|
|
11319 |
|
|
if SIM_TIME_REDUCTIONS = 1 then
|
11320 |
|
|
state <= s_rdv;
|
11321 |
|
|
else
|
11322 |
|
|
state <= s_rrp_reset;
|
11323 |
|
|
end if;
|
11324 |
|
|
|
11325 |
|
|
mtp_almts_checked <= 0;
|
11326 |
|
|
end if;
|
11327 |
|
|
end if;
|
11328 |
|
|
|
11329 |
|
|
when s_poa => state <= s_tracking_setup;
|
11330 |
|
|
|
11331 |
|
|
when s_tracking_setup => state <= s_prep_customer_mr_setup;
|
11332 |
|
|
cs_counter <= 0;
|
11333 |
|
|
|
11334 |
|
|
when s_prep_customer_mr_setup => if cs_counter = MEM_IF_NUM_RANKS - 1 then -- s_prep_customer_mr_setup is always performed over all cs
|
11335 |
|
|
state <= s_operational;
|
11336 |
|
|
else
|
11337 |
|
|
cs_counter <= cs_counter + 1;
|
11338 |
|
|
reissue_cmd_req <= '1';
|
11339 |
|
|
end if;
|
11340 |
|
|
|
11341 |
|
|
when s_tracking => state <= s_operational;
|
11342 |
|
|
int_ctl_init_success <= int_ctl_init_success;
|
11343 |
|
|
int_ctl_init_fail <= int_ctl_init_fail;
|
11344 |
|
|
|
11345 |
|
|
when s_operational => int_ctl_init_success <= '1';
|
11346 |
|
|
int_ctl_init_fail <= '0';
|
11347 |
|
|
hold_state <= '0';
|
11348 |
|
|
if tracking_update_due = '1' and mmi_ctrl.hl_css.tracking_dis = '0' then
|
11349 |
|
|
state <= s_tracking;
|
11350 |
|
|
hold_state <= '1';
|
11351 |
|
|
end if;
|
11352 |
|
|
|
11353 |
|
|
when s_non_operational => int_ctl_init_success <= '0';
|
11354 |
|
|
int_ctl_init_fail <= '1';
|
11355 |
|
|
hold_state <= '0';
|
11356 |
|
|
if last_state /= s_non_operational then -- print a warning on entering this state
|
11357 |
|
|
report ctrl_report_prefix & "memory calibration has failed (output from ctrl block)" severity WARNING;
|
11358 |
|
|
end if;
|
11359 |
|
|
|
11360 |
|
|
when others => state <= t_master_sm_state'succ(state);
|
11361 |
|
|
end case;
|
11362 |
|
|
end if;
|
11363 |
|
|
end if;
|
11364 |
|
|
|
11365 |
|
|
if (flag_done_timeout = '1' -- no done signal from current active block
|
11366 |
|
|
or flag_ack_timeout = '1' -- or no ack signal from current active block
|
11367 |
|
|
or curr_ctrl.command_err = '1' -- or an error from current active block
|
11368 |
|
|
or mtp_err = '1') -- or an error due to mtp alignment
|
11369 |
|
|
and GENERATE_ADDITIONAL_DBG_RTL = 1 then -- only use when GENERATE_ADDITIONAL_DBG_RTL set to minimise logic in non-debug mode
|
11370 |
|
|
state <= s_non_operational;
|
11371 |
|
|
end if;
|
11372 |
|
|
|
11373 |
|
|
if mmi_ctrl.calibration_start = '1' then -- restart calibration process
|
11374 |
|
|
state <= s_cal;
|
11375 |
|
|
end if;
|
11376 |
|
|
|
11377 |
|
|
if ctl_recalibrate_req = '1' then -- restart all incl. initialisation
|
11378 |
|
|
state <= s_reset;
|
11379 |
|
|
end if;
|
11380 |
|
|
|
11381 |
|
|
end if;
|
11382 |
|
|
|
11383 |
|
|
end process;
|
11384 |
|
|
|
11385 |
|
|
-- generate output calibration fail/success signals
|
11386 |
|
|
process(clk, rst_n)
|
11387 |
|
|
begin
|
11388 |
|
|
if rst_n = '0' then
|
11389 |
|
|
|
11390 |
|
|
ctl_init_fail <= '0';
|
11391 |
|
|
ctl_init_success <= '0';
|
11392 |
|
|
|
11393 |
|
|
elsif rising_edge(clk) then
|
11394 |
|
|
|
11395 |
|
|
ctl_init_fail <= int_ctl_init_fail;
|
11396 |
|
|
ctl_init_success <= int_ctl_init_success;
|
11397 |
|
|
|
11398 |
|
|
end if;
|
11399 |
|
|
end process;
|
11400 |
|
|
|
11401 |
|
|
-- assign ac_nt to the output int_ac_nt
|
11402 |
|
|
process(ac_nt)
|
11403 |
|
|
begin
|
11404 |
|
|
int_ac_nt <= ac_nt;
|
11405 |
|
|
end process;
|
11406 |
|
|
|
11407 |
|
|
-- ------------------------------------------------------------------------------
|
11408 |
|
|
-- find correct mtp_almt from returned data
|
11409 |
|
|
-- ------------------------------------------------------------------------------
|
11410 |
|
|
|
11411 |
|
|
mtp_almt: block
|
11412 |
|
|
|
11413 |
|
|
signal dvw_size_a0 : natural range 0 to 255; -- maximum size of command result
|
11414 |
|
|
signal dvw_size_a1 : natural range 0 to 255;
|
11415 |
|
|
|
11416 |
|
|
begin
|
11417 |
|
|
|
11418 |
|
|
process (clk, rst_n)
|
11419 |
|
|
|
11420 |
|
|
variable v_dvw_a0_small : boolean;
|
11421 |
|
|
variable v_dvw_a1_small : boolean;
|
11422 |
|
|
|
11423 |
|
|
begin
|
11424 |
|
|
if rst_n = '0' then
|
11425 |
|
|
|
11426 |
|
|
mtp_correct_almt <= 0;
|
11427 |
|
|
dvw_size_a0 <= 0;
|
11428 |
|
|
dvw_size_a1 <= 0;
|
11429 |
|
|
mtp_no_valid_almt <= '0';
|
11430 |
|
|
mtp_both_valid_almt <= '0';
|
11431 |
|
|
mtp_err <= '0';
|
11432 |
|
|
|
11433 |
|
|
elsif rising_edge(clk) then
|
11434 |
|
|
|
11435 |
|
|
-- update the dvw sizes
|
11436 |
|
|
if state = s_read_mtp then
|
11437 |
|
|
if curr_ctrl.command_done = '1' then
|
11438 |
|
|
if mtp_almts_checked = 0 then
|
11439 |
|
|
dvw_size_a0 <= to_integer(unsigned(curr_ctrl.command_result));
|
11440 |
|
|
else
|
11441 |
|
|
dvw_size_a1 <= to_integer(unsigned(curr_ctrl.command_result));
|
11442 |
|
|
end if;
|
11443 |
|
|
end if;
|
11444 |
|
|
end if;
|
11445 |
|
|
|
11446 |
|
|
-- check dvw size and set mtp almt
|
11447 |
|
|
if dvw_size_a0 < dvw_size_a1 then
|
11448 |
|
|
mtp_correct_almt <= 1;
|
11449 |
|
|
else
|
11450 |
|
|
mtp_correct_almt <= 0;
|
11451 |
|
|
end if;
|
11452 |
|
|
|
11453 |
|
|
-- error conditions
|
11454 |
|
|
if mtp_almts_checked = 2 and GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if finished alignment checking (and GENERATE_ADDITIONAL_DBG_RTL set)
|
11455 |
|
|
|
11456 |
|
|
-- perform size checks once per dvw
|
11457 |
|
|
if dvw_size_a0 < 3 then
|
11458 |
|
|
v_dvw_a0_small := true;
|
11459 |
|
|
else
|
11460 |
|
|
v_dvw_a0_small := false;
|
11461 |
|
|
end if;
|
11462 |
|
|
|
11463 |
|
|
if dvw_size_a1 < 3 then
|
11464 |
|
|
v_dvw_a1_small := true;
|
11465 |
|
|
else
|
11466 |
|
|
v_dvw_a1_small := false;
|
11467 |
|
|
end if;
|
11468 |
|
|
|
11469 |
|
|
if v_dvw_a0_small = true and v_dvw_a1_small = true then
|
11470 |
|
|
mtp_no_valid_almt <= '1';
|
11471 |
|
|
mtp_err <= '1';
|
11472 |
|
|
end if;
|
11473 |
|
|
|
11474 |
|
|
if v_dvw_a0_small = false and v_dvw_a1_small = false then
|
11475 |
|
|
mtp_both_valid_almt <= '1';
|
11476 |
|
|
mtp_err <= '1';
|
11477 |
|
|
end if;
|
11478 |
|
|
|
11479 |
|
|
else
|
11480 |
|
|
|
11481 |
|
|
mtp_no_valid_almt <= '0';
|
11482 |
|
|
mtp_both_valid_almt <= '0';
|
11483 |
|
|
mtp_err <= '0';
|
11484 |
|
|
|
11485 |
|
|
end if;
|
11486 |
|
|
|
11487 |
|
|
end if;
|
11488 |
|
|
|
11489 |
|
|
end process;
|
11490 |
|
|
|
11491 |
|
|
end block;
|
11492 |
|
|
|
11493 |
|
|
-- ------------------------------------------------------------------------------
|
11494 |
|
|
-- process to generate command outputs, based on state, last_state and mmi_ctrl.
|
11495 |
|
|
-- asynchronously
|
11496 |
|
|
-- ------------------------------------------------------------------------------
|
11497 |
|
|
|
11498 |
|
|
process (state, last_state, mmi_ctrl, reissue_cmd_req, cs_counter, mtp_almts_checked, mtp_correct_almt)
|
11499 |
|
|
begin
|
11500 |
|
|
master_ctrl_op_rec <= defaults;
|
11501 |
|
|
master_ctrl_iram_push <= defaults;
|
11502 |
|
|
|
11503 |
|
|
case state is
|
11504 |
|
|
|
11505 |
|
|
-- special condition states
|
11506 |
|
|
when s_reset | s_phy_initialise | s_cal =>
|
11507 |
|
|
null;
|
11508 |
|
|
|
11509 |
|
|
when s_write_ihi =>
|
11510 |
|
|
if mmi_ctrl.hl_css.write_ihi_dis = '0' then
|
11511 |
|
|
master_ctrl_op_rec.command <= find_cmd(state);
|
11512 |
|
|
if state /= last_state then
|
11513 |
|
|
master_ctrl_op_rec.command_req <= '1';
|
11514 |
|
|
end if;
|
11515 |
|
|
end if;
|
11516 |
|
|
|
11517 |
|
|
when s_operational | s_non_operational =>
|
11518 |
|
|
master_ctrl_op_rec.command <= find_cmd(state);
|
11519 |
|
|
|
11520 |
|
|
when others => -- default condition for most states
|
11521 |
|
|
if find_dis_bit(state, mmi_ctrl) = '0' then
|
11522 |
|
|
master_ctrl_op_rec.command <= find_cmd(state);
|
11523 |
|
|
if state /= last_state or reissue_cmd_req = '1' then
|
11524 |
|
|
master_ctrl_op_rec.command_req <= '1';
|
11525 |
|
|
end if;
|
11526 |
|
|
else
|
11527 |
|
|
if state = last_state then -- safe state exit if state disabled mid-calibration
|
11528 |
|
|
master_ctrl_op_rec.command <= find_cmd(state);
|
11529 |
|
|
end if;
|
11530 |
|
|
end if;
|
11531 |
|
|
|
11532 |
|
|
end case;
|
11533 |
|
|
|
11534 |
|
|
-- for multiple chip select commands assign operand to cs_counter
|
11535 |
|
|
master_ctrl_op_rec.command_op <= defaults;
|
11536 |
|
|
master_ctrl_op_rec.command_op.current_cs <= cs_counter;
|
11537 |
|
|
if state = s_rrp_sweep or state = s_read_mtp or state = s_poa then
|
11538 |
|
|
if mtp_almts_checked /= 2 or SIM_TIME_REDUCTIONS = 2 then
|
11539 |
|
|
master_ctrl_op_rec.command_op.single_bit <= '1';
|
11540 |
|
|
end if;
|
11541 |
|
|
if mtp_almts_checked /= 2 then
|
11542 |
|
|
master_ctrl_op_rec.command_op.mtp_almt <= mtp_almts_checked;
|
11543 |
|
|
else
|
11544 |
|
|
master_ctrl_op_rec.command_op.mtp_almt <= mtp_correct_almt;
|
11545 |
|
|
end if;
|
11546 |
|
|
end if;
|
11547 |
|
|
|
11548 |
|
|
-- set write mode and packing mode for iram
|
11549 |
|
|
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
|
11550 |
|
|
|
11551 |
|
|
case state is
|
11552 |
|
|
when s_rrp_sweep =>
|
11553 |
|
|
master_ctrl_iram_push.write_mode <= overwrite_ram;
|
11554 |
|
|
master_ctrl_iram_push.packing_mode <= dq_bitwise;
|
11555 |
|
|
|
11556 |
|
|
when s_rrp_seek |
|
11557 |
|
|
s_read_mtp =>
|
11558 |
|
|
|
11559 |
|
|
master_ctrl_iram_push.write_mode <= overwrite_ram;
|
11560 |
|
|
master_ctrl_iram_push.packing_mode <= dq_wordwise;
|
11561 |
|
|
|
11562 |
|
|
when others =>
|
11563 |
|
|
|
11564 |
|
|
null;
|
11565 |
|
|
|
11566 |
|
|
end case;
|
11567 |
|
|
end if;
|
11568 |
|
|
|
11569 |
|
|
-- set current active block
|
11570 |
|
|
master_ctrl_iram_push.active_block <= curr_active_block(find_cmd(state));
|
11571 |
|
|
|
11572 |
|
|
end process;
|
11573 |
|
|
|
11574 |
|
|
-- some concurc_read_burst_trent assignments to outputs
|
11575 |
|
|
process (master_ctrl_iram_push, master_ctrl_op_rec)
|
11576 |
|
|
begin
|
11577 |
|
|
ctrl_iram_ihi_write <= '0';
|
11578 |
|
|
ctrl_iram_push <= master_ctrl_iram_push;
|
11579 |
|
|
ctrl_op_rec <= master_ctrl_op_rec;
|
11580 |
|
|
cmd_req_asserted <= master_ctrl_op_rec.command_req;
|
11581 |
|
|
end process;
|
11582 |
|
|
|
11583 |
|
|
-- -----------------------------------------------------------------------------
|
11584 |
|
|
-- tracking interval counter
|
11585 |
|
|
-- -----------------------------------------------------------------------------
|
11586 |
|
|
process(clk, rst_n)
|
11587 |
|
|
begin
|
11588 |
|
|
if rst_n = '0' then
|
11589 |
|
|
milisecond_tick_gen_count <= c_ticks_per_ms -1;
|
11590 |
|
|
tracking_ms_counter <= 0;
|
11591 |
|
|
tracking_update_due <= '0';
|
11592 |
|
|
|
11593 |
|
|
elsif rising_edge(clk) then
|
11594 |
|
|
if state = s_operational and last_state/= s_operational then
|
11595 |
|
|
|
11596 |
|
|
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
|
11597 |
|
|
milisecond_tick_gen_count <= c_ticks_per_10us -1;
|
11598 |
|
|
else
|
11599 |
|
|
milisecond_tick_gen_count <= c_ticks_per_ms -1;
|
11600 |
|
|
end if;
|
11601 |
|
|
|
11602 |
|
|
tracking_ms_counter <= mmi_ctrl.tracking_period_ms;
|
11603 |
|
|
|
11604 |
|
|
elsif state = s_operational then
|
11605 |
|
|
if milisecond_tick_gen_count = 0 and tracking_update_due /= '1' then
|
11606 |
|
|
|
11607 |
|
|
if tracking_ms_counter = 0 then
|
11608 |
|
|
tracking_update_due <= '1';
|
11609 |
|
|
else
|
11610 |
|
|
tracking_ms_counter <= tracking_ms_counter -1;
|
11611 |
|
|
end if;
|
11612 |
|
|
|
11613 |
|
|
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
|
11614 |
|
|
milisecond_tick_gen_count <= c_ticks_per_10us -1;
|
11615 |
|
|
else
|
11616 |
|
|
milisecond_tick_gen_count <= c_ticks_per_ms -1;
|
11617 |
|
|
end if;
|
11618 |
|
|
|
11619 |
|
|
elsif milisecond_tick_gen_count /= 0 then
|
11620 |
|
|
milisecond_tick_gen_count <= milisecond_tick_gen_count -1;
|
11621 |
|
|
end if;
|
11622 |
|
|
|
11623 |
|
|
else
|
11624 |
|
|
|
11625 |
|
|
tracking_update_due <= '0';
|
11626 |
|
|
end if;
|
11627 |
|
|
end if;
|
11628 |
|
|
|
11629 |
|
|
end process;
|
11630 |
|
|
|
11631 |
|
|
end architecture struct;
|
11632 |
|
|
--
|
11633 |
|
|
|
11634 |
|
|
-- -----------------------------------------------------------------------------
|
11635 |
|
|
-- Abstract : top level for the non-levelling AFI PHY sequencer
|
11636 |
|
|
-- The top level instances the sub-blocks of the AFI PHY
|
11637 |
|
|
-- sequencer. In addition a number of multiplexing and high-
|
11638 |
|
|
-- level control operations are performed. This includes the
|
11639 |
|
|
-- multiplexing and generation of control signals for: the
|
11640 |
|
|
-- address and command DRAM interface and pll, oct and datapath
|
11641 |
|
|
-- latency control signals.
|
11642 |
|
|
-- -----------------------------------------------------------------------------
|
11643 |
|
|
|
11644 |
|
|
library ieee;
|
11645 |
|
|
use ieee.std_logic_1164.all;
|
11646 |
|
|
use ieee.numeric_std.all;
|
11647 |
|
|
|
11648 |
|
|
|
11649 |
|
|
library work;
|
11650 |
|
|
|
11651 |
|
|
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
|
11652 |
|
|
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
|
11653 |
|
|
-- for the stages of DRAM memory calibration.
|
11654 |
|
|
--
|
11655 |
|
|
use work.altera_ddr_phy_alt_mem_phy_record_pkg.all;
|
11656 |
|
|
|
11657 |
|
|
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
|
11658 |
|
|
-- registers for the mmi status registers and functions/procedures applied to the registers
|
11659 |
|
|
--
|
11660 |
|
|
use work.altera_ddr_phy_alt_mem_phy_regs_pkg.all;
|
11661 |
|
|
|
11662 |
|
|
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
|
11663 |
|
|
-- thoughout the sequencer and will not change (for constants which may change between sequencer
|
11664 |
|
|
-- instances generics are used)
|
11665 |
|
|
--
|
11666 |
|
|
use work.altera_ddr_phy_alt_mem_phy_constants_pkg.all;
|
11667 |
|
|
|
11668 |
|
|
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
|
11669 |
|
|
-- for iram writes during calibration
|
11670 |
|
|
--
|
11671 |
|
|
use work.altera_ddr_phy_alt_mem_phy_iram_addr_pkg.all;
|
11672 |
|
|
|
11673 |
|
|
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
|
11674 |
|
|
-- and command signals in one record and unify the functions operating on this record.
|
11675 |
|
|
--
|
11676 |
|
|
use work.altera_ddr_phy_alt_mem_phy_addr_cmd_pkg.all;
|
11677 |
|
|
|
11678 |
|
|
|
11679 |
|
|
-- Individually include each of library files for the sub-blocks of the sequencer:
|
11680 |
|
|
--
|
11681 |
|
|
use work.altera_ddr_phy_alt_mem_phy_admin;
|
11682 |
|
|
--
|
11683 |
|
|
use work.altera_ddr_phy_alt_mem_phy_mmi;
|
11684 |
|
|
--
|
11685 |
|
|
use work.altera_ddr_phy_alt_mem_phy_iram;
|
11686 |
|
|
--
|
11687 |
|
|
use work.altera_ddr_phy_alt_mem_phy_dgrb;
|
11688 |
|
|
--
|
11689 |
|
|
use work.altera_ddr_phy_alt_mem_phy_dgwb;
|
11690 |
|
|
--
|
11691 |
|
|
use work.altera_ddr_phy_alt_mem_phy_ctrl;
|
11692 |
|
|
|
11693 |
|
|
--
|
11694 |
|
|
entity altera_ddr_phy_alt_mem_phy_seq IS
|
11695 |
|
|
generic (
|
11696 |
|
|
-- choice of FPGA device family and DRAM type
|
11697 |
|
|
FAMILY : string := "CYCLONEIII";
|
11698 |
|
|
MEM_IF_MEMTYPE : string := "DDR2";
|
11699 |
|
|
SPEED_GRADE : string := "C6";
|
11700 |
|
|
FAMILYGROUP_ID : natural := 2;
|
11701 |
|
|
|
11702 |
|
|
-- physical interface width definitions
|
11703 |
|
|
MEM_IF_DQS_WIDTH : natural := 9;
|
11704 |
|
|
MEM_IF_DWIDTH : natural := 72;
|
11705 |
|
|
MEM_IF_DM_WIDTH : natural := 9;
|
11706 |
|
|
MEM_IF_DQ_PER_DQS : natural := 8;
|
11707 |
|
|
DWIDTH_RATIO : natural := 4;
|
11708 |
|
|
CLOCK_INDEX_WIDTH : natural := 4;
|
11709 |
|
|
MEM_IF_CLK_PAIR_COUNT : natural := 3;
|
11710 |
|
|
MEM_IF_ADDR_WIDTH : natural := 13;
|
11711 |
|
|
MEM_IF_BANKADDR_WIDTH : natural := 3;
|
11712 |
|
|
MEM_IF_NUM_RANKS : natural := 1;
|
11713 |
|
|
MEM_IF_RANKS_PER_SLOT : natural := 1;
|
11714 |
|
|
ADV_LAT_WIDTH : natural := 5;
|
11715 |
|
|
RESYNCHRONISE_AVALON_DBG : natural := 0; -- 0 = false, 1 = true
|
11716 |
|
|
AV_IF_ADDR_WIDTH : natural := 13;
|
11717 |
|
|
|
11718 |
|
|
|
11719 |
|
|
-- setup / algorithm information
|
11720 |
|
|
NOM_DQS_PHASE_SETTING : natural := 2;
|
11721 |
|
|
SCAN_CLK_DIVIDE_BY : natural := 2;
|
11722 |
|
|
RDP_ADDR_WIDTH : natural := 4;
|
11723 |
|
|
PLL_STEPS_PER_CYCLE : natural := 16;
|
11724 |
|
|
IOE_PHASES_PER_TCK : natural := 8;
|
11725 |
|
|
IOE_DELAYS_PER_PHS : natural := 5;
|
11726 |
|
|
MEM_IF_CLK_PS : natural := 2500;
|
11727 |
|
|
|
11728 |
|
|
MEM_IF_ADDR_CMD_PHASE : natural := 270;
|
11729 |
|
|
|
11730 |
|
|
TRACKING_INTERVAL_IN_MS : natural := 128;
|
11731 |
|
|
|
11732 |
|
|
MEM_IF_CAL_BANK : natural := 0; -- location to calibrate to
|
11733 |
|
|
MEM_IF_CAL_BASE_COL : natural := 0; -- default all zeros
|
11734 |
|
|
MEM_IF_CAL_BASE_ROW : natural := 0;
|
11735 |
|
|
|
11736 |
|
|
WRITE_DESKEW_T10 : natural := 0;
|
11737 |
|
|
WRITE_DESKEW_T9NI : natural := 0;
|
11738 |
|
|
WRITE_DESKEW_T9I : natural := 0;
|
11739 |
|
|
WRITE_DESKEW_RANGE : natural := 0;
|
11740 |
|
|
-- initial mode register settings
|
11741 |
|
|
PHY_DEF_MR_1ST : natural := 0;
|
11742 |
|
|
PHY_DEF_MR_2ND : natural := 0;
|
11743 |
|
|
PHY_DEF_MR_3RD : natural := 0;
|
11744 |
|
|
PHY_DEF_MR_4TH : natural := 0;
|
11745 |
|
|
|
11746 |
|
|
MEM_IF_DQSN_EN : natural := 0; -- default off for Cyclone-III
|
11747 |
|
|
MEM_IF_DQS_CAPTURE_EN : natural := 1;
|
11748 |
|
|
|
11749 |
|
|
GENERATE_ADDITIONAL_DBG_RTL : natural := 0; -- 1 signals to include iram and mmi blocks and 0 not to include
|
11750 |
|
|
|
11751 |
|
|
SINGLE_DQS_DELAY_CONTROL_CODE : natural := 0; -- reserved for future use
|
11752 |
|
|
SNOOP_MRS : natural := 0; -- reserved for future use
|
11753 |
|
|
PRESET_RLAT : natural := 0; -- reserved for future use
|
11754 |
|
|
EN_OCT : natural := 1; -- Does the sequencer use OCT during calibration.
|
11755 |
|
|
OCT_LAT_WIDTH : natural := 6;
|
11756 |
|
|
SIM_TIME_REDUCTIONS : natural := 0; -- if 0 null, if 2 rrp for 1 dqs group and 1 cs
|
11757 |
|
|
CAPABILITIES : natural := 0; -- advertise capabilities i.e. which ctrl block states to execute (default all on)
|
11758 |
|
|
TINIT_TCK : natural := 80000;
|
11759 |
|
|
TINIT_RST : natural := 100;
|
11760 |
|
|
GENERATE_TRACKING_PHASE_STORE : natural := 0; -- reserved for future use
|
11761 |
|
|
IP_BUILDNUM : natural := 0
|
11762 |
|
|
);
|
11763 |
|
|
port (
|
11764 |
|
|
-- clk / reset
|
11765 |
|
|
clk : in std_logic;
|
11766 |
|
|
rst_n : in std_logic;
|
11767 |
|
|
|
11768 |
|
|
-- calibration status and prompt
|
11769 |
|
|
ctl_init_success : out std_logic;
|
11770 |
|
|
ctl_init_fail : out std_logic;
|
11771 |
|
|
ctl_recalibrate_req : in std_logic;
|
11772 |
|
|
|
11773 |
|
|
-- the following two signals are reserved for future use
|
11774 |
|
|
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
|
11775 |
|
|
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
|
11776 |
|
|
|
11777 |
|
|
-- pll reconfiguration
|
11778 |
|
|
seq_pll_inc_dec_n : out std_logic;
|
11779 |
|
|
seq_pll_start_reconfig : out std_logic;
|
11780 |
|
|
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
|
11781 |
|
|
seq_pll_phs_shift_busy : in std_logic;
|
11782 |
|
|
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
|
11783 |
|
|
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic/measure clock
|
11784 |
|
|
|
11785 |
|
|
|
11786 |
|
|
-- scanchain associated signals (reserved for future use)
|
11787 |
|
|
seq_scan_clk : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
|
11788 |
|
|
seq_scan_enable_dqs_config : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
|
11789 |
|
|
seq_scan_update : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
|
11790 |
|
|
seq_scan_din : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
|
11791 |
|
|
seq_scan_enable_ck : out std_logic_vector(MEM_IF_CLK_PAIR_COUNT - 1 downto 0);
|
11792 |
|
|
seq_scan_enable_dqs : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
|
11793 |
|
|
seq_scan_enable_dqsn : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
|
11794 |
|
|
seq_scan_enable_dq : out std_logic_vector(MEM_IF_DWIDTH - 1 downto 0);
|
11795 |
|
|
seq_scan_enable_dm : out std_logic_vector(MEM_IF_DM_WIDTH - 1 downto 0);
|
11796 |
|
|
seq_scan_enable_d : out std_logic_vector(MEM_IF_DWIDTH - 1 downto 0);
|
11797 |
|
|
hr_rsc_clk : in std_logic;
|
11798 |
|
|
|
11799 |
|
|
-- address / command interface (note these are mapped internally to the seq_ac record)
|
11800 |
|
|
seq_ac_addr : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_ADDR_WIDTH - 1 downto 0);
|
11801 |
|
|
seq_ac_ba : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_BANKADDR_WIDTH - 1 downto 0);
|
11802 |
|
|
seq_ac_cas_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
|
11803 |
|
|
seq_ac_ras_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
|
11804 |
|
|
seq_ac_we_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
|
11805 |
|
|
seq_ac_cke : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
|
11806 |
|
|
seq_ac_cs_n : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
|
11807 |
|
|
seq_ac_odt : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
|
11808 |
|
|
seq_ac_rst_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
|
11809 |
|
|
seq_ac_sel : out std_logic;
|
11810 |
|
|
seq_mem_clk_disable : out std_logic;
|
11811 |
|
|
|
11812 |
|
|
-- additional datapath latency (reserved for future use)
|
11813 |
|
|
seq_ac_add_1t_ac_lat_internal : out std_logic;
|
11814 |
|
|
seq_ac_add_1t_odt_lat_internal : out std_logic;
|
11815 |
|
|
seq_ac_add_2t : out std_logic;
|
11816 |
|
|
|
11817 |
|
|
-- read datapath interface
|
11818 |
|
|
seq_rdp_reset_req_n : out std_logic;
|
11819 |
|
|
seq_rdp_inc_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
|
11820 |
|
|
seq_rdp_dec_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
|
11821 |
|
|
rdata : in std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
|
11822 |
|
|
|
11823 |
|
|
-- read data valid (associated signals) interface
|
11824 |
|
|
seq_rdv_doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
|
11825 |
|
|
rdata_valid : in std_logic_vector( DWIDTH_RATIO/2 - 1 downto 0);
|
11826 |
|
|
seq_rdata_valid_lat_inc : out std_logic;
|
11827 |
|
|
seq_rdata_valid_lat_dec : out std_logic;
|
11828 |
|
|
seq_ctl_rlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
|
11829 |
|
|
|
11830 |
|
|
-- postamble interface (unused for Cyclone-III)
|
11831 |
|
|
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
|
11832 |
|
|
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
|
11833 |
|
|
seq_poa_protection_override_1x : out std_logic;
|
11834 |
|
|
|
11835 |
|
|
-- OCT path control
|
11836 |
|
|
seq_oct_oct_delay : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
|
11837 |
|
|
seq_oct_oct_extend : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
|
11838 |
|
|
seq_oct_value : out std_logic;
|
11839 |
|
|
|
11840 |
|
|
-- write data path interface
|
11841 |
|
|
seq_wdp_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
|
11842 |
|
|
seq_wdp_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
|
11843 |
|
|
seq_wdp_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
|
11844 |
|
|
seq_wdp_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
|
11845 |
|
|
seq_wdp_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
|
11846 |
|
|
seq_wdp_ovride : out std_logic;
|
11847 |
|
|
seq_dqs_add_2t_delay : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
|
11848 |
|
|
seq_ctl_wlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
|
11849 |
|
|
|
11850 |
|
|
-- address and command snooping interface (reserved for future use)
|
11851 |
|
|
ctl_seq_ac_snoop_addr : in std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_ADDR_WIDTH - 1 downto 0);
|
11852 |
|
|
ctl_seq_ac_snoop_ba : in std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_BANKADDR_WIDTH - 1 downto 0);
|
11853 |
|
|
ctl_seq_ac_snoop_cke : in std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
|
11854 |
|
|
ctl_seq_ac_snoop_cs_n : in std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
|
11855 |
|
|
ctl_seq_ac_snoop_cas_n : in std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
|
11856 |
|
|
ctl_seq_ac_snoop_ras_n : in std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
|
11857 |
|
|
ctl_seq_ac_snoop_we_n : in std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
|
11858 |
|
|
ctl_seq_ac_snoop_rst_n : in std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
|
11859 |
|
|
|
11860 |
|
|
-- mimic path interface
|
11861 |
|
|
seq_mmc_start : out std_logic;
|
11862 |
|
|
mmc_seq_done : in std_logic;
|
11863 |
|
|
mmc_seq_value : in std_logic;
|
11864 |
|
|
|
11865 |
|
|
--synchronous Avalon debug interface (internally re-synchronised to input clock (a generic option))
|
11866 |
|
|
dbg_seq_clk : in std_logic;
|
11867 |
|
|
dbg_seq_rst_n : in std_logic;
|
11868 |
|
|
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH - 1 downto 0);
|
11869 |
|
|
dbg_seq_wr : in std_logic;
|
11870 |
|
|
dbg_seq_rd : in std_logic;
|
11871 |
|
|
dbg_seq_cs : in std_logic;
|
11872 |
|
|
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
|
11873 |
|
|
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
|
11874 |
|
|
seq_dbg_waitrequest : out std_logic
|
11875 |
|
|
);
|
11876 |
|
|
end entity;
|
11877 |
|
|
|
11878 |
|
|
--
|
11879 |
|
|
architecture struct of altera_ddr_phy_alt_mem_phy_seq IS
|
11880 |
|
|
|
11881 |
|
|
-- debug signals (similar to those seen in the Quartus v8.0 DDR/DDR2 sequencer)
|
11882 |
|
|
signal rsu_multiple_valid_latencies_err : std_logic; -- true if >2 valid latency values are detected
|
11883 |
|
|
signal rsu_grt_one_dvw_err : std_logic; -- true if >1 data valid window is detected
|
11884 |
|
|
signal rsu_no_dvw_err : std_logic; -- true if no data valid window is detected
|
11885 |
|
|
signal rsu_codvw_phase : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
|
11886 |
|
|
signal rsu_codvw_size : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
|
11887 |
|
|
signal rsu_read_latency : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0); -- set to the correct read latency if calibration is successful
|
11888 |
|
|
|
11889 |
|
|
-- outputs from the dgrb to generate the above rsu_codvw_* signals and report status to the mmi
|
11890 |
|
|
signal dgrb_mmi : t_dgrb_mmi;
|
11891 |
|
|
|
11892 |
|
|
-- admin to mmi interface
|
11893 |
|
|
signal regs_admin_ctrl_rec : t_admin_ctrl; -- mmi register settings information
|
11894 |
|
|
signal admin_regs_status_rec : t_admin_stat; -- admin status information
|
11895 |
|
|
|
11896 |
|
|
-- odt enable from the admin block based on mr settings
|
11897 |
|
|
signal enable_odt : std_logic;
|
11898 |
|
|
|
11899 |
|
|
-- iram status information (sent to the ctrl block)
|
11900 |
|
|
signal iram_status : t_iram_stat;
|
11901 |
|
|
|
11902 |
|
|
-- dgrb iram write interface
|
11903 |
|
|
signal dgrb_iram : t_iram_push;
|
11904 |
|
|
|
11905 |
|
|
-- ctrl to iram interface
|
11906 |
|
|
signal ctrl_idib_top : natural; -- current write location in the iram
|
11907 |
|
|
signal ctrl_active_block : t_ctrl_active_block;
|
11908 |
|
|
signal ctrl_iram_push : t_ctrl_iram;
|
11909 |
|
|
signal iram_push_done : std_logic;
|
11910 |
|
|
signal ctrl_iram_ihi_write : std_logic;
|
11911 |
|
|
|
11912 |
|
|
-- local copies of calibration status
|
11913 |
|
|
signal ctl_init_success_int : std_logic;
|
11914 |
|
|
signal ctl_init_fail_int : std_logic;
|
11915 |
|
|
|
11916 |
|
|
-- refresh period failure flag
|
11917 |
|
|
signal trefi_failure : std_logic;
|
11918 |
|
|
|
11919 |
|
|
-- unified ctrl signal broadcast to all blocks from the ctrl block
|
11920 |
|
|
signal ctrl_broadcast : t_ctrl_command;
|
11921 |
|
|
|
11922 |
|
|
-- standardised status report per block to control block
|
11923 |
|
|
signal admin_ctrl : t_ctrl_stat;
|
11924 |
|
|
signal dgwb_ctrl : t_ctrl_stat;
|
11925 |
|
|
signal dgrb_ctrl : t_ctrl_stat;
|
11926 |
|
|
|
11927 |
|
|
-- mmi and ctrl block interface
|
11928 |
|
|
signal mmi_ctrl : t_mmi_ctrl;
|
11929 |
|
|
signal ctrl_mmi : t_ctrl_mmi;
|
11930 |
|
|
|
11931 |
|
|
-- write datapath override signals
|
11932 |
|
|
signal dgwb_wdp_override : std_logic;
|
11933 |
|
|
signal dgrb_wdp_override : std_logic;
|
11934 |
|
|
|
11935 |
|
|
-- address/command access request and grant between the dgrb/dgwb blocks and the admin block
|
11936 |
|
|
signal dgb_ac_access_gnt : std_logic;
|
11937 |
|
|
signal dgb_ac_access_gnt_r : std_logic;
|
11938 |
|
|
signal dgb_ac_access_req : std_logic;
|
11939 |
|
|
signal dgwb_ac_access_req : std_logic;
|
11940 |
|
|
signal dgrb_ac_access_req : std_logic;
|
11941 |
|
|
|
11942 |
|
|
-- per block address/command record (multiplexed in this entity)
|
11943 |
|
|
signal admin_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
|
11944 |
|
|
signal dgwb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
|
11945 |
|
|
signal dgrb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
|
11946 |
|
|
|
11947 |
|
|
-- doing read signal
|
11948 |
|
|
signal seq_rdv_doing_rd_int : std_logic_vector(seq_rdv_doing_rd'range);
|
11949 |
|
|
|
11950 |
|
|
-- local copy of interface to inc/dec latency on rdata_valid and postamble
|
11951 |
|
|
signal seq_rdata_valid_lat_dec_int : std_logic;
|
11952 |
|
|
signal seq_rdata_valid_lat_inc_int : std_logic;
|
11953 |
|
|
signal seq_poa_lat_inc_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
|
11954 |
|
|
signal seq_poa_lat_dec_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
|
11955 |
|
|
signal seq_poa_lat_dec_1x_sc_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
|
11956 |
|
|
signal seq_poa_lat_inc_1x_sc_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
|
11957 |
|
|
|
11958 |
|
|
-- local copy of write/read latency
|
11959 |
|
|
signal seq_ctl_wlat_int : std_logic_vector(seq_ctl_wlat'range);
|
11960 |
|
|
signal seq_ctl_rlat_int : std_logic_vector(seq_ctl_rlat'range);
|
11961 |
|
|
|
11962 |
|
|
-- parameterisation of dgrb / dgwb / admin blocks from mmi register settings
|
11963 |
|
|
signal parameterisation_rec : t_algm_paramaterisation;
|
11964 |
|
|
|
11965 |
|
|
-- PLL reconfig
|
11966 |
|
|
signal seq_pll_phs_shift_busy_r : std_logic;
|
11967 |
|
|
signal seq_pll_phs_shift_busy_ccd : std_logic;
|
11968 |
|
|
signal dgrb_pll_inc_dec_n : std_logic;
|
11969 |
|
|
signal dgrb_pll_start_reconfig : std_logic;
|
11970 |
|
|
signal dgrb_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
|
11971 |
|
|
signal dgrb_phs_shft_busy : std_logic;
|
11972 |
|
|
signal mmi_pll_inc_dec_n : std_logic;
|
11973 |
|
|
signal mmi_pll_start_reconfig : std_logic;
|
11974 |
|
|
signal mmi_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
|
11975 |
|
|
signal pll_mmi : t_pll_mmi;
|
11976 |
|
|
signal mmi_pll : t_mmi_pll_reconfig;
|
11977 |
|
|
|
11978 |
|
|
|
11979 |
|
|
-- address and command 1t setting (unused for Full Rate)
|
11980 |
|
|
signal int_ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
|
11981 |
|
|
signal dgrb_ctrl_ac_nt_good : std_logic;
|
11982 |
|
|
|
11983 |
|
|
-- the following signals are reserved for future use
|
11984 |
|
|
signal ctl_cal_byte_lanes_r : std_logic_vector(ctl_cal_byte_lanes'range);
|
11985 |
|
|
signal dgrb_sc : t_sc_int_ctrl;
|
11986 |
|
|
signal sc_dgrb_ack : std_logic;
|
11987 |
|
|
signal dgwb_sc : t_sc_int_ctrl;
|
11988 |
|
|
signal sc_dgwb_ack : std_logic;
|
11989 |
|
|
signal regs_sc_ctrl : t_sc_ctrl_if;
|
11990 |
|
|
signal sc_regs_status : t_sc_stat;
|
11991 |
|
|
signal proc_ctrl : t_ctrl_stat;
|
11992 |
|
|
signal setup_ctrl : t_ctrl_stat;
|
11993 |
|
|
signal mmi_setup : t_ctrl_cmd_id;
|
11994 |
|
|
signal proc_iram : t_iram_ctrl;
|
11995 |
|
|
signal setup_iram : t_iram_ctrl;
|
11996 |
|
|
signal dgwb_iram : t_iram_push;
|
11997 |
|
|
|
11998 |
|
|
-- convert input generics from natural to std_logic_vector
|
11999 |
|
|
constant c_phy_def_mr_1st_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_1ST, 16));
|
12000 |
|
|
constant c_phy_def_mr_2nd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_2ND, 16));
|
12001 |
|
|
constant c_phy_def_mr_3rd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_3RD, 16));
|
12002 |
|
|
constant c_phy_def_mr_4th_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_4TH, 16));
|
12003 |
|
|
|
12004 |
|
|
-- set sequencer capabilities
|
12005 |
|
|
constant c_capabilities : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(CAPABILITIES,32));
|
12006 |
|
|
|
12007 |
|
|
-- setup for address/command interface
|
12008 |
|
|
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
|
12009 |
|
|
|
12010 |
|
|
-- setup for odt signals
|
12011 |
|
|
-- odt setting as implemented in the altera high-performance controller for ddrx memories
|
12012 |
|
|
constant c_odt_settings : t_odt_array(0 to MEM_IF_NUM_RANKS-1) := set_odt_values(MEM_IF_NUM_RANKS, MEM_IF_RANKS_PER_SLOT, MEM_IF_MEMTYPE);
|
12013 |
|
|
|
12014 |
|
|
-- a prefix for all report signals to identify phy and sequencer block
|
12015 |
|
|
--
|
12016 |
|
|
constant seq_report_prefix : string := "altera_ddr_phy_alt_mem_phy_seq (top) : ";
|
12017 |
|
|
|
12018 |
|
|
-- setup iram configuration
|
12019 |
|
|
constant c_iram_addresses : t_base_hdr_addresses := calc_iram_addresses(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_NUM_RANKS, MEM_IF_DQS_CAPTURE_EN);
|
12020 |
|
|
constant c_int_iram_awidth : natural := c_iram_addresses.required_addr_bits;
|
12021 |
|
|
|
12022 |
|
|
constant c_preset_codvw_phase : natural := 0;
|
12023 |
|
|
constant c_preset_codvw_size : natural := 0;
|
12024 |
|
|
|
12025 |
|
|
begin -- architecture struct
|
12026 |
|
|
|
12027 |
|
|
-- ---------------------------------------------------------------
|
12028 |
|
|
-- tie off unused signals to default values
|
12029 |
|
|
-- ---------------------------------------------------------------
|
12030 |
|
|
|
12031 |
|
|
seq_poa_lat_dec_1x_sc_int <= (others => '0');
|
12032 |
|
|
seq_poa_lat_inc_1x_sc_int <= (others => '0');
|
12033 |
|
|
setup_iram <= defaults;
|
12034 |
|
|
setup_ctrl <= defaults; -- to ctrl block
|
12035 |
|
|
proc_iram <= defaults;
|
12036 |
|
|
proc_ctrl <= defaults;
|
12037 |
|
|
|
12038 |
|
|
-- scan chain associated signals
|
12039 |
|
|
seq_scan_clk <= (others => '0');
|
12040 |
|
|
seq_scan_enable_dqs_config <= (others => '0');
|
12041 |
|
|
seq_scan_update <= (others => '0');
|
12042 |
|
|
seq_scan_din <= (others => '0');
|
12043 |
|
|
sc_dgrb_ack <= '0';
|
12044 |
|
|
sc_dgwb_ack <= '0';
|
12045 |
|
|
sc_regs_status <= defaults;
|
12046 |
|
|
seq_scan_enable_ck <= (others => '0');
|
12047 |
|
|
seq_scan_enable_dqs <= (others => '0');
|
12048 |
|
|
seq_scan_enable_dqsn <= (others => '0');
|
12049 |
|
|
seq_scan_enable_dq <= (others => '0');
|
12050 |
|
|
seq_scan_enable_dm <= (others => '0');
|
12051 |
|
|
seq_scan_enable_d <= (others => '0');
|
12052 |
|
|
|
12053 |
|
|
seq_dqs_add_2t_delay <= (others => '0');
|
12054 |
|
|
|
12055 |
|
|
--
|
12056 |
|
|
admin: entity altera_ddr_phy_alt_mem_phy_admin
|
12057 |
|
|
generic map
|
12058 |
|
|
(
|
12059 |
|
|
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
|
12060 |
|
|
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
|
12061 |
|
|
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
|
12062 |
|
|
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
|
12063 |
|
|
DWIDTH_RATIO => DWIDTH_RATIO,
|
12064 |
|
|
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
|
12065 |
|
|
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
|
12066 |
|
|
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
|
12067 |
|
|
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
|
12068 |
|
|
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
|
12069 |
|
|
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
|
12070 |
|
|
MEM_IF_DQSN_EN => MEM_IF_DQSN_EN,
|
12071 |
|
|
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
|
12072 |
|
|
MEM_IF_CAL_BANK => MEM_IF_CAL_BANK,
|
12073 |
|
|
MEM_IF_CAL_BASE_ROW => MEM_IF_CAL_BASE_ROW,
|
12074 |
|
|
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
|
12075 |
|
|
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
|
12076 |
|
|
TINIT_TCK => TINIT_TCK,
|
12077 |
|
|
TINIT_RST => TINIT_RST
|
12078 |
|
|
)
|
12079 |
|
|
port map
|
12080 |
|
|
(
|
12081 |
|
|
clk => clk,
|
12082 |
|
|
rst_n => rst_n,
|
12083 |
|
|
mem_ac_swapped_ranks => mem_ac_swapped_ranks,
|
12084 |
|
|
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
|
12085 |
|
|
seq_ac => admin_ac,
|
12086 |
|
|
seq_ac_sel => seq_ac_sel,
|
12087 |
|
|
enable_odt => enable_odt,
|
12088 |
|
|
regs_admin_ctrl_rec => regs_admin_ctrl_rec,
|
12089 |
|
|
admin_regs_status_rec => admin_regs_status_rec,
|
12090 |
|
|
trefi_failure => trefi_failure,
|
12091 |
|
|
ctrl_admin => ctrl_broadcast,
|
12092 |
|
|
admin_ctrl => admin_ctrl,
|
12093 |
|
|
ac_access_req => dgb_ac_access_req,
|
12094 |
|
|
ac_access_gnt => dgb_ac_access_gnt,
|
12095 |
|
|
cal_fail => ctl_init_fail_int,
|
12096 |
|
|
cal_success => ctl_init_success_int
|
12097 |
|
|
);
|
12098 |
|
|
|
12099 |
|
|
-- selectively include the debug i/f (iram and mmi blocks)
|
12100 |
|
|
with_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 1 generate
|
12101 |
|
|
|
12102 |
|
|
signal mmi_iram : t_iram_ctrl;
|
12103 |
|
|
signal mmi_iram_enable_writes : std_logic;
|
12104 |
|
|
signal rrp_mem_loc : natural range 0 to 2 ** c_int_iram_awidth - 1;
|
12105 |
|
|
signal command_req_r : std_logic;
|
12106 |
|
|
|
12107 |
|
|
signal ctrl_broadcast_r : t_ctrl_command;
|
12108 |
|
|
|
12109 |
|
|
begin
|
12110 |
|
|
|
12111 |
|
|
-- register ctrl_broadcast locally
|
12112 |
|
|
process (clk, rst_n)
|
12113 |
|
|
begin
|
12114 |
|
|
if rst_n = '0' then
|
12115 |
|
|
ctrl_broadcast_r <= defaults;
|
12116 |
|
|
elsif rising_edge(clk) then
|
12117 |
|
|
ctrl_broadcast_r <= ctrl_broadcast;
|
12118 |
|
|
end if;
|
12119 |
|
|
end process;
|
12120 |
|
|
|
12121 |
|
|
--
|
12122 |
|
|
mmi : entity altera_ddr_phy_alt_mem_phy_mmi
|
12123 |
|
|
generic map (
|
12124 |
|
|
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
|
12125 |
|
|
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
|
12126 |
|
|
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
|
12127 |
|
|
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
|
12128 |
|
|
DWIDTH_RATIO => DWIDTH_RATIO,
|
12129 |
|
|
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
|
12130 |
|
|
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
|
12131 |
|
|
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
|
12132 |
|
|
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
|
12133 |
|
|
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
|
12134 |
|
|
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
|
12135 |
|
|
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
|
12136 |
|
|
RESYNCHRONISE_AVALON_DBG => RESYNCHRONISE_AVALON_DBG,
|
12137 |
|
|
AV_IF_ADDR_WIDTH => AV_IF_ADDR_WIDTH,
|
12138 |
|
|
NOM_DQS_PHASE_SETTING => NOM_DQS_PHASE_SETTING,
|
12139 |
|
|
SCAN_CLK_DIVIDE_BY => SCAN_CLK_DIVIDE_BY,
|
12140 |
|
|
RDP_ADDR_WIDTH => RDP_ADDR_WIDTH,
|
12141 |
|
|
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
|
12142 |
|
|
IOE_PHASES_PER_TCK => IOE_PHASES_PER_TCK,
|
12143 |
|
|
IOE_DELAYS_PER_PHS => IOE_DELAYS_PER_PHS,
|
12144 |
|
|
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
|
12145 |
|
|
PHY_DEF_MR_1ST => c_phy_def_mr_1st_sl_vector,
|
12146 |
|
|
PHY_DEF_MR_2ND => c_phy_def_mr_2nd_sl_vector,
|
12147 |
|
|
PHY_DEF_MR_3RD => c_phy_def_mr_3rd_sl_vector,
|
12148 |
|
|
PHY_DEF_MR_4TH => c_phy_def_mr_4th_sl_vector,
|
12149 |
|
|
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
|
12150 |
|
|
SNOOP_MRS => SNOOP_MRS,
|
12151 |
|
|
PRESET_RLAT => PRESET_RLAT,
|
12152 |
|
|
CAPABILITIES => CAPABILITIES,
|
12153 |
|
|
IRAM_AWIDTH => c_int_iram_awidth,
|
12154 |
|
|
TRACKING_INTERVAL_IN_MS => TRACKING_INTERVAL_IN_MS,
|
12155 |
|
|
READ_LAT_WIDTH => ADV_LAT_WIDTH
|
12156 |
|
|
)
|
12157 |
|
|
port map(
|
12158 |
|
|
clk => clk,
|
12159 |
|
|
rst_n => rst_n,
|
12160 |
|
|
dbg_seq_clk => dbg_seq_clk,
|
12161 |
|
|
dbg_seq_rst_n => dbg_seq_rst_n,
|
12162 |
|
|
dbg_seq_addr => dbg_seq_addr,
|
12163 |
|
|
dbg_seq_wr => dbg_seq_wr,
|
12164 |
|
|
dbg_seq_rd => dbg_seq_rd,
|
12165 |
|
|
dbg_seq_cs => dbg_seq_cs,
|
12166 |
|
|
dbg_seq_wr_data => dbg_seq_wr_data,
|
12167 |
|
|
seq_dbg_rd_data => seq_dbg_rd_data,
|
12168 |
|
|
seq_dbg_waitrequest => seq_dbg_waitrequest,
|
12169 |
|
|
regs_admin_ctrl => regs_admin_ctrl_rec,
|
12170 |
|
|
admin_regs_status => admin_regs_status_rec,
|
12171 |
|
|
regs_sc_ctrl => regs_sc_ctrl,
|
12172 |
|
|
sc_regs_status => sc_regs_status,
|
12173 |
|
|
mmi_iram => mmi_iram,
|
12174 |
|
|
mmi_iram_enable_writes => mmi_iram_enable_writes,
|
12175 |
|
|
iram_status => iram_status,
|
12176 |
|
|
mmi_ctrl => mmi_ctrl,
|
12177 |
|
|
ctrl_mmi => ctrl_mmi,
|
12178 |
|
|
int_ac_1t => int_ac_nt(0),
|
12179 |
|
|
invert_ac_1t => open,
|
12180 |
|
|
trefi_failure => trefi_failure,
|
12181 |
|
|
parameterisation_rec => parameterisation_rec,
|
12182 |
|
|
pll_mmi => pll_mmi,
|
12183 |
|
|
mmi_pll => mmi_pll,
|
12184 |
|
|
dgrb_mmi => dgrb_mmi
|
12185 |
|
|
);
|
12186 |
|
|
|
12187 |
|
|
|
12188 |
|
|
--
|
12189 |
|
|
iram : entity altera_ddr_phy_alt_mem_phy_iram
|
12190 |
|
|
generic map(
|
12191 |
|
|
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
|
12192 |
|
|
FAMILYGROUP_ID => FAMILYGROUP_ID,
|
12193 |
|
|
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
|
12194 |
|
|
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
|
12195 |
|
|
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
|
12196 |
|
|
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
|
12197 |
|
|
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
|
12198 |
|
|
IRAM_AWIDTH => c_int_iram_awidth,
|
12199 |
|
|
REFRESH_COUNT_INIT => 12,
|
12200 |
|
|
PRESET_RLAT => PRESET_RLAT,
|
12201 |
|
|
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
|
12202 |
|
|
CAPABILITIES => CAPABILITIES,
|
12203 |
|
|
IP_BUILDNUM => IP_BUILDNUM
|
12204 |
|
|
)
|
12205 |
|
|
port map(
|
12206 |
|
|
clk => clk,
|
12207 |
|
|
rst_n => rst_n,
|
12208 |
|
|
mmi_iram => mmi_iram,
|
12209 |
|
|
mmi_iram_enable_writes => mmi_iram_enable_writes,
|
12210 |
|
|
proc_iram => proc_iram,
|
12211 |
|
|
setup_iram => setup_iram,
|
12212 |
|
|
iram_status => iram_status,
|
12213 |
|
|
ctrl_iram => ctrl_broadcast_r,
|
12214 |
|
|
ctrl_iram_push => ctrl_iram_push,
|
12215 |
|
|
ctrl_active_block => ctrl_iram_push.active_block, -- TODO: tbd -- PC changed from DGRB
|
12216 |
|
|
dgwb_iram => dgwb_iram,
|
12217 |
|
|
dgrb_iram => dgrb_iram,
|
12218 |
|
|
iram_push_done => iram_push_done,
|
12219 |
|
|
ctrl_iram_ihi_write => ctrl_iram_ihi_write,
|
12220 |
|
|
admin_regs_status_rec => admin_regs_status_rec,
|
12221 |
|
|
ctrl_idib_top => ctrl_idib_top,
|
12222 |
|
|
ctrl_calibration_stage => encode_current_stage(ctrl_broadcast.command)
|
12223 |
|
|
);
|
12224 |
|
|
|
12225 |
|
|
-- calculate where current data should go in the iram
|
12226 |
|
|
process (clk, rst_n)
|
12227 |
|
|
|
12228 |
|
|
variable v_words_req : natural range 0 to 2 * MEM_IF_DWIDTH * PLL_STEPS_PER_CYCLE * DWIDTH_RATIO - 1; -- how many words are required
|
12229 |
|
|
|
12230 |
|
|
begin
|
12231 |
|
|
if rst_n = '0' then
|
12232 |
|
|
|
12233 |
|
|
ctrl_idib_top <= 0;
|
12234 |
|
|
command_req_r <= '0';
|
12235 |
|
|
rrp_mem_loc <= 0;
|
12236 |
|
|
|
12237 |
|
|
elsif rising_edge(clk) then
|
12238 |
|
|
|
12239 |
|
|
if command_req_r = '0' and ctrl_broadcast_r.command_req = '1' then -- execute once on each command_req assertion
|
12240 |
|
|
|
12241 |
|
|
-- default a 'safe location'
|
12242 |
|
|
ctrl_idib_top <= c_iram_addresses.safe_dummy;
|
12243 |
|
|
|
12244 |
|
|
case ctrl_broadcast_r.command is
|
12245 |
|
|
|
12246 |
|
|
when cmd_write_ihi => -- reset pointers
|
12247 |
|
|
|
12248 |
|
|
rrp_mem_loc <= c_iram_addresses.rrp;
|
12249 |
|
|
ctrl_idib_top <= 0; -- write header to zero location always
|
12250 |
|
|
|
12251 |
|
|
when cmd_rrp_sweep =>
|
12252 |
|
|
|
12253 |
|
|
-- add previous space requirement onto the current address
|
12254 |
|
|
ctrl_idib_top <= rrp_mem_loc;
|
12255 |
|
|
|
12256 |
|
|
-- add the current space requirement to v_rrp_mem_loc
|
12257 |
|
|
-- there are (DWIDTH_RATIO/2) * PLL_STEPS_PER_CYCLE phases swept packed into 32 bit words per pin
|
12258 |
|
|
-- note: special case for single_bit calibration stages (e.g. read_mtp alignment)
|
12259 |
|
|
|
12260 |
|
|
if ctrl_broadcast_r.command_op.single_bit = '1' then
|
12261 |
|
|
v_words_req := iram_wd_for_one_pin_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
|
12262 |
|
|
else
|
12263 |
|
|
v_words_req := iram_wd_for_full_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
|
12264 |
|
|
end if;
|
12265 |
|
|
|
12266 |
|
|
v_words_req := v_words_req + 2; -- add 1 word location for header / footer information
|
12267 |
|
|
|
12268 |
|
|
rrp_mem_loc <= rrp_mem_loc + v_words_req;
|
12269 |
|
|
|
12270 |
|
|
when cmd_rrp_seek |
|
12271 |
|
|
cmd_read_mtp =>
|
12272 |
|
|
|
12273 |
|
|
-- add previous space requirement onto the current address
|
12274 |
|
|
ctrl_idib_top <= rrp_mem_loc;
|
12275 |
|
|
|
12276 |
|
|
-- require 3 words - header, result and footer
|
12277 |
|
|
v_words_req := 3;
|
12278 |
|
|
|
12279 |
|
|
rrp_mem_loc <= rrp_mem_loc + v_words_req;
|
12280 |
|
|
|
12281 |
|
|
when others =>
|
12282 |
|
|
null;
|
12283 |
|
|
|
12284 |
|
|
end case;
|
12285 |
|
|
|
12286 |
|
|
end if;
|
12287 |
|
|
|
12288 |
|
|
command_req_r <= ctrl_broadcast_r.command_req;
|
12289 |
|
|
|
12290 |
|
|
end if;
|
12291 |
|
|
|
12292 |
|
|
end process;
|
12293 |
|
|
|
12294 |
|
|
end generate; -- with debug interface
|
12295 |
|
|
|
12296 |
|
|
-- if no debug interface (iram/mmi block) tie off relevant signals
|
12297 |
|
|
without_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 0 generate
|
12298 |
|
|
|
12299 |
|
|
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(CAPABILITIES, 32));
|
12300 |
|
|
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
|
12301 |
|
|
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE_EN);
|
12302 |
|
|
|
12303 |
|
|
signal mmi_regs : t_mmi_regs := defaults;
|
12304 |
|
|
|
12305 |
|
|
begin
|
12306 |
|
|
|
12307 |
|
|
-- avalon interface signals
|
12308 |
|
|
seq_dbg_rd_data <= (others => '0');
|
12309 |
|
|
seq_dbg_waitrequest <= '0';
|
12310 |
|
|
|
12311 |
|
|
-- The following registers are generated to simplify the assignments which follow
|
12312 |
|
|
-- but will be optimised away in synthesis
|
12313 |
|
|
mmi_regs.rw_regs <= defaults(c_phy_def_mr_1st_sl_vector,
|
12314 |
|
|
c_phy_def_mr_2nd_sl_vector,
|
12315 |
|
|
c_phy_def_mr_3rd_sl_vector,
|
12316 |
|
|
c_phy_def_mr_4th_sl_vector,
|
12317 |
|
|
NOM_DQS_PHASE_SETTING,
|
12318 |
|
|
PLL_STEPS_PER_CYCLE,
|
12319 |
|
|
c_pll_360_sweeps,
|
12320 |
|
|
TRACKING_INTERVAL_IN_MS,
|
12321 |
|
|
c_hl_stage_enable);
|
12322 |
|
|
|
12323 |
|
|
mmi_regs.ro_regs <= defaults(dgrb_mmi,
|
12324 |
|
|
ctrl_mmi,
|
12325 |
|
|
pll_mmi,
|
12326 |
|
|
mmi_regs.rw_regs.rw_if_test,
|
12327 |
|
|
'0', -- do not use iram
|
12328 |
|
|
MEM_IF_DQS_CAPTURE_EN,
|
12329 |
|
|
int_ac_nt(0),
|
12330 |
|
|
trefi_failure,
|
12331 |
|
|
iram_status,
|
12332 |
|
|
c_int_iram_awidth);
|
12333 |
|
|
|
12334 |
|
|
process(mmi_regs)
|
12335 |
|
|
begin
|
12336 |
|
|
-- debug parameterisation signals
|
12337 |
|
|
regs_admin_ctrl_rec <= pack_record(mmi_regs.rw_regs);
|
12338 |
|
|
regs_sc_ctrl <= defaults;
|
12339 |
|
|
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
|
12340 |
|
|
mmi_pll <= pack_record(mmi_regs.rw_regs);
|
12341 |
|
|
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
|
12342 |
|
|
end process;
|
12343 |
|
|
|
12344 |
|
|
-- from the iram
|
12345 |
|
|
iram_status <= defaults;
|
12346 |
|
|
iram_push_done <= '0';
|
12347 |
|
|
|
12348 |
|
|
end generate; -- without debug interface
|
12349 |
|
|
|
12350 |
|
|
--
|
12351 |
|
|
dgrb : entity altera_ddr_phy_alt_mem_phy_dgrb
|
12352 |
|
|
generic map(
|
12353 |
|
|
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
|
12354 |
|
|
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
|
12355 |
|
|
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
|
12356 |
|
|
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
|
12357 |
|
|
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
|
12358 |
|
|
DWIDTH_RATIO => DWIDTH_RATIO,
|
12359 |
|
|
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
|
12360 |
|
|
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
|
12361 |
|
|
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
|
12362 |
|
|
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
|
12363 |
|
|
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
|
12364 |
|
|
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
|
12365 |
|
|
PRESET_RLAT => PRESET_RLAT,
|
12366 |
|
|
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
|
12367 |
|
|
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
|
12368 |
|
|
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
|
12369 |
|
|
PRESET_CODVW_PHASE => c_preset_codvw_phase,
|
12370 |
|
|
PRESET_CODVW_SIZE => c_preset_codvw_size,
|
12371 |
|
|
MEM_IF_CAL_BANK => MEM_IF_CAL_BANK,
|
12372 |
|
|
MEM_IF_CAL_BASE_COL => MEM_IF_CAL_BASE_COL,
|
12373 |
|
|
EN_OCT => EN_OCT
|
12374 |
|
|
)
|
12375 |
|
|
port map(
|
12376 |
|
|
clk => clk,
|
12377 |
|
|
rst_n => rst_n,
|
12378 |
|
|
dgrb_ctrl => dgrb_ctrl,
|
12379 |
|
|
ctrl_dgrb => ctrl_broadcast,
|
12380 |
|
|
parameterisation_rec => parameterisation_rec,
|
12381 |
|
|
phs_shft_busy => dgrb_phs_shft_busy,
|
12382 |
|
|
seq_pll_inc_dec_n => dgrb_pll_inc_dec_n,
|
12383 |
|
|
seq_pll_select => dgrb_pll_select,
|
12384 |
|
|
seq_pll_start_reconfig => dgrb_pll_start_reconfig,
|
12385 |
|
|
pll_resync_clk_index => pll_resync_clk_index,
|
12386 |
|
|
pll_measure_clk_index => pll_measure_clk_index,
|
12387 |
|
|
dgrb_iram => dgrb_iram,
|
12388 |
|
|
iram_push_done => iram_push_done,
|
12389 |
|
|
dgrb_ac => dgrb_ac,
|
12390 |
|
|
dgrb_ac_access_req => dgrb_ac_access_req,
|
12391 |
|
|
dgrb_ac_access_gnt => dgb_ac_access_gnt_r,
|
12392 |
|
|
seq_rdp_inc_read_lat_1x => seq_rdp_inc_read_lat_1x,
|
12393 |
|
|
seq_rdp_dec_read_lat_1x => seq_rdp_dec_read_lat_1x,
|
12394 |
|
|
seq_rdata_valid_lat_inc => seq_rdata_valid_lat_inc_int,
|
12395 |
|
|
seq_rdata_valid_lat_dec => seq_rdata_valid_lat_dec_int,
|
12396 |
|
|
seq_poa_lat_dec_1x => seq_poa_lat_dec_1x_int,
|
12397 |
|
|
seq_poa_lat_inc_1x => seq_poa_lat_inc_1x_int,
|
12398 |
|
|
rdata_valid => rdata_valid,
|
12399 |
|
|
rdata => rdata,
|
12400 |
|
|
doing_rd => seq_rdv_doing_rd_int,
|
12401 |
|
|
rd_lat => seq_ctl_rlat_int,
|
12402 |
|
|
wd_lat => seq_ctl_wlat_int,
|
12403 |
|
|
dgrb_wdp_ovride => dgrb_wdp_override,
|
12404 |
|
|
seq_oct_value => seq_oct_value,
|
12405 |
|
|
seq_mmc_start => seq_mmc_start,
|
12406 |
|
|
mmc_seq_done => mmc_seq_done,
|
12407 |
|
|
mmc_seq_value => mmc_seq_value,
|
12408 |
|
|
dgrb_sc => dgrb_sc,
|
12409 |
|
|
sc_dgrb_ack => sc_dgrb_ack,
|
12410 |
|
|
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
|
12411 |
|
|
odt_settings => c_odt_settings,
|
12412 |
|
|
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
|
12413 |
|
|
dgrb_mmi => dgrb_mmi
|
12414 |
|
|
);
|
12415 |
|
|
|
12416 |
|
|
--
|
12417 |
|
|
dgwb : entity altera_ddr_phy_alt_mem_phy_dgwb
|
12418 |
|
|
generic map(
|
12419 |
|
|
-- Physical IF width definitions
|
12420 |
|
|
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
|
12421 |
|
|
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
|
12422 |
|
|
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
|
12423 |
|
|
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
|
12424 |
|
|
DWIDTH_RATIO => DWIDTH_RATIO,
|
12425 |
|
|
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
|
12426 |
|
|
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
|
12427 |
|
|
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
|
12428 |
|
|
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
|
12429 |
|
|
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
|
12430 |
|
|
MEM_IF_CAL_BANK => MEM_IF_CAL_BANK,
|
12431 |
|
|
MEM_IF_CAL_BASE_COL => MEM_IF_CAL_BASE_COL
|
12432 |
|
|
)
|
12433 |
|
|
port map(
|
12434 |
|
|
clk => clk,
|
12435 |
|
|
rst_n => rst_n,
|
12436 |
|
|
parameterisation_rec => parameterisation_rec,
|
12437 |
|
|
dgwb_ctrl => dgwb_ctrl,
|
12438 |
|
|
ctrl_dgwb => ctrl_broadcast,
|
12439 |
|
|
dgwb_iram => dgwb_iram,
|
12440 |
|
|
iram_push_done => iram_push_done,
|
12441 |
|
|
dgwb_ac_access_req => dgwb_ac_access_req,
|
12442 |
|
|
dgwb_ac_access_gnt => dgb_ac_access_gnt_r,
|
12443 |
|
|
dgwb_dqs_burst => seq_wdp_dqs_burst,
|
12444 |
|
|
dgwb_wdata_valid => seq_wdp_wdata_valid,
|
12445 |
|
|
dgwb_wdata => seq_wdp_wdata,
|
12446 |
|
|
dgwb_dm => seq_wdp_dm,
|
12447 |
|
|
dgwb_dqs => seq_wdp_dqs,
|
12448 |
|
|
dgwb_wdp_ovride => dgwb_wdp_override,
|
12449 |
|
|
dgwb_ac => dgwb_ac,
|
12450 |
|
|
dgwb_sc => dgwb_sc,
|
12451 |
|
|
sc_dgwb_ack => sc_dgwb_ack,
|
12452 |
|
|
bypassed_rdata => rdata(DWIDTH_RATIO * MEM_IF_DWIDTH -1 downto (DWIDTH_RATIO-1) * MEM_IF_DWIDTH),
|
12453 |
|
|
odt_settings => c_odt_settings
|
12454 |
|
|
);
|
12455 |
|
|
|
12456 |
|
|
--
|
12457 |
|
|
ctrl: entity altera_ddr_phy_alt_mem_phy_ctrl
|
12458 |
|
|
generic map(
|
12459 |
|
|
MEM_IF_DLL_LOCK_COUNT => 1280/(DWIDTH_RATIO/2),
|
12460 |
|
|
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
|
12461 |
|
|
DWIDTH_RATIO => DWIDTH_RATIO,
|
12462 |
|
|
IRAM_ADDRESSING => c_iram_addresses,
|
12463 |
|
|
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
|
12464 |
|
|
TRACKING_INTERVAL_IN_MS => TRACKING_INTERVAL_IN_MS,
|
12465 |
|
|
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
|
12466 |
|
|
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
|
12467 |
|
|
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
|
12468 |
|
|
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
|
12469 |
|
|
ACK_SEVERITY => warning
|
12470 |
|
|
)
|
12471 |
|
|
port map(
|
12472 |
|
|
clk => clk,
|
12473 |
|
|
rst_n => rst_n,
|
12474 |
|
|
ctl_init_success => ctl_init_success_int,
|
12475 |
|
|
ctl_init_fail => ctl_init_fail_int,
|
12476 |
|
|
ctl_recalibrate_req => ctl_recalibrate_req,
|
12477 |
|
|
sc_init_done => '1',
|
12478 |
|
|
iram_status => iram_status,
|
12479 |
|
|
iram_push_done => iram_push_done,
|
12480 |
|
|
ctrl_op_rec => ctrl_broadcast,
|
12481 |
|
|
admin_ctrl => admin_ctrl,
|
12482 |
|
|
dgrb_ctrl => dgrb_ctrl,
|
12483 |
|
|
dgwb_ctrl => dgwb_ctrl,
|
12484 |
|
|
proc_ctrl => proc_ctrl,
|
12485 |
|
|
setup_ctrl => setup_ctrl,
|
12486 |
|
|
ctrl_iram_ihi_write => ctrl_iram_ihi_write,
|
12487 |
|
|
ctrl_iram_push => ctrl_iram_push,
|
12488 |
|
|
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
|
12489 |
|
|
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
|
12490 |
|
|
int_ac_nt => int_ac_nt,
|
12491 |
|
|
mmi_ctrl => mmi_ctrl,
|
12492 |
|
|
ctrl_mmi => ctrl_mmi
|
12493 |
|
|
);
|
12494 |
|
|
|
12495 |
|
|
|
12496 |
|
|
-- ------------------------------------------------------------------
|
12497 |
|
|
-- generate legacy rsu signals
|
12498 |
|
|
-- ------------------------------------------------------------------
|
12499 |
|
|
process(rst_n, clk)
|
12500 |
|
|
begin
|
12501 |
|
|
if rst_n = '0' then
|
12502 |
|
|
rsu_multiple_valid_latencies_err <= '0';
|
12503 |
|
|
rsu_grt_one_dvw_err <= '0';
|
12504 |
|
|
rsu_no_dvw_err <= '0';
|
12505 |
|
|
rsu_codvw_phase <= (others => '0');
|
12506 |
|
|
rsu_codvw_size <= (others => '0');
|
12507 |
|
|
rsu_read_latency <= (others => '0');
|
12508 |
|
|
elsif rising_edge(clk) then
|
12509 |
|
|
|
12510 |
|
|
if dgrb_ctrl.command_err = '1' then
|
12511 |
|
|
case to_integer(unsigned(dgrb_ctrl.command_result)) is
|
12512 |
|
|
when C_ERR_RESYNC_NO_VALID_PHASES =>
|
12513 |
|
|
rsu_no_dvw_err <= '1';
|
12514 |
|
|
when C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS =>
|
12515 |
|
|
rsu_multiple_valid_latencies_err <= '1';
|
12516 |
|
|
when others => null;
|
12517 |
|
|
end case;
|
12518 |
|
|
end if;
|
12519 |
|
|
|
12520 |
|
|
rsu_codvw_phase(dgrb_mmi.cal_codvw_phase'range) <= dgrb_mmi.cal_codvw_phase;
|
12521 |
|
|
rsu_codvw_size(dgrb_mmi.cal_codvw_size'range) <= dgrb_mmi.cal_codvw_size;
|
12522 |
|
|
rsu_read_latency <= seq_ctl_rlat_int;
|
12523 |
|
|
rsu_grt_one_dvw_err <= dgrb_mmi.codvw_grt_one_dvw;
|
12524 |
|
|
|
12525 |
|
|
-- Reset the flag on a recal request :
|
12526 |
|
|
if ( ctl_recalibrate_req = '1') then
|
12527 |
|
|
rsu_grt_one_dvw_err <= '0';
|
12528 |
|
|
rsu_no_dvw_err <= '0';
|
12529 |
|
|
rsu_multiple_valid_latencies_err <= '0';
|
12530 |
|
|
end if;
|
12531 |
|
|
|
12532 |
|
|
end if;
|
12533 |
|
|
end process;
|
12534 |
|
|
|
12535 |
|
|
-- ---------------------------------------------------------------
|
12536 |
|
|
-- top level multiplexing and ctrl functionality
|
12537 |
|
|
-- ---------------------------------------------------------------
|
12538 |
|
|
|
12539 |
|
|
oct_delay_block : block
|
12540 |
|
|
constant DEFAULT_OCT_DELAY_CONST : integer := - 2; -- higher increases delay by one mem_clk cycle, lower decreases delay by one mem_clk cycle.
|
12541 |
|
|
constant DEFAULT_OCT_EXTEND : natural := 5;
|
12542 |
|
|
|
12543 |
|
|
-- Returns additive latency extracted from mr0 as a natural number.
|
12544 |
|
|
function decode_cl(mr0 : in std_logic_vector(12 downto 0))
|
12545 |
|
|
return natural is
|
12546 |
|
|
variable v_cl : natural range 0 to 2**4 - 1;
|
12547 |
|
|
begin
|
12548 |
|
|
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
|
12549 |
|
|
v_cl := to_integer(unsigned(mr0(6 downto 4)));
|
12550 |
|
|
elsif MEM_IF_MEMTYPE = "DDR3" then
|
12551 |
|
|
v_cl := to_integer(unsigned(mr0(6 downto 4))) + 4;
|
12552 |
|
|
else
|
12553 |
|
|
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
|
12554 |
|
|
end if;
|
12555 |
|
|
|
12556 |
|
|
return v_cl;
|
12557 |
|
|
end function;
|
12558 |
|
|
|
12559 |
|
|
|
12560 |
|
|
-- Returns additive latency extracted from mr1 as a natural number.
|
12561 |
|
|
function decode_al(mr1 : in std_logic_vector(12 downto 0))
|
12562 |
|
|
return natural is
|
12563 |
|
|
variable v_al : natural range 0 to 2**4 - 1;
|
12564 |
|
|
begin
|
12565 |
|
|
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
|
12566 |
|
|
v_al := to_integer(unsigned(mr1(5 downto 3)));
|
12567 |
|
|
elsif MEM_IF_MEMTYPE = "DDR3" then
|
12568 |
|
|
v_al := to_integer(unsigned(mr1(4 downto 3)));
|
12569 |
|
|
else
|
12570 |
|
|
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
|
12571 |
|
|
end if;
|
12572 |
|
|
|
12573 |
|
|
return v_al;
|
12574 |
|
|
end function;
|
12575 |
|
|
|
12576 |
|
|
|
12577 |
|
|
-- Returns additive latency extracted from mr1 as a natural number.
|
12578 |
|
|
function decode_cwl(
|
12579 |
|
|
mr0 : in std_logic_vector(12 downto 0);
|
12580 |
|
|
mr2 : in std_logic_vector(12 downto 0)
|
12581 |
|
|
)
|
12582 |
|
|
return natural is
|
12583 |
|
|
variable v_cwl : natural range 0 to 2**4 - 1;
|
12584 |
|
|
begin
|
12585 |
|
|
if MEM_IF_MEMTYPE = "DDR" then
|
12586 |
|
|
v_cwl := 1;
|
12587 |
|
|
elsif MEM_IF_MEMTYPE = "DDR2" then
|
12588 |
|
|
v_cwl := decode_cl(mr0) - 1;
|
12589 |
|
|
elsif MEM_IF_MEMTYPE = "DDR3" then
|
12590 |
|
|
v_cwl := to_integer(unsigned(mr2(4 downto 3))) + 5;
|
12591 |
|
|
else
|
12592 |
|
|
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
|
12593 |
|
|
end if;
|
12594 |
|
|
|
12595 |
|
|
return v_cwl;
|
12596 |
|
|
end function;
|
12597 |
|
|
|
12598 |
|
|
begin
|
12599 |
|
|
-- Process to work out timings for OCT extension and delay with respect to doing_read. NOTE that it is calculated on the basis of CL, CWL, ctl_wlat
|
12600 |
|
|
oct_delay_proc : process(clk, rst_n)
|
12601 |
|
|
variable v_cl : natural range 0 to 2**4 - 1; -- Total read latency.
|
12602 |
|
|
variable v_cwl : natural range 0 to 2**4 - 1; -- Total write latency
|
12603 |
|
|
variable oct_delay : natural range 0 to 2**OCT_LAT_WIDTH - 1;
|
12604 |
|
|
begin
|
12605 |
|
|
if rst_n = '0' then
|
12606 |
|
|
seq_oct_oct_delay <= (others => '0');
|
12607 |
|
|
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
|
12608 |
|
|
elsif rising_edge(clk) then
|
12609 |
|
|
if ctl_init_success_int = '1' then
|
12610 |
|
|
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
|
12611 |
|
|
|
12612 |
|
|
v_cl := decode_cl(admin_regs_status_rec.mr0);
|
12613 |
|
|
v_cwl := decode_cwl(admin_regs_status_rec.mr0, admin_regs_status_rec.mr2);
|
12614 |
|
|
|
12615 |
|
|
oct_delay := DWIDTH_RATIO * to_integer(unsigned(seq_ctl_wlat_int)) / 2 + (v_cl - v_cwl) + DEFAULT_OCT_DELAY_CONST;
|
12616 |
|
|
seq_oct_oct_delay <= std_logic_vector(to_unsigned(oct_delay, OCT_LAT_WIDTH));
|
12617 |
|
|
else
|
12618 |
|
|
seq_oct_oct_delay <= (others => '0');
|
12619 |
|
|
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
|
12620 |
|
|
end if;
|
12621 |
|
|
end if;
|
12622 |
|
|
end process;
|
12623 |
|
|
end block;
|
12624 |
|
|
|
12625 |
|
|
|
12626 |
|
|
-- control postamble protection override signal (seq_poa_protection_override_1x)
|
12627 |
|
|
process(clk, rst_n)
|
12628 |
|
|
variable v_warning_given : std_logic;
|
12629 |
|
|
begin
|
12630 |
|
|
if rst_n = '0' then
|
12631 |
|
|
seq_poa_protection_override_1x <= '0';
|
12632 |
|
|
|
12633 |
|
|
v_warning_given := '0';
|
12634 |
|
|
elsif rising_edge(clk) then
|
12635 |
|
|
|
12636 |
|
|
case ctrl_broadcast.command is
|
12637 |
|
|
when cmd_rdv |
|
12638 |
|
|
cmd_rrp_sweep |
|
12639 |
|
|
cmd_rrp_seek |
|
12640 |
|
|
cmd_prep_adv_rd_lat |
|
12641 |
|
|
cmd_prep_adv_wr_lat => seq_poa_protection_override_1x <= '1';
|
12642 |
|
|
when others => seq_poa_protection_override_1x <= '0';
|
12643 |
|
|
end case;
|
12644 |
|
|
|
12645 |
|
|
-- seq_poa_protection_override_1x <= '1';
|
12646 |
|
|
|
12647 |
|
|
end if;
|
12648 |
|
|
end process;
|
12649 |
|
|
|
12650 |
|
|
ac_mux : block
|
12651 |
|
|
|
12652 |
|
|
signal seen_phy_init_complete : std_logic;
|
12653 |
|
|
|
12654 |
|
|
signal ctrl_broadcast_r : t_ctrl_command;
|
12655 |
|
|
|
12656 |
|
|
begin
|
12657 |
|
|
|
12658 |
|
|
-- register ctrl_broadcast locally
|
12659 |
|
|
-- #for speed and to reduce fan out
|
12660 |
|
|
process (clk, rst_n)
|
12661 |
|
|
begin
|
12662 |
|
|
if rst_n = '0' then
|
12663 |
|
|
ctrl_broadcast_r <= defaults;
|
12664 |
|
|
elsif rising_edge(clk) then
|
12665 |
|
|
ctrl_broadcast_r <= ctrl_broadcast;
|
12666 |
|
|
end if;
|
12667 |
|
|
end process;
|
12668 |
|
|
|
12669 |
|
|
-- multiplex mem interface control between admin, dgrb and dgwb
|
12670 |
|
|
process(clk, rst_n)
|
12671 |
|
|
variable v_seq_ac_mux : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
|
12672 |
|
|
begin
|
12673 |
|
|
if rst_n = '0' then
|
12674 |
|
|
|
12675 |
|
|
seq_rdv_doing_rd <= (others => '0');
|
12676 |
|
|
|
12677 |
|
|
seq_mem_clk_disable <= '1';
|
12678 |
|
|
seen_phy_init_complete <= '0';
|
12679 |
|
|
|
12680 |
|
|
seq_ac_addr <= (others => '0');
|
12681 |
|
|
seq_ac_ba <= (others => '0');
|
12682 |
|
|
seq_ac_cas_n <= (others => '1');
|
12683 |
|
|
seq_ac_ras_n <= (others => '1');
|
12684 |
|
|
seq_ac_we_n <= (others => '1');
|
12685 |
|
|
seq_ac_cke <= (others => '0');
|
12686 |
|
|
seq_ac_cs_n <= (others => '1');
|
12687 |
|
|
seq_ac_odt <= (others => '0');
|
12688 |
|
|
seq_ac_rst_n <= (others => '0');
|
12689 |
|
|
|
12690 |
|
|
elsif rising_edge(clk) then
|
12691 |
|
|
|
12692 |
|
|
seq_rdv_doing_rd <= seq_rdv_doing_rd_int;
|
12693 |
|
|
|
12694 |
|
|
if dgwb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
|
12695 |
|
|
v_seq_ac_mux := dgwb_ac;
|
12696 |
|
|
elsif dgrb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
|
12697 |
|
|
v_seq_ac_mux := dgrb_ac;
|
12698 |
|
|
else
|
12699 |
|
|
v_seq_ac_mux := admin_ac;
|
12700 |
|
|
end if;
|
12701 |
|
|
|
12702 |
|
|
if ctl_recalibrate_req = '1' then
|
12703 |
|
|
seq_mem_clk_disable <= '1';
|
12704 |
|
|
seen_phy_init_complete <= '0';
|
12705 |
|
|
elsif ctrl_broadcast_r.command = cmd_init_dram and ctrl_broadcast_r.command_req = '1' then
|
12706 |
|
|
seq_mem_clk_disable <= '0';
|
12707 |
|
|
seen_phy_init_complete <= '1';
|
12708 |
|
|
end if;
|
12709 |
|
|
|
12710 |
|
|
if seen_phy_init_complete /= '1' then -- if not initialised the phy hold in reset
|
12711 |
|
|
|
12712 |
|
|
seq_ac_addr <= (others => '0');
|
12713 |
|
|
seq_ac_ba <= (others => '0');
|
12714 |
|
|
seq_ac_cas_n <= (others => '1');
|
12715 |
|
|
seq_ac_ras_n <= (others => '1');
|
12716 |
|
|
seq_ac_we_n <= (others => '1');
|
12717 |
|
|
seq_ac_cke <= (others => '0');
|
12718 |
|
|
seq_ac_cs_n <= (others => '1');
|
12719 |
|
|
seq_ac_odt <= (others => '0');
|
12720 |
|
|
seq_ac_rst_n <= (others => '0');
|
12721 |
|
|
|
12722 |
|
|
else
|
12723 |
|
|
|
12724 |
|
|
if enable_odt = '0' then
|
12725 |
|
|
v_seq_ac_mux := mask(c_seq_addr_cmd_config, v_seq_ac_mux, odt, '0');
|
12726 |
|
|
end if;
|
12727 |
|
|
|
12728 |
|
|
unpack_addr_cmd_vector (
|
12729 |
|
|
c_seq_addr_cmd_config,
|
12730 |
|
|
v_seq_ac_mux,
|
12731 |
|
|
seq_ac_addr,
|
12732 |
|
|
seq_ac_ba,
|
12733 |
|
|
seq_ac_cas_n,
|
12734 |
|
|
seq_ac_ras_n,
|
12735 |
|
|
seq_ac_we_n,
|
12736 |
|
|
seq_ac_cke,
|
12737 |
|
|
seq_ac_cs_n,
|
12738 |
|
|
seq_ac_odt,
|
12739 |
|
|
seq_ac_rst_n);
|
12740 |
|
|
|
12741 |
|
|
end if;
|
12742 |
|
|
|
12743 |
|
|
end if;
|
12744 |
|
|
end process;
|
12745 |
|
|
|
12746 |
|
|
end block;
|
12747 |
|
|
|
12748 |
|
|
-- register dgb_ac_access_gnt signal to ensure ODT set correctly in dgrb and dgwb prior to a read or write operation
|
12749 |
|
|
process(clk, rst_n)
|
12750 |
|
|
begin
|
12751 |
|
|
if rst_n = '0' then
|
12752 |
|
|
dgb_ac_access_gnt_r <= '0';
|
12753 |
|
|
elsif rising_edge(clk) then
|
12754 |
|
|
dgb_ac_access_gnt_r <= dgb_ac_access_gnt;
|
12755 |
|
|
end if;
|
12756 |
|
|
end process;
|
12757 |
|
|
|
12758 |
|
|
-- multiplex access request from dgrb/dgwb to admin block with checking for multiple accesses
|
12759 |
|
|
process (dgrb_ac_access_req, dgwb_ac_access_req)
|
12760 |
|
|
begin
|
12761 |
|
|
dgb_ac_access_req <= '0';
|
12762 |
|
|
if dgwb_ac_access_req = '1' and dgrb_ac_access_req = '1' then
|
12763 |
|
|
report seq_report_prefix & "multiple accesses attempted from DGRB and DGWB to admin block via signals dg.b_ac_access_reg " severity failure;
|
12764 |
|
|
elsif dgwb_ac_access_req = '1' or dgrb_ac_access_req = '1' then
|
12765 |
|
|
dgb_ac_access_req <= '1';
|
12766 |
|
|
end if;
|
12767 |
|
|
end process;
|
12768 |
|
|
|
12769 |
|
|
-- switch postamble and rdata_valid latencies
|
12770 |
|
|
-- note: postamble unused for Cyclone-III but code maintained for future use
|
12771 |
|
|
|
12772 |
|
|
process(clk, rst_n)
|
12773 |
|
|
variable lat_change : natural range 0 to 63;
|
12774 |
|
|
begin
|
12775 |
|
|
if rst_n = '0' then
|
12776 |
|
|
seq_rdata_valid_lat_dec <= '0';
|
12777 |
|
|
seq_rdata_valid_lat_inc <= '0';
|
12778 |
|
|
seq_poa_lat_dec_1x <= (others => '0');
|
12779 |
|
|
seq_poa_lat_inc_1x <= (others => '0');
|
12780 |
|
|
lat_change := 0;
|
12781 |
|
|
elsif rising_edge(clk) then
|
12782 |
|
|
|
12783 |
|
|
if c_capabilities(c_hl_css_reg_cal_dis_bit) = '0' then
|
12784 |
|
|
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int or seq_poa_lat_inc_1x_sc_int;
|
12785 |
|
|
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int or seq_poa_lat_dec_1x_sc_int;
|
12786 |
|
|
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
|
12787 |
|
|
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
|
12788 |
|
|
|
12789 |
|
|
else
|
12790 |
|
|
seq_poa_lat_dec_1x <= (others => '0');
|
12791 |
|
|
seq_poa_lat_inc_1x <= (others => '0');
|
12792 |
|
|
seq_rdata_valid_lat_inc <= '0';
|
12793 |
|
|
seq_rdata_valid_lat_dec <= '0';
|
12794 |
|
|
|
12795 |
|
|
if lat_change /= 0 and lat_change /= 61 then -- allow time for resynch clocks to lock
|
12796 |
|
|
lat_change := lat_change + 1;
|
12797 |
|
|
elsif ctl_recalibrate_req = '1' then
|
12798 |
|
|
lat_change := 0;
|
12799 |
|
|
end if;
|
12800 |
|
|
|
12801 |
|
|
if ( (lat_change >= 14)
|
12802 |
|
|
and (lat_change mod 2 = 0)
|
12803 |
|
|
)then
|
12804 |
|
|
seq_poa_lat_dec_1x <= (others => '1');
|
12805 |
|
|
end if;
|
12806 |
|
|
|
12807 |
|
|
if ( (lat_change >= 20)
|
12808 |
|
|
and (lat_change mod 2 = 0)
|
12809 |
|
|
)then
|
12810 |
|
|
seq_rdata_valid_lat_dec <= '1';
|
12811 |
|
|
end if;
|
12812 |
|
|
|
12813 |
|
|
end if;
|
12814 |
|
|
|
12815 |
|
|
end if;
|
12816 |
|
|
end process;
|
12817 |
|
|
|
12818 |
|
|
-- register output fail/success signals - avoiding optimisation out
|
12819 |
|
|
process(clk, rst_n)
|
12820 |
|
|
begin
|
12821 |
|
|
if rst_n = '0' then
|
12822 |
|
|
ctl_init_fail <= '0';
|
12823 |
|
|
ctl_init_success <= '0';
|
12824 |
|
|
elsif rising_edge(clk) then
|
12825 |
|
|
ctl_init_fail <= ctl_init_fail_int;
|
12826 |
|
|
ctl_init_success <= ctl_init_success_int;
|
12827 |
|
|
end if;
|
12828 |
|
|
end process;
|
12829 |
|
|
|
12830 |
|
|
-- ctl_cal_byte_lanes is currently unused
|
12831 |
|
|
-- seq_rdp_reset_req_n - when ctl_recalibrate_req issued
|
12832 |
|
|
process(clk,rst_n)
|
12833 |
|
|
begin
|
12834 |
|
|
if rst_n = '0' then
|
12835 |
|
|
seq_rdp_reset_req_n <= '0';
|
12836 |
|
|
ctl_cal_byte_lanes_r <= (others => '1');
|
12837 |
|
|
elsif rising_edge(clk) then
|
12838 |
|
|
ctl_cal_byte_lanes_r <= not ctl_cal_byte_lanes;
|
12839 |
|
|
|
12840 |
|
|
if ctl_recalibrate_req = '1' then
|
12841 |
|
|
seq_rdp_reset_req_n <= '0';
|
12842 |
|
|
elsif sc_regs_status.busy = '0' then
|
12843 |
|
|
seq_rdp_reset_req_n <= '1';
|
12844 |
|
|
end if;
|
12845 |
|
|
end if;
|
12846 |
|
|
end process;
|
12847 |
|
|
|
12848 |
|
|
-- register 1t addr/cmd and odt latency outputs
|
12849 |
|
|
process(clk, rst_n)
|
12850 |
|
|
begin
|
12851 |
|
|
if rst_n = '0' then
|
12852 |
|
|
seq_ac_add_1t_ac_lat_internal <= '0';
|
12853 |
|
|
seq_ac_add_1t_odt_lat_internal <= '0';
|
12854 |
|
|
seq_ac_add_2t <= '0';
|
12855 |
|
|
elsif rising_edge(clk) then
|
12856 |
|
|
seq_ac_add_1t_ac_lat_internal <= int_ac_nt(0);
|
12857 |
|
|
seq_ac_add_1t_odt_lat_internal <= int_ac_nt(0);
|
12858 |
|
|
seq_ac_add_2t <= '0';
|
12859 |
|
|
end if;
|
12860 |
|
|
end process;
|
12861 |
|
|
|
12862 |
|
|
-- override write datapath signal generation
|
12863 |
|
|
process(dgwb_wdp_override, dgrb_wdp_override, ctl_init_success_int, ctl_init_fail_int)
|
12864 |
|
|
begin
|
12865 |
|
|
if ctl_init_success_int = '0' and ctl_init_fail_int = '0' then -- if calibrating
|
12866 |
|
|
seq_wdp_ovride <= dgwb_wdp_override or dgrb_wdp_override;
|
12867 |
|
|
else
|
12868 |
|
|
seq_wdp_ovride <= '0';
|
12869 |
|
|
end if;
|
12870 |
|
|
end process;
|
12871 |
|
|
|
12872 |
|
|
-- output write/read latency
|
12873 |
|
|
seq_ctl_wlat <= seq_ctl_wlat_int;
|
12874 |
|
|
seq_ctl_rlat <= seq_ctl_rlat_int;
|
12875 |
|
|
|
12876 |
|
|
process (clk, rst_n)
|
12877 |
|
|
begin
|
12878 |
|
|
if rst_n = '0' then
|
12879 |
|
|
seq_pll_phs_shift_busy_r <= '0';
|
12880 |
|
|
seq_pll_phs_shift_busy_ccd <= '0';
|
12881 |
|
|
elsif rising_edge(clk) then
|
12882 |
|
|
seq_pll_phs_shift_busy_r <= seq_pll_phs_shift_busy;
|
12883 |
|
|
seq_pll_phs_shift_busy_ccd <= seq_pll_phs_shift_busy_r;
|
12884 |
|
|
end if;
|
12885 |
|
|
end process;
|
12886 |
|
|
|
12887 |
|
|
|
12888 |
|
|
pll_ctrl: block
|
12889 |
|
|
|
12890 |
|
|
-- static resync setup variables for sim time reductions
|
12891 |
|
|
signal static_rst_offset : natural range 0 to 2*PLL_STEPS_PER_CYCLE;
|
12892 |
|
|
signal phs_shft_busy_1r : std_logic;
|
12893 |
|
|
signal pll_set_delay : natural range 100 downto 0; -- wait 100 clock cycles for clk to be stable before setting resync phase
|
12894 |
|
|
|
12895 |
|
|
-- pll signal generation
|
12896 |
|
|
signal mmi_pll_active : boolean;
|
12897 |
|
|
signal seq_pll_phs_shift_busy_ccd_1t : std_logic;
|
12898 |
|
|
|
12899 |
|
|
begin
|
12900 |
|
|
|
12901 |
|
|
-- multiplex ppl interface between dgrb and mmi blocks
|
12902 |
|
|
-- plus static setup of rsc phase to a known 'good' condition
|
12903 |
|
|
process(clk,rst_n)
|
12904 |
|
|
|
12905 |
|
|
begin
|
12906 |
|
|
if rst_n = '0' then
|
12907 |
|
|
|
12908 |
|
|
seq_pll_inc_dec_n <= '0';
|
12909 |
|
|
seq_pll_start_reconfig <= '0';
|
12910 |
|
|
seq_pll_select <= (others => '0');
|
12911 |
|
|
|
12912 |
|
|
dgrb_phs_shft_busy <= '0';
|
12913 |
|
|
|
12914 |
|
|
-- static resync setup variables for sim time reductions
|
12915 |
|
|
if SIM_TIME_REDUCTIONS = 1 then
|
12916 |
|
|
static_rst_offset <= c_preset_codvw_phase;
|
12917 |
|
|
else
|
12918 |
|
|
static_rst_offset <= 0;
|
12919 |
|
|
end if;
|
12920 |
|
|
|
12921 |
|
|
phs_shft_busy_1r <= '0';
|
12922 |
|
|
pll_set_delay <= 100;
|
12923 |
|
|
|
12924 |
|
|
elsif rising_edge(clk) then
|
12925 |
|
|
|
12926 |
|
|
dgrb_phs_shft_busy <= '0';
|
12927 |
|
|
|
12928 |
|
|
if static_rst_offset /= 0 and pll_set_delay = 0 then
|
12929 |
|
|
|
12930 |
|
|
seq_pll_inc_dec_n <= '1';
|
12931 |
|
|
seq_pll_start_reconfig <= '1';
|
12932 |
|
|
seq_pll_select <= pll_resync_clk_index;
|
12933 |
|
|
|
12934 |
|
|
if seq_pll_phs_shift_busy_ccd = '1' then -- no metastability hardening needed in simulation
|
12935 |
|
|
-- PLL phase shift started - so stop requesting a shift
|
12936 |
|
|
seq_pll_start_reconfig <= '0';
|
12937 |
|
|
end if;
|
12938 |
|
|
|
12939 |
|
|
if seq_pll_phs_shift_busy_ccd = '0' and phs_shft_busy_1r = '1' then
|
12940 |
|
|
-- PLL phase shift finished - so proceed to flush the datapath
|
12941 |
|
|
static_rst_offset <= static_rst_offset - 1;
|
12942 |
|
|
seq_pll_start_reconfig <= '0';
|
12943 |
|
|
end if;
|
12944 |
|
|
|
12945 |
|
|
phs_shft_busy_1r <= seq_pll_phs_shift_busy_ccd;
|
12946 |
|
|
|
12947 |
|
|
else
|
12948 |
|
|
|
12949 |
|
|
if ctrl_iram_push.active_block = ret_dgrb then
|
12950 |
|
|
seq_pll_inc_dec_n <= dgrb_pll_inc_dec_n;
|
12951 |
|
|
seq_pll_start_reconfig <= dgrb_pll_start_reconfig;
|
12952 |
|
|
seq_pll_select <= dgrb_pll_select;
|
12953 |
|
|
dgrb_phs_shft_busy <= seq_pll_phs_shift_busy_ccd;
|
12954 |
|
|
else
|
12955 |
|
|
seq_pll_inc_dec_n <= mmi_pll_inc_dec_n;
|
12956 |
|
|
seq_pll_start_reconfig <= mmi_pll_start_reconfig;
|
12957 |
|
|
seq_pll_select <= mmi_pll_select;
|
12958 |
|
|
end if;
|
12959 |
|
|
|
12960 |
|
|
end if;
|
12961 |
|
|
|
12962 |
|
|
if pll_set_delay /= 0 then
|
12963 |
|
|
pll_set_delay <= pll_set_delay - 1;
|
12964 |
|
|
end if;
|
12965 |
|
|
|
12966 |
|
|
end if;
|
12967 |
|
|
end process;
|
12968 |
|
|
|
12969 |
|
|
|
12970 |
|
|
|
12971 |
|
|
-- generate mmi pll signals
|
12972 |
|
|
process (clk, rst_n)
|
12973 |
|
|
|
12974 |
|
|
begin
|
12975 |
|
|
if rst_n = '0' then
|
12976 |
|
|
|
12977 |
|
|
pll_mmi.pll_busy <= '0';
|
12978 |
|
|
pll_mmi.err <= (others => '0');
|
12979 |
|
|
mmi_pll_inc_dec_n <= '0';
|
12980 |
|
|
mmi_pll_start_reconfig <= '0';
|
12981 |
|
|
mmi_pll_select <= (others => '0');
|
12982 |
|
|
mmi_pll_active <= false;
|
12983 |
|
|
seq_pll_phs_shift_busy_ccd_1t <= '0';
|
12984 |
|
|
|
12985 |
|
|
elsif rising_edge(clk) then
|
12986 |
|
|
|
12987 |
|
|
if mmi_pll_active = true then
|
12988 |
|
|
pll_mmi.pll_busy <= '1';
|
12989 |
|
|
else
|
12990 |
|
|
pll_mmi.pll_busy <= mmi_pll.pll_phs_shft_up_wc or mmi_pll.pll_phs_shft_dn_wc;
|
12991 |
|
|
end if;
|
12992 |
|
|
|
12993 |
|
|
if pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' then
|
12994 |
|
|
pll_mmi.err <= "01";
|
12995 |
|
|
elsif pll_mmi.err = "00" and mmi_pll_active = true then
|
12996 |
|
|
pll_mmi.err <= "10";
|
12997 |
|
|
elsif pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' and mmi_pll_active = true then
|
12998 |
|
|
pll_mmi.err <= "11";
|
12999 |
|
|
end if;
|
13000 |
|
|
|
13001 |
|
|
if mmi_pll.pll_phs_shft_up_wc = '1' and mmi_pll_active = false then
|
13002 |
|
|
mmi_pll_inc_dec_n <= '1';
|
13003 |
|
|
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
|
13004 |
|
|
mmi_pll_active <= true;
|
13005 |
|
|
|
13006 |
|
|
elsif mmi_pll.pll_phs_shft_dn_wc = '1' and mmi_pll_active = false then
|
13007 |
|
|
mmi_pll_inc_dec_n <= '0';
|
13008 |
|
|
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
|
13009 |
|
|
mmi_pll_active <= true;
|
13010 |
|
|
|
13011 |
|
|
elsif seq_pll_phs_shift_busy_ccd_1t = '1' and seq_pll_phs_shift_busy_ccd = '0' then
|
13012 |
|
|
mmi_pll_start_reconfig <= '0';
|
13013 |
|
|
mmi_pll_active <= false;
|
13014 |
|
|
|
13015 |
|
|
elsif mmi_pll_active = true and mmi_pll_start_reconfig = '0' and seq_pll_phs_shift_busy_ccd = '0' then
|
13016 |
|
|
mmi_pll_start_reconfig <= '1';
|
13017 |
|
|
|
13018 |
|
|
elsif seq_pll_phs_shift_busy_ccd_1t = '0' and seq_pll_phs_shift_busy_ccd = '1' then
|
13019 |
|
|
mmi_pll_start_reconfig <= '0';
|
13020 |
|
|
|
13021 |
|
|
end if;
|
13022 |
|
|
|
13023 |
|
|
seq_pll_phs_shift_busy_ccd_1t <= seq_pll_phs_shift_busy_ccd;
|
13024 |
|
|
|
13025 |
|
|
end if;
|
13026 |
|
|
end process;
|
13027 |
|
|
|
13028 |
|
|
end block; -- pll_ctrl
|
13029 |
|
|
|
13030 |
|
|
--synopsys synthesis_off
|
13031 |
|
|
|
13032 |
|
|
reporting : block
|
13033 |
|
|
|
13034 |
|
|
function pass_or_fail_report( cal_success : in std_logic;
|
13035 |
|
|
cal_fail : in std_logic
|
13036 |
|
|
) return string is
|
13037 |
|
|
begin
|
13038 |
|
|
if cal_success = '1' and cal_fail = '1' then
|
13039 |
|
|
return "unknown state cal_fail and cal_success both high";
|
13040 |
|
|
end if;
|
13041 |
|
|
if cal_success = '1' then
|
13042 |
|
|
return "PASSED";
|
13043 |
|
|
end if;
|
13044 |
|
|
if cal_fail = '1' then
|
13045 |
|
|
return "FAILED";
|
13046 |
|
|
end if;
|
13047 |
|
|
return "calibration report run whilst sequencer is still calibrating";
|
13048 |
|
|
end function;
|
13049 |
|
|
|
13050 |
|
|
function is_stage_disabled ( stage_name : in string;
|
13051 |
|
|
stage_dis : in std_logic
|
13052 |
|
|
) return string is
|
13053 |
|
|
begin
|
13054 |
|
|
if stage_dis = '0' then
|
13055 |
|
|
return "";
|
13056 |
|
|
else
|
13057 |
|
|
return stage_name & " stage is disabled" & LF;
|
13058 |
|
|
end if;
|
13059 |
|
|
end function;
|
13060 |
|
|
|
13061 |
|
|
function disabled_stages ( capabilities : in std_logic_vector
|
13062 |
|
|
) return string is
|
13063 |
|
|
begin
|
13064 |
|
|
return is_stage_disabled("all calibration", c_capabilities(c_hl_css_reg_cal_dis_bit)) &
|
13065 |
|
|
is_stage_disabled("initialisation", c_capabilities(c_hl_css_reg_phy_initialise_dis_bit)) &
|
13066 |
|
|
is_stage_disabled("DRAM initialisation", c_capabilities(c_hl_css_reg_init_dram_dis_bit)) &
|
13067 |
|
|
is_stage_disabled("iram header write", c_capabilities(c_hl_css_reg_write_ihi_dis_bit)) &
|
13068 |
|
|
is_stage_disabled("burst training pattern write", c_capabilities(c_hl_css_reg_write_btp_dis_bit)) &
|
13069 |
|
|
is_stage_disabled("read resynch phase (reset stage) calculation", c_capabilities(c_hl_css_reg_rrp_reset_dis_bit)) &
|
13070 |
|
|
is_stage_disabled("read resynch phase (sweep stage) calculation", c_capabilities(c_hl_css_reg_rrp_sweep_dis_bit)) &
|
13071 |
|
|
is_stage_disabled("read resynch phase (seek stage) calculation", c_capabilities(c_hl_css_reg_rrp_seek_dis_bit)) &
|
13072 |
|
|
is_stage_disabled("read data valid window calculation", c_capabilities(c_hl_css_reg_rdv_dis_bit)) &
|
13073 |
|
|
is_stage_disabled("write latency timing calc", c_capabilities(c_hl_css_reg_was_dis_bit)) &
|
13074 |
|
|
is_stage_disabled("advertise read latency", c_capabilities(c_hl_css_reg_adv_rd_lat_dis_bit)) &
|
13075 |
|
|
is_stage_disabled("advertise write latency", c_capabilities(c_hl_css_reg_adv_wr_lat_dis_bit)) &
|
13076 |
|
|
is_stage_disabled("write customer mode register settings", c_capabilities(c_hl_css_reg_prep_customer_mr_setup_dis_bit)) &
|
13077 |
|
|
is_stage_disabled("tracking", c_capabilities(c_hl_css_reg_tracking_dis_bit));
|
13078 |
|
|
end function;
|
13079 |
|
|
|
13080 |
|
|
function read_resync_report ( codvw_phase : in std_logic_vector;
|
13081 |
|
|
codvw_size : in std_logic_vector ) return string
|
13082 |
|
|
is
|
13083 |
|
|
|
13084 |
|
|
begin
|
13085 |
|
|
if SIM_TIME_REDUCTIONS = 1 then
|
13086 |
|
|
return "-- read resynch phase static setup (no calibration run) report:" & LF &
|
13087 |
|
|
" -- statically set centre of data valid window phase : " & natural'image(to_integer(unsigned(codvw_phase))) & LF &
|
13088 |
|
|
" -- statically set centre of data valid window size : " & natural'image(to_integer(unsigned(codvw_size))) & LF &
|
13089 |
|
|
" -- note: this mode only works for simulation and sets resync phase" & LF &
|
13090 |
|
|
" to a known good operating condition for no test bench" & LF &
|
13091 |
|
|
" delays on mem_dq signal" & LF;
|
13092 |
|
|
else
|
13093 |
|
|
return "-- read resynch phase calibration report:" & LF &
|
13094 |
|
|
" -- calibrated centre of data valid window phase : " & natural'image(to_integer(unsigned(codvw_phase))) & LF &
|
13095 |
|
|
" -- calibrated centre of data valid window size : " & natural'image(to_integer(unsigned(codvw_size))) & LF;
|
13096 |
|
|
end if;
|
13097 |
|
|
end function;
|
13098 |
|
|
|
13099 |
|
|
function ac_nt_report( ac_nt : in std_logic_vector;
|
13100 |
|
|
dgrb_ctrl_ac_nt_good : in std_logic ) return string
|
13101 |
|
|
is
|
13102 |
|
|
|
13103 |
|
|
begin
|
13104 |
|
|
if DWIDTH_RATIO = 4 then
|
13105 |
|
|
if dgrb_ctrl_ac_nt_good = '1' then
|
13106 |
|
|
if ac_nt(0) = '1' then
|
13107 |
|
|
return "-- chosen address and command 1T delay: add 1T delay" & LF;
|
13108 |
|
|
else
|
13109 |
|
|
return "-- chosen address and command 1T delay: no 1T delay" & LF;
|
13110 |
|
|
end if;
|
13111 |
|
|
else
|
13112 |
|
|
return "-- no valid address and command phase chosen (calibration FAILED)" & LF;
|
13113 |
|
|
end if;
|
13114 |
|
|
else
|
13115 |
|
|
return "";
|
13116 |
|
|
end if;
|
13117 |
|
|
end function;
|
13118 |
|
|
|
13119 |
|
|
function calibration_report ( capabilities : in std_logic_vector;
|
13120 |
|
|
cal_success : in std_logic;
|
13121 |
|
|
cal_fail : in std_logic;
|
13122 |
|
|
ctl_rlat : in std_logic_vector;
|
13123 |
|
|
ctl_wlat : in std_logic_vector;
|
13124 |
|
|
codvw_phase : in std_logic_vector;
|
13125 |
|
|
codvw_size : in std_logic_vector;
|
13126 |
|
|
ac_nt : in std_logic_vector;
|
13127 |
|
|
dgrb_ctrl_ac_nt_good : in std_logic) return string
|
13128 |
|
|
is
|
13129 |
|
|
|
13130 |
|
|
begin
|
13131 |
|
|
return seq_report_prefix & " report..." & LF &
|
13132 |
|
|
"-----------------------------------------------------------------------" & LF &
|
13133 |
|
|
"-- **** ALTMEMPHY CALIBRATION has completed ****" & LF &
|
13134 |
|
|
"-- Status:" & LF &
|
13135 |
|
|
"-- calibration has : " & pass_or_fail_report(cal_success, cal_fail) & LF &
|
13136 |
|
|
"-- PHY read latency (ctl_rlat) is : " & natural'image(to_integer(unsigned(ctl_rlat))) & LF &
|
13137 |
|
|
"-- address/command to PHY write latency (ctl_wlat) is : " & natural'image(to_integer(unsigned(ctl_wlat))) & LF &
|
13138 |
|
|
read_resync_report(codvw_phase, codvw_size) &
|
13139 |
|
|
ac_nt_report(ac_nt, dgrb_ctrl_ac_nt_good) &
|
13140 |
|
|
disabled_stages(capabilities) &
|
13141 |
|
|
"-----------------------------------------------------------------------";
|
13142 |
|
|
end function;
|
13143 |
|
|
|
13144 |
|
|
begin
|
13145 |
|
|
|
13146 |
|
|
-- -------------------------------------------------------
|
13147 |
|
|
-- calibration result reporting
|
13148 |
|
|
-- -------------------------------------------------------
|
13149 |
|
|
process(rst_n, clk)
|
13150 |
|
|
variable v_reports_written : std_logic;
|
13151 |
|
|
variable v_cal_request_r : std_logic;
|
13152 |
|
|
variable v_rewrite_report : std_logic;
|
13153 |
|
|
|
13154 |
|
|
begin
|
13155 |
|
|
if rst_n = '0' then
|
13156 |
|
|
v_reports_written := '0';
|
13157 |
|
|
v_cal_request_r := '0';
|
13158 |
|
|
v_rewrite_report := '0';
|
13159 |
|
|
|
13160 |
|
|
elsif Rising_Edge(clk) then
|
13161 |
|
|
if v_reports_written = '0' then
|
13162 |
|
|
if ctl_init_success_int = '1' or ctl_init_fail_int = '1' then
|
13163 |
|
|
v_reports_written := '1';
|
13164 |
|
|
|
13165 |
|
|
report calibration_report(c_capabilities,
|
13166 |
|
|
ctl_init_success_int,
|
13167 |
|
|
ctl_init_fail_int,
|
13168 |
|
|
seq_ctl_rlat_int,
|
13169 |
|
|
seq_ctl_wlat_int,
|
13170 |
|
|
dgrb_mmi.cal_codvw_phase,
|
13171 |
|
|
dgrb_mmi.cal_codvw_size,
|
13172 |
|
|
int_ac_nt,
|
13173 |
|
|
dgrb_ctrl_ac_nt_good
|
13174 |
|
|
) severity note;
|
13175 |
|
|
|
13176 |
|
|
end if;
|
13177 |
|
|
end if;
|
13178 |
|
|
|
13179 |
|
|
-- if recalibrate request triggered watch for cal success / fail going low and re-trigger report writing
|
13180 |
|
|
if ctl_recalibrate_req = '1' and v_cal_request_r = '0' then
|
13181 |
|
|
v_rewrite_report := '1';
|
13182 |
|
|
end if;
|
13183 |
|
|
if v_rewrite_report = '1' and ctl_init_success_int = '0' and ctl_init_fail_int = '0' then
|
13184 |
|
|
v_reports_written := '0';
|
13185 |
|
|
v_rewrite_report := '0';
|
13186 |
|
|
end if;
|
13187 |
|
|
|
13188 |
|
|
v_cal_request_r := ctl_recalibrate_req;
|
13189 |
|
|
end if;
|
13190 |
|
|
end process;
|
13191 |
|
|
|
13192 |
|
|
-- -------------------------------------------------------
|
13193 |
|
|
-- capabilities vector reporting and coarse PHY setup sanity checks
|
13194 |
|
|
-- -------------------------------------------------------
|
13195 |
|
|
|
13196 |
|
|
process(rst_n, clk)
|
13197 |
|
|
variable reports_written : std_logic;
|
13198 |
|
|
begin
|
13199 |
|
|
if rst_n = '0' then
|
13200 |
|
|
reports_written := '0';
|
13201 |
|
|
|
13202 |
|
|
elsif Rising_Edge(clk) then
|
13203 |
|
|
|
13204 |
|
|
if reports_written = '0' then
|
13205 |
|
|
reports_written := '1';
|
13206 |
|
|
if MEM_IF_MEMTYPE="DDR" or MEM_IF_MEMTYPE="DDR2" or MEM_IF_MEMTYPE="DDR3" then
|
13207 |
|
|
if DWIDTH_RATIO = 2 or DWIDTH_RATIO = 4 then
|
13208 |
|
|
report disabled_stages(c_capabilities) severity note;
|
13209 |
|
|
else
|
13210 |
|
|
report seq_report_prefix & "unsupported rate for non-levelling AFI PHY sequencer - only full- or half-rate supported" severity warning;
|
13211 |
|
|
end if;
|
13212 |
|
|
else
|
13213 |
|
|
report seq_report_prefix & "memory type " & MEM_IF_MEMTYPE & " is not supported in non-levelling AFI PHY sequencer" severity failure;
|
13214 |
|
|
end if;
|
13215 |
|
|
end if;
|
13216 |
|
|
end if;
|
13217 |
|
|
|
13218 |
|
|
end process;
|
13219 |
|
|
|
13220 |
|
|
end block; -- reporting
|
13221 |
|
|
|
13222 |
|
|
--synopsys synthesis_on
|
13223 |
|
|
|
13224 |
|
|
end architecture struct;
|