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xianfeng |
//
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`ifdef ALT_MEM_PHY_DEFINES
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`else
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`include "alt_mem_phy_defines.v"
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`endif
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//
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module altera_ddr_phy_alt_mem_phy_seq_wrapper (
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// dss ports
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phy_clk_1x,
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reset_phy_clk_1x_n,
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ctl_cal_success,
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ctl_cal_fail,
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ctl_cal_req,
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int_RANK_HAS_ADDR_SWAP,
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ctl_cal_byte_lane_sel_n,
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seq_pll_inc_dec_n,
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seq_pll_start_reconfig,
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seq_pll_select,
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phs_shft_busy,
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pll_resync_clk_index,
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pll_measure_clk_index,
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sc_clk_dp,
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scan_enable_dqs_config,
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scan_update,
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scan_din,
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scan_enable_ck,
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scan_enable_dqs,
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scan_enable_dqsn,
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scan_enable_dq,
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scan_enable_dm,
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scan_enable_d,
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hr_rsc_clk,
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seq_ac_addr,
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seq_ac_ba,
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seq_ac_cas_n,
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seq_ac_ras_n,
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seq_ac_we_n,
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seq_ac_cke,
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seq_ac_cs_n,
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seq_ac_odt,
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seq_ac_rst_n,
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seq_ac_sel,
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seq_mem_clk_disable,
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ctl_add_1t_ac_lat_internal,
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ctl_add_1t_odt_lat_internal,
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ctl_add_intermediate_regs_internal,
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seq_rdv_doing_rd,
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seq_rdp_reset_req_n,
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seq_rdp_inc_read_lat_1x,
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seq_rdp_dec_read_lat_1x,
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ctl_rdata,
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int_rdata_valid_1t,
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seq_rdata_valid_lat_inc,
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seq_rdata_valid_lat_dec,
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ctl_rlat,
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seq_poa_lat_dec_1x,
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seq_poa_lat_inc_1x,
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seq_poa_protection_override_1x,
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seq_oct_oct_delay,
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seq_oct_oct_extend,
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seq_oct_val,
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seq_wdp_dqs_burst,
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seq_wdp_wdata_valid,
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seq_wdp_wdata,
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seq_wdp_dm,
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seq_wdp_dqs,
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seq_wdp_ovride,
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seq_dqs_add_2t_delay,
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ctl_wlat,
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ctl_addr,
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ctl_ba,
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ctl_cke,
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ctl_cs_n,
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ctl_cas_n,
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ctl_ras_n,
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ctl_we_n,
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ctl_rst_n,
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seq_mmc_start,
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mmc_seq_done,
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mmc_seq_value,
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dbg_clk,
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dbg_reset_n,
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dbg_addr,
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dbg_wr,
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dbg_rd,
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dbg_cs,
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dbg_wr_data,
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dbg_rd_data,
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dbg_waitrequest
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);
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//Inserted Generics
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localparam SPEED_GRADE = "C6";
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localparam MEM_IF_DQS_WIDTH = 2;
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localparam MEM_IF_DWIDTH = 16;
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localparam MEM_IF_DM_WIDTH = 2;
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localparam MEM_IF_DQ_PER_DQS = 8;
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localparam DWIDTH_RATIO = 2;
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localparam CLOCK_INDEX_WIDTH = 3;
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localparam MEM_IF_CLK_PAIR_COUNT = 1;
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localparam MEM_IF_ADDR_WIDTH = 13;
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localparam MEM_IF_BANKADDR_WIDTH = 2;
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localparam MEM_IF_CS_WIDTH = 1;
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localparam RESYNCHRONISE_AVALON_DBG = 0;
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localparam DBG_A_WIDTH = 13;
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localparam DQS_PHASE_SETTING = 2;
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localparam SCAN_CLK_DIVIDE_BY = 2;
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localparam PLL_STEPS_PER_CYCLE = 64;
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localparam MEM_IF_CLK_PS = 6667;
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localparam DQS_DELAY_CTL_WIDTH = 6;
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localparam MEM_IF_MEMTYPE = "DDR";
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localparam RANK_HAS_ADDR_SWAP = 0;
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localparam MEM_IF_MR_0 = 50;
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localparam MEM_IF_MR_1 = 0;
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localparam MEM_IF_MR_2 = 0;
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localparam MEM_IF_MR_3 = 0;
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localparam MEM_IF_OCT_EN = 0;
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localparam IP_BUILDNUM = 235;
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localparam FAMILY = "Cyclone III";
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localparam FAMILYGROUP_ID = 2;
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localparam MEM_IF_ADDR_CMD_PHASE = 90;
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localparam CAPABILITIES = 2048;
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localparam WRITE_DESKEW_T10 = 0;
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localparam WRITE_DESKEW_T9NI = 0;
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localparam WRITE_DESKEW_T9I = 0;
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localparam WRITE_DESKEW_RANGE = 0;
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localparam IOE_PHASES_PER_TCK = 12;
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localparam ADV_LAT_WIDTH = 5;
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localparam RDP_ADDR_WIDTH = 4;
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localparam IOE_DELAYS_PER_PHS = 5;
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localparam SINGLE_DQS_DELAY_CONTROL_CODE = 0;
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localparam SNOOP_MRS = 0;
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localparam PRESET_RLAT = 0;
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localparam MEM_IF_DQS_CAPTURE_EN = 0;
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localparam REDUCE_SIM_TIME = 0;
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localparam TINIT_TCK = 30004;
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localparam TINIT_RST = 0;
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localparam GENERATE_ADDITIONAL_DBG_RTL = 0;
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localparam MEM_IF_CS_PER_RANK = 1;
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localparam MEM_IF_RANKS_PER_SLOT = 1;
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localparam OCT_LAT_WIDTH = ADV_LAT_WIDTH;
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localparam GENERATE_TRACKING_PHASE_STORE = 0;
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// note that num_ranks if the number of discrete chip select signals output from the sequencer
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// cs_width is the total number of chip selects which go from the phy to the memory (there can
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// be more than one chip select per rank).
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localparam MEM_IF_NUM_RANKS = MEM_IF_CS_WIDTH/MEM_IF_CS_PER_RANK;
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input wire phy_clk_1x;
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input wire reset_phy_clk_1x_n;
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output wire ctl_cal_success;
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output wire ctl_cal_fail;
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input wire ctl_cal_req;
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input wire [MEM_IF_NUM_RANKS - 1 : 0] int_RANK_HAS_ADDR_SWAP;
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input wire [MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 : 0] ctl_cal_byte_lane_sel_n;
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output wire seq_pll_inc_dec_n;
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output wire seq_pll_start_reconfig;
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output wire [CLOCK_INDEX_WIDTH - 1 : 0] seq_pll_select;
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input wire phs_shft_busy;
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input wire [CLOCK_INDEX_WIDTH - 1 : 0] pll_resync_clk_index;
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input wire [CLOCK_INDEX_WIDTH - 1 : 0] pll_measure_clk_index;
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output [MEM_IF_DQS_WIDTH - 1 : 0] sc_clk_dp;
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output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_enable_dqs_config;
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output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_update;
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output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_din;
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output wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] scan_enable_ck;
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output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_enable_dqs;
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output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_enable_dqsn;
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output wire [MEM_IF_DWIDTH - 1 : 0] scan_enable_dq;
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output wire [MEM_IF_DM_WIDTH - 1 : 0] scan_enable_dm;
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output wire [MEM_IF_DWIDTH - 1 : 0] scan_enable_d;
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input wire hr_rsc_clk;
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output wire [(DWIDTH_RATIO/2) * MEM_IF_ADDR_WIDTH - 1 : 0] seq_ac_addr;
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output wire [(DWIDTH_RATIO/2) * MEM_IF_BANKADDR_WIDTH - 1 : 0] seq_ac_ba;
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output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_cas_n;
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output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_ras_n;
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output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_we_n;
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output wire [(DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 : 0] seq_ac_cke;
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output wire [(DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 : 0] seq_ac_cs_n;
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output wire [(DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 : 0] seq_ac_odt;
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output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_rst_n;
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output wire seq_ac_sel;
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output wire seq_mem_clk_disable;
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output wire ctl_add_1t_ac_lat_internal;
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output wire ctl_add_1t_odt_lat_internal;
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output wire ctl_add_intermediate_regs_internal;
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output wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_rdv_doing_rd;
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output wire seq_rdp_reset_req_n;
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output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_rdp_inc_read_lat_1x;
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output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_rdp_dec_read_lat_1x;
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input wire [DWIDTH_RATIO * MEM_IF_DWIDTH - 1 : 0] ctl_rdata;
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input wire [DWIDTH_RATIO/2 - 1 : 0] int_rdata_valid_1t;
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output wire seq_rdata_valid_lat_inc;
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output wire seq_rdata_valid_lat_dec;
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output wire [ADV_LAT_WIDTH - 1 : 0] ctl_rlat;
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output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_poa_lat_dec_1x;
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output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_poa_lat_inc_1x;
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output wire seq_poa_protection_override_1x;
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output wire [OCT_LAT_WIDTH - 1 : 0] seq_oct_oct_delay;
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output wire [OCT_LAT_WIDTH - 1 : 0] seq_oct_oct_extend;
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output wire seq_oct_val;
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output wire [(DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 : 0] seq_wdp_dqs_burst;
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output wire [(DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 : 0] seq_wdp_wdata_valid;
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output wire [DWIDTH_RATIO * MEM_IF_DWIDTH - 1 : 0] seq_wdp_wdata;
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output wire [DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 : 0] seq_wdp_dm;
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output wire [DWIDTH_RATIO - 1 : 0] seq_wdp_dqs;
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output wire seq_wdp_ovride;
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output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_dqs_add_2t_delay;
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output wire [ADV_LAT_WIDTH - 1 : 0] ctl_wlat;
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input wire [(DWIDTH_RATIO/2) * MEM_IF_ADDR_WIDTH - 1 : 0] ctl_addr;
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input wire [(DWIDTH_RATIO/2) * MEM_IF_BANKADDR_WIDTH - 1 : 0] ctl_ba;
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input wire [(DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 : 0] ctl_cke;
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input wire [(DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 : 0] ctl_cs_n;
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input wire [(DWIDTH_RATIO/2) - 1 : 0] ctl_cas_n;
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input wire [(DWIDTH_RATIO/2) - 1 : 0] ctl_ras_n;
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input wire [(DWIDTH_RATIO/2) - 1 : 0] ctl_we_n;
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input wire [(DWIDTH_RATIO/2) - 1 : 0] ctl_rst_n;
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output wire seq_mmc_start;
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input wire mmc_seq_done;
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input wire mmc_seq_value;
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input wire dbg_clk;
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input wire dbg_reset_n;
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input wire [DBG_A_WIDTH - 1 : 0] dbg_addr;
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input wire dbg_wr;
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input wire dbg_rd;
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input wire dbg_cs;
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input wire [ 31 : 0] dbg_wr_data;
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output wire [ 31 : 0] dbg_rd_data;
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output wire dbg_waitrequest;
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(* altera_attribute = "-name global_signal off" *) wire [MEM_IF_DQS_WIDTH - 1 : 0] sc_clk_dp;
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// instantiate the deskew (DDR3) or non-deskew (DDR/DDR2/DDR3) sequencer:
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//
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altera_ddr_phy_alt_mem_phy_seq #(
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.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
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| 244 |
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.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
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| 245 |
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.MEM_IF_DM_WIDTH (MEM_IF_DM_WIDTH),
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| 246 |
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.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
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| 247 |
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.DWIDTH_RATIO (DWIDTH_RATIO),
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| 248 |
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.CLOCK_INDEX_WIDTH (CLOCK_INDEX_WIDTH),
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| 249 |
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.MEM_IF_CLK_PAIR_COUNT (MEM_IF_CLK_PAIR_COUNT),
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| 250 |
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.MEM_IF_ADDR_WIDTH (MEM_IF_ADDR_WIDTH),
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| 251 |
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.MEM_IF_BANKADDR_WIDTH (MEM_IF_BANKADDR_WIDTH),
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| 252 |
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.MEM_IF_NUM_RANKS (MEM_IF_NUM_RANKS),
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| 253 |
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.MEM_IF_RANKS_PER_SLOT (MEM_IF_RANKS_PER_SLOT),
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| 254 |
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.ADV_LAT_WIDTH (ADV_LAT_WIDTH),
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| 255 |
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.RESYNCHRONISE_AVALON_DBG (RESYNCHRONISE_AVALON_DBG),
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| 256 |
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.AV_IF_ADDR_WIDTH (DBG_A_WIDTH),
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.NOM_DQS_PHASE_SETTING (DQS_PHASE_SETTING),
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.SCAN_CLK_DIVIDE_BY (SCAN_CLK_DIVIDE_BY),
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.RDP_ADDR_WIDTH (RDP_ADDR_WIDTH),
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.PLL_STEPS_PER_CYCLE (PLL_STEPS_PER_CYCLE),
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.IOE_PHASES_PER_TCK (IOE_PHASES_PER_TCK),
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.IOE_DELAYS_PER_PHS (IOE_DELAYS_PER_PHS),
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.MEM_IF_CLK_PS (MEM_IF_CLK_PS),
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| 264 |
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.PHY_DEF_MR_1ST (MEM_IF_MR_0),
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.PHY_DEF_MR_2ND (MEM_IF_MR_1),
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.PHY_DEF_MR_3RD (MEM_IF_MR_2),
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.PHY_DEF_MR_4TH (MEM_IF_MR_3),
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.MEM_IF_DQSN_EN (0),
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.MEM_IF_DQS_CAPTURE_EN (MEM_IF_DQS_CAPTURE_EN),
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.FAMILY (FAMILY),
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.FAMILYGROUP_ID (FAMILYGROUP_ID),
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.SPEED_GRADE (SPEED_GRADE),
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| 273 |
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.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
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| 274 |
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.WRITE_DESKEW_T10 (WRITE_DESKEW_T10),
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| 275 |
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.WRITE_DESKEW_T9NI (WRITE_DESKEW_T9NI),
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| 276 |
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.WRITE_DESKEW_T9I (WRITE_DESKEW_T9I),
|
| 277 |
|
|
.WRITE_DESKEW_RANGE (WRITE_DESKEW_RANGE),
|
| 278 |
|
|
.SINGLE_DQS_DELAY_CONTROL_CODE (SINGLE_DQS_DELAY_CONTROL_CODE),
|
| 279 |
|
|
.SNOOP_MRS (SNOOP_MRS),
|
| 280 |
|
|
.PRESET_RLAT (PRESET_RLAT),
|
| 281 |
|
|
.EN_OCT (MEM_IF_OCT_EN),
|
| 282 |
|
|
.SIM_TIME_REDUCTIONS (REDUCE_SIM_TIME),
|
| 283 |
|
|
.CAPABILITIES (CAPABILITIES),
|
| 284 |
|
|
.GENERATE_ADDITIONAL_DBG_RTL (GENERATE_ADDITIONAL_DBG_RTL),
|
| 285 |
|
|
.TINIT_TCK (TINIT_TCK),
|
| 286 |
|
|
.TINIT_RST (TINIT_RST),
|
| 287 |
|
|
.GENERATE_TRACKING_PHASE_STORE (0),
|
| 288 |
|
|
.OCT_LAT_WIDTH (OCT_LAT_WIDTH),
|
| 289 |
|
|
.IP_BUILDNUM (IP_BUILDNUM)
|
| 290 |
|
|
) seq_inst (
|
| 291 |
|
|
.clk (phy_clk_1x),
|
| 292 |
|
|
.rst_n (reset_phy_clk_1x_n),
|
| 293 |
|
|
.ctl_init_success (ctl_cal_success),
|
| 294 |
|
|
.ctl_init_fail (ctl_cal_fail),
|
| 295 |
|
|
.ctl_recalibrate_req (ctl_cal_req),
|
| 296 |
|
|
.MEM_AC_SWAPPED_RANKS (int_RANK_HAS_ADDR_SWAP),
|
| 297 |
|
|
.ctl_cal_byte_lanes (ctl_cal_byte_lane_sel_n),
|
| 298 |
|
|
.seq_pll_inc_dec_n (seq_pll_inc_dec_n),
|
| 299 |
|
|
.seq_pll_start_reconfig (seq_pll_start_reconfig),
|
| 300 |
|
|
.seq_pll_select (seq_pll_select),
|
| 301 |
|
|
.seq_pll_phs_shift_busy (phs_shft_busy),
|
| 302 |
|
|
.pll_resync_clk_index (pll_resync_clk_index),
|
| 303 |
|
|
.pll_measure_clk_index (pll_measure_clk_index),
|
| 304 |
|
|
.seq_scan_clk (sc_clk_dp),
|
| 305 |
|
|
.seq_scan_enable_dqs_config (scan_enable_dqs_config),
|
| 306 |
|
|
.seq_scan_update (scan_update),
|
| 307 |
|
|
.seq_scan_din (scan_din),
|
| 308 |
|
|
.seq_scan_enable_ck (scan_enable_ck),
|
| 309 |
|
|
.seq_scan_enable_dqs (scan_enable_dqs),
|
| 310 |
|
|
.seq_scan_enable_dqsn (scan_enable_dqsn),
|
| 311 |
|
|
.seq_scan_enable_dq (scan_enable_dq),
|
| 312 |
|
|
.seq_scan_enable_dm (scan_enable_dm),
|
| 313 |
|
|
.seq_scan_enable_d (scan_enable_d),
|
| 314 |
|
|
.hr_rsc_clk (hr_rsc_clk),
|
| 315 |
|
|
.seq_ac_addr (seq_ac_addr),
|
| 316 |
|
|
.seq_ac_ba (seq_ac_ba),
|
| 317 |
|
|
.seq_ac_cas_n (seq_ac_cas_n),
|
| 318 |
|
|
.seq_ac_ras_n (seq_ac_ras_n),
|
| 319 |
|
|
.seq_ac_we_n (seq_ac_we_n),
|
| 320 |
|
|
.seq_ac_cke (seq_ac_cke),
|
| 321 |
|
|
.seq_ac_cs_n (seq_ac_cs_n),
|
| 322 |
|
|
.seq_ac_odt (seq_ac_odt),
|
| 323 |
|
|
.seq_ac_rst_n (seq_ac_rst_n),
|
| 324 |
|
|
.seq_ac_sel (seq_ac_sel),
|
| 325 |
|
|
.seq_mem_clk_disable (seq_mem_clk_disable),
|
| 326 |
|
|
.seq_ac_add_1t_ac_lat_internal (ctl_add_1t_ac_lat_internal),
|
| 327 |
|
|
.seq_ac_add_1t_odt_lat_internal (ctl_add_1t_odt_lat_internal),
|
| 328 |
|
|
.seq_ac_add_2t (ctl_add_intermediate_regs_internal),
|
| 329 |
|
|
.seq_rdv_doing_rd (seq_rdv_doing_rd),
|
| 330 |
|
|
.seq_rdp_reset_req_n (seq_rdp_reset_req_n),
|
| 331 |
|
|
.seq_rdp_inc_read_lat_1x (seq_rdp_inc_read_lat_1x),
|
| 332 |
|
|
.seq_rdp_dec_read_lat_1x (seq_rdp_dec_read_lat_1x),
|
| 333 |
|
|
.rdata (ctl_rdata),
|
| 334 |
|
|
.rdata_valid (int_rdata_valid_1t),
|
| 335 |
|
|
.seq_rdata_valid_lat_inc (seq_rdata_valid_lat_inc),
|
| 336 |
|
|
.seq_rdata_valid_lat_dec (seq_rdata_valid_lat_dec),
|
| 337 |
|
|
.seq_ctl_rlat (ctl_rlat),
|
| 338 |
|
|
.seq_poa_lat_dec_1x (seq_poa_lat_dec_1x),
|
| 339 |
|
|
.seq_poa_lat_inc_1x (seq_poa_lat_inc_1x),
|
| 340 |
|
|
.seq_poa_protection_override_1x (seq_poa_protection_override_1x),
|
| 341 |
|
|
.seq_oct_oct_delay (seq_oct_oct_delay),
|
| 342 |
|
|
.seq_oct_oct_extend (seq_oct_oct_extend),
|
| 343 |
|
|
.seq_oct_value (seq_oct_val),
|
| 344 |
|
|
.seq_wdp_dqs_burst (seq_wdp_dqs_burst),
|
| 345 |
|
|
.seq_wdp_wdata_valid (seq_wdp_wdata_valid),
|
| 346 |
|
|
.seq_wdp_wdata (seq_wdp_wdata),
|
| 347 |
|
|
.seq_wdp_dm (seq_wdp_dm),
|
| 348 |
|
|
.seq_wdp_dqs (seq_wdp_dqs),
|
| 349 |
|
|
.seq_wdp_ovride (seq_wdp_ovride),
|
| 350 |
|
|
.seq_dqs_add_2t_delay (seq_dqs_add_2t_delay),
|
| 351 |
|
|
.seq_ctl_wlat (ctl_wlat),
|
| 352 |
|
|
.ctl_seq_ac_snoop_addr (ctl_addr),
|
| 353 |
|
|
.ctl_seq_ac_snoop_ba (ctl_ba),
|
| 354 |
|
|
.ctl_seq_ac_snoop_cke (ctl_cke),
|
| 355 |
|
|
.ctl_seq_ac_snoop_cs_n (ctl_cs_n),
|
| 356 |
|
|
.ctl_seq_ac_snoop_cas_n (ctl_cas_n),
|
| 357 |
|
|
.ctl_seq_ac_snoop_ras_n (ctl_ras_n),
|
| 358 |
|
|
.ctl_seq_ac_snoop_we_n (ctl_we_n),
|
| 359 |
|
|
.ctl_seq_ac_snoop_rst_n (ctl_rst_n),
|
| 360 |
|
|
.seq_mmc_start (seq_mmc_start),
|
| 361 |
|
|
.mmc_seq_done (mmc_seq_done),
|
| 362 |
|
|
.mmc_seq_value (mmc_seq_value),
|
| 363 |
|
|
.dbg_seq_clk (dbg_clk),
|
| 364 |
|
|
.dbg_seq_rst_n (dbg_reset_n),
|
| 365 |
|
|
.dbg_seq_addr (dbg_addr),
|
| 366 |
|
|
.dbg_seq_wr (dbg_wr),
|
| 367 |
|
|
.dbg_seq_rd (dbg_rd),
|
| 368 |
|
|
.dbg_seq_cs (dbg_cs),
|
| 369 |
|
|
.dbg_seq_wr_data (dbg_wr_data),
|
| 370 |
|
|
.seq_dbg_rd_data (dbg_rd_data),
|
| 371 |
|
|
.seq_dbg_waitrequest (dbg_waitrequest)
|
| 372 |
|
|
);
|
| 373 |
|
|
|
| 374 |
|
|
|
| 375 |
|
|
endmodule
|
| 376 |
|
|
|
