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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [altera_pll/] [altera_pll_waveforms.html] - Blame information for rev 12

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1 12 xianfeng 
<html>
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<title>Sample Waveforms for altera_pll.v </title>
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<h2><CENTER>Sample behavioral waveforms for design file altera_pll.v </CENTER></h2>
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<P>The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design altera_pll.v. The design altera_pll.v has Cyclone III AUTO pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 20000 ps. Output port LOCKED  will go high when the PLL locks to the input clock. </P>
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<CENTER><img src=altera_pll_wave0.jpg> </CENTER>
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<P><CENTER><FONT size=2>Fig. 1 : Wave showing NORMAL mode operation. </CENTER></P>
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<P><FONT size=3></P>
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<P></P>
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</html>

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