URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [altera_ram/] [altera_ram_inst.v] - Blame information for rev 12

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altera_ram      altera_ram_inst (
        .address ( address_sig ),
        .clock ( clock_sig ),
        .data ( data_sig ),
        .wren ( wren_sig ),
        .q ( q_sig )
        );

Line No.	Rev	Author	Line
1	12	xianfeng	`altera_ram altera_ram_inst (`
2			`.address ( address_sig ),`
3			`.clock ( clock_sig ),`
4			`.data ( data_sig ),`
5			`.wren ( wren_sig ),`
6			`.q ( q_sig )`
7			`);`

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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [altera_ram/] [altera_ram_inst.v] - Blame information for rev 12