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xianfeng |
// megafunction wizard: %RAM: 1-PORT%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altsyncram
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// ============================================================
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// File Name: altera_ram.v
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// Megafunction Name(s):
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// altsyncram
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 9.0 Build 235 06/17/2009 SP 2 SJ Full Version
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// ************************************************************
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//Copyright (C) 1991-2009 Altera Corporation
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
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//Subscription Agreement, Altera MegaCore Function License
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//Agreement, or other applicable license agreement, including,
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//without limitation, that your use is for the sole purpose of
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//programming logic devices manufactured by Altera and sold by
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//Altera or its authorized distributors. Please refer to the
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//applicable agreement for further details.
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//altsyncram CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" DEVICE_FAMILY="Cyclone III" ENABLE_RUNTIME_MOD="NO" INIT_FILE="./bootrom/boot.mif" NUMWORDS_A=16384 OPERATION_MODE="SINGLE_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" POWER_UP_UNINITIALIZED="FALSE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" WIDTH_A=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=14 address_a clock0 data_a q_a wren_a
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//VERSION_BEGIN 9.0SP2 cbx_altsyncram 2009:05:19:16:53:16:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2009:05:07:10:25:28:SJ cbx_lpm_compare 2009:02:03:01:43:16:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_lpm_mux 2009:03:31:01:01:28:SJ cbx_mgl 2009:02:26:16:06:21:SJ cbx_stratix 2008:09:18:16:08:35:SJ cbx_stratixii 2008:11:14:16:08:42:SJ cbx_stratixiii 2009:05:12:13:36:56:SJ cbx_util_mgl 2008:11:21:14:58:47:SJ VERSION_END
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// altera message_off 10463
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//lpm_decode DEVICE_FAMILY="Cyclone III" LPM_DECODES=2 LPM_WIDTH=1 data enable eq
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//VERSION_BEGIN 9.0SP2 cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2009:05:07:10:25:28:SJ cbx_lpm_compare 2009:02:03:01:43:16:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_mgl 2009:02:26:16:06:21:SJ cbx_stratix 2008:09:18:16:08:35:SJ cbx_stratixii 2008:11:14:16:08:42:SJ VERSION_END
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//synthesis_resources = lut 1
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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module altera_ram_decode
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(
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data,
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enable,
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eq) /* synthesis synthesis_clearbox=1 */;
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input [0:0] data;
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input enable;
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output [1:0] eq;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri0 [0:0] data;
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tri1 enable;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [1:0] eq_node;
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assign
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eq = eq_node,
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eq_node = {(data & enable), ((~ data) & enable)};
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endmodule //altera_ram_decode
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//lpm_decode DEVICE_FAMILY="Cyclone III" LPM_DECODES=2 LPM_WIDTH=1 data eq
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//VERSION_BEGIN 9.0SP2 cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2009:05:07:10:25:28:SJ cbx_lpm_compare 2009:02:03:01:43:16:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_mgl 2009:02:26:16:06:21:SJ cbx_stratix 2008:09:18:16:08:35:SJ cbx_stratixii 2008:11:14:16:08:42:SJ VERSION_END
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//synthesis_resources = lut 1
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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module altera_ram_decode1
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(
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data,
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eq) /* synthesis synthesis_clearbox=1 */;
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input [0:0] data;
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output [1:0] eq;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri0 [0:0] data;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire enable;
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wire [1:0] eq_node;
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assign
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enable = 1'b1,
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eq = eq_node,
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eq_node = {(data & enable), ((~ data) & enable)};
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endmodule //altera_ram_decode1
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//lpm_mux DEVICE_FAMILY="Cyclone III" LPM_SIZE=2 LPM_WIDTH=8 LPM_WIDTHS=1 data result sel
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//VERSION_BEGIN 9.0SP2 cbx_lpm_mux 2009:03:31:01:01:28:SJ cbx_mgl 2009:02:26:16:06:21:SJ VERSION_END
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//synthesis_resources = lut 8
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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module altera_ram_mux
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(
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data,
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result,
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sel) /* synthesis synthesis_clearbox=1 */;
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input [15:0] data;
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output [7:0] result;
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input [0:0] sel;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri0 [15:0] data;
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tri0 [0:0] sel;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [7:0] result_node;
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wire [0:0] sel_node;
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wire [1:0] w_data130w;
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wire [1:0] w_data144w;
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wire [1:0] w_data156w;
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wire [1:0] w_data168w;
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wire [1:0] w_data180w;
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wire [1:0] w_data192w;
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wire [1:0] w_data204w;
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wire [1:0] w_data216w;
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assign
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result = result_node,
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result_node = {((sel_node & w_data216w[1]) | ((~ sel_node) & w_data216w[0])), ((sel_node & w_data204w[1]) | ((~ sel_node) & w_data204w[0])), ((sel_node & w_data192w[1]) | ((~ sel_node) & w_data192w[0])), ((sel_node & w_data180w[1]) | ((~ sel_node) & w_data180w[0])), ((sel_node & w_data168w[1]) | ((~ sel_node) & w_data168w[0])), ((sel_node & w_data156w[1]) | ((~ sel_node) & w_data156w[0])), ((sel_node & w_data144w[1]) | ((~ sel_node) & w_data144w[0])), ((sel_node & w_data130w[1]) | ((~ sel_node) & w_data130w[0]))},
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sel_node = {sel[0]},
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w_data130w = {data[8], data[0]},
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w_data144w = {data[9], data[1]},
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w_data156w = {data[10], data[2]},
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w_data168w = {data[11], data[3]},
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w_data180w = {data[12], data[4]},
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w_data192w = {data[13], data[5]},
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w_data204w = {data[14], data[6]},
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w_data216w = {data[15], data[7]};
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endmodule //altera_ram_mux
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//synthesis_resources = lut 10 M9K 16 reg 2
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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(* ALTERA_ATTRIBUTE = {"OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"} *)
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module altera_ram_altsyncram
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(
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address_a,
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clock0,
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data_a,
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q_a,
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wren_a) /* synthesis synthesis_clearbox=1 */;
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input [13:0] address_a;
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input clock0;
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input [7:0] data_a;
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output [7:0] q_a;
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input wren_a;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri1 clock0;
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tri1 [7:0] data_a;
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tri0 wren_a;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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reg [0:0] address_reg_a;
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reg [0:0] out_address_reg_a;
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wire [1:0] wire_decode3_eq;
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wire [1:0] wire_rden_decode_eq;
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wire [7:0] wire_mux2_result;
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wire [0:0] wire_ram_block1a_0portadataout;
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wire [0:0] wire_ram_block1a_1portadataout;
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wire [0:0] wire_ram_block1a_2portadataout;
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wire [0:0] wire_ram_block1a_3portadataout;
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wire [0:0] wire_ram_block1a_4portadataout;
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wire [0:0] wire_ram_block1a_5portadataout;
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wire [0:0] wire_ram_block1a_6portadataout;
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wire [0:0] wire_ram_block1a_7portadataout;
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wire [0:0] wire_ram_block1a_8portadataout;
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wire [0:0] wire_ram_block1a_9portadataout;
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wire [0:0] wire_ram_block1a_10portadataout;
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wire [0:0] wire_ram_block1a_11portadataout;
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wire [0:0] wire_ram_block1a_12portadataout;
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wire [0:0] wire_ram_block1a_13portadataout;
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wire [0:0] wire_ram_block1a_14portadataout;
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wire [0:0] wire_ram_block1a_15portadataout;
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wire [0:0] address_a_sel;
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wire [13:0] address_a_wire;
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wire [0:0] rden_decode_addr_sel_a;
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// synopsys translate_off
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initial
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address_reg_a = 0;
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// synopsys translate_on
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always @ ( posedge clock0)
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address_reg_a <= address_a_sel;
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// synopsys translate_off
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initial
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out_address_reg_a = 0;
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// synopsys translate_on
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always @ ( posedge clock0)
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out_address_reg_a <= address_reg_a;
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altera_ram_decode decode3
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(
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.data(address_a_wire[13]),
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.enable(wren_a),
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.eq(wire_decode3_eq));
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altera_ram_decode1 rden_decode
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(
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.data(rden_decode_addr_sel_a),
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.eq(wire_rden_decode_eq));
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altera_ram_mux mux2
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(
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.data({wire_ram_block1a_15portadataout[0], wire_ram_block1a_14portadataout[0], wire_ram_block1a_13portadataout[0], wire_ram_block1a_12portadataout[0], wire_ram_block1a_11portadataout[0], wire_ram_block1a_10portadataout[0], wire_ram_block1a_9portadataout[0], wire_ram_block1a_8portadataout[0], wire_ram_block1a_7portadataout[0], wire_ram_block1a_6portadataout[0], wire_ram_block1a_5portadataout[0], wire_ram_block1a_4portadataout[0], wire_ram_block1a_3portadataout[0], wire_ram_block1a_2portadataout[0], wire_ram_block1a_1portadataout[0], wire_ram_block1a_0portadataout[0]}),
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.result(wire_mux2_result),
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.sel(out_address_reg_a));
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cycloneiii_ram_block ram_block1a_0
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(
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.clk0(clock0),
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.ena0(wire_rden_decode_eq[0]),
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.portaaddr({address_a_wire[12:0]}),
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.portadatain({data_a[0]}),
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.portadataout(wire_ram_block1a_0portadataout[0:0]),
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.portare(1'b1),
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.portawe(wire_decode3_eq[0]),
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.portbdataout()
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`ifndef FORMAL_VERIFICATION
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// synopsys translate_off
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`endif
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,
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.clk1(1'b0),
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.clr0(1'b0),
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.clr1(1'b0),
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.ena1(1'b1),
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.ena2(1'b1),
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.ena3(1'b1),
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.portaaddrstall(1'b0),
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.portabyteenamasks({1{1'b1}}),
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.portbaddr({1{1'b0}}),
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.portbaddrstall(1'b0),
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.portbbyteenamasks({1{1'b1}}),
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.portbdatain({1{1'b0}}),
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.portbre(1'b1),
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.portbwe(1'b0)
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`ifndef FORMAL_VERIFICATION
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// synopsys translate_on
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`endif
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// synopsys translate_off
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,
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.devclrn(1'b1),
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.devpor(1'b1)
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// synopsys translate_on
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);
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defparam
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ram_block1a_0.clk0_core_clock_enable = "ena0",
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ram_block1a_0.clk0_input_clock_enable = "none",
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ram_block1a_0.clk0_output_clock_enable = "none",
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ram_block1a_0.connectivity_checking = "OFF",
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ram_block1a_0.init_file = "./bootrom/boot.mif",
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ram_block1a_0.init_file_layout = "port_a",
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ram_block1a_0.logical_ram_name = "ALTSYNCRAM",
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|
|
ram_block1a_0.mem_init0 = 2048'h0000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100000000000000000000000104011111111000000001111111100000060001088000000000000000000000000000000000000000000000000014A6020326E5A94,
|
| 279 |
|
|
ram_block1a_0.mem_init1 = 2048'h020820000081F9080017E0076022222222222262022333238F1982B01F2A01F008B3A021200222222226202000226202EF3EC226202EF3EE822620332387070F11F80881D093222226203323170209F20182238222222620201F00280226004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000A71F228001F228001022000010A20A0A2AA8A02001033333332222222233333332222221022222222222222222222222222220231818100201026,
|
| 280 |
|
|
ram_block1a_0.mem_init2 = 2048'h013A321A88641195657832514A80001C5CD40207170CAA80000E2E6A280200E2E1A28000E2E24A54001C5CC8114EB75064A72F85CBA928C9D905A4A8AFF641492A2BFD905A4A8AFF641492A2BFD9050950AFF641696547886413E56C5203231F9FE08C31BC31BC31B431BC30B1B1BE01B1B601BE04313171B60102601313601360136013E013E013A013A013A0132013E0132013E0CB13A0132200082202222620222620233323132017BA6201FBA201B2008201B6010201B6010201B601020000000801090013600820000224000021022222226203322223332317601F17E0079787171E0188F08CF180970188F0811800828FF0A000282201F0B002820000,
|
| 281 |
|
|
ram_block1a_0.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 282 |
|
|
ram_block1a_0.operation_mode = "single_port",
|
| 283 |
|
|
ram_block1a_0.port_a_address_width = 13,
|
| 284 |
|
|
ram_block1a_0.port_a_byte_enable_mask_width = 1,
|
| 285 |
|
|
ram_block1a_0.port_a_byte_size = 1,
|
| 286 |
|
|
ram_block1a_0.port_a_data_out_clear = "none",
|
| 287 |
|
|
ram_block1a_0.port_a_data_out_clock = "clock0",
|
| 288 |
|
|
ram_block1a_0.port_a_data_width = 1,
|
| 289 |
|
|
ram_block1a_0.port_a_first_address = 0,
|
| 290 |
|
|
ram_block1a_0.port_a_first_bit_number = 0,
|
| 291 |
|
|
ram_block1a_0.port_a_last_address = 8191,
|
| 292 |
|
|
ram_block1a_0.port_a_logical_ram_depth = 16384,
|
| 293 |
|
|
ram_block1a_0.port_a_logical_ram_width = 8,
|
| 294 |
|
|
ram_block1a_0.port_a_read_during_write_mode = "new_data_no_nbe_read",
|
| 295 |
|
|
ram_block1a_0.power_up_uninitialized = "false",
|
| 296 |
|
|
ram_block1a_0.ram_block_type = "AUTO",
|
| 297 |
|
|
ram_block1a_0.lpm_type = "cycloneiii_ram_block";
|
| 298 |
|
|
cycloneiii_ram_block ram_block1a_1
|
| 299 |
|
|
(
|
| 300 |
|
|
.clk0(clock0),
|
| 301 |
|
|
.ena0(wire_rden_decode_eq[0]),
|
| 302 |
|
|
.portaaddr({address_a_wire[12:0]}),
|
| 303 |
|
|
.portadatain({data_a[1]}),
|
| 304 |
|
|
.portadataout(wire_ram_block1a_1portadataout[0:0]),
|
| 305 |
|
|
.portare(1'b1),
|
| 306 |
|
|
.portawe(wire_decode3_eq[0]),
|
| 307 |
|
|
.portbdataout()
|
| 308 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 309 |
|
|
// synopsys translate_off
|
| 310 |
|
|
`endif
|
| 311 |
|
|
,
|
| 312 |
|
|
.clk1(1'b0),
|
| 313 |
|
|
.clr0(1'b0),
|
| 314 |
|
|
.clr1(1'b0),
|
| 315 |
|
|
.ena1(1'b1),
|
| 316 |
|
|
.ena2(1'b1),
|
| 317 |
|
|
.ena3(1'b1),
|
| 318 |
|
|
.portaaddrstall(1'b0),
|
| 319 |
|
|
.portabyteenamasks({1{1'b1}}),
|
| 320 |
|
|
.portbaddr({1{1'b0}}),
|
| 321 |
|
|
.portbaddrstall(1'b0),
|
| 322 |
|
|
.portbbyteenamasks({1{1'b1}}),
|
| 323 |
|
|
.portbdatain({1{1'b0}}),
|
| 324 |
|
|
.portbre(1'b1),
|
| 325 |
|
|
.portbwe(1'b0)
|
| 326 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 327 |
|
|
// synopsys translate_on
|
| 328 |
|
|
`endif
|
| 329 |
|
|
// synopsys translate_off
|
| 330 |
|
|
,
|
| 331 |
|
|
.devclrn(1'b1),
|
| 332 |
|
|
.devpor(1'b1)
|
| 333 |
|
|
// synopsys translate_on
|
| 334 |
|
|
);
|
| 335 |
|
|
defparam
|
| 336 |
|
|
ram_block1a_1.clk0_core_clock_enable = "ena0",
|
| 337 |
|
|
ram_block1a_1.clk0_input_clock_enable = "none",
|
| 338 |
|
|
ram_block1a_1.clk0_output_clock_enable = "none",
|
| 339 |
|
|
ram_block1a_1.connectivity_checking = "OFF",
|
| 340 |
|
|
ram_block1a_1.init_file = "./bootrom/boot.mif",
|
| 341 |
|
|
ram_block1a_1.init_file_layout = "port_a",
|
| 342 |
|
|
ram_block1a_1.logical_ram_name = "ALTSYNCRAM",
|
| 343 |
|
|
ram_block1a_1.mem_init0 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006011111111111111110000000000000000000C0000000000000000000000000000000000000000000000000001AD8010140D3900,
|
| 344 |
|
|
ram_block1a_1.mem_init1 = 2048'h802002002081F119300F201F200000000000004001100000070002A2072220F02022B0B0200000000004000000004000EF2EC004000EF2EA8004000000078F2F00F80802C2820000040000000F0202F200822282000004000207000200040020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002F070000007000000822000000A2020A0AA820A000011111111111111100000000000000000000000000000000000000000000000804080200804,
|
| 345 |
|
|
ram_block1a_1.mem_init2 = 2048'h00C4130A40951048123152263C00403A0A32000E82949900001D0549900201D052110021D05181B0003A0A2A2C5E852248195389B214D88045429F012B6150A7C04AD85421F012B615087C04AD85427E01AB615098662FA79511058C9000000F2F20ACF07CF074F07CF07CF870F0F600707E00720CF0F0F0F60002E00F0F600F600F600FE00FE00FE00FE00FE00F600F200F600F20CF07E0070E000822000004000004001000000F6007A222007A2200FE008200F2008A20FA008220F2008A0000282908008007A008A000800800086040000000400111111000000F200707202727176F020088701DF002278008F0160828028F800222282200702222000808,
|
| 346 |
|
|
ram_block1a_1.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 347 |
|
|
ram_block1a_1.operation_mode = "single_port",
|
| 348 |
|
|
ram_block1a_1.port_a_address_width = 13,
|
| 349 |
|
|
ram_block1a_1.port_a_byte_enable_mask_width = 1,
|
| 350 |
|
|
ram_block1a_1.port_a_byte_size = 1,
|
| 351 |
|
|
ram_block1a_1.port_a_data_out_clear = "none",
|
| 352 |
|
|
ram_block1a_1.port_a_data_out_clock = "clock0",
|
| 353 |
|
|
ram_block1a_1.port_a_data_width = 1,
|
| 354 |
|
|
ram_block1a_1.port_a_first_address = 0,
|
| 355 |
|
|
ram_block1a_1.port_a_first_bit_number = 1,
|
| 356 |
|
|
ram_block1a_1.port_a_last_address = 8191,
|
| 357 |
|
|
ram_block1a_1.port_a_logical_ram_depth = 16384,
|
| 358 |
|
|
ram_block1a_1.port_a_logical_ram_width = 8,
|
| 359 |
|
|
ram_block1a_1.port_a_read_during_write_mode = "new_data_no_nbe_read",
|
| 360 |
|
|
ram_block1a_1.power_up_uninitialized = "false",
|
| 361 |
|
|
ram_block1a_1.ram_block_type = "AUTO",
|
| 362 |
|
|
ram_block1a_1.lpm_type = "cycloneiii_ram_block";
|
| 363 |
|
|
cycloneiii_ram_block ram_block1a_2
|
| 364 |
|
|
(
|
| 365 |
|
|
.clk0(clock0),
|
| 366 |
|
|
.ena0(wire_rden_decode_eq[0]),
|
| 367 |
|
|
.portaaddr({address_a_wire[12:0]}),
|
| 368 |
|
|
.portadatain({data_a[2]}),
|
| 369 |
|
|
.portadataout(wire_ram_block1a_2portadataout[0:0]),
|
| 370 |
|
|
.portare(1'b1),
|
| 371 |
|
|
.portawe(wire_decode3_eq[0]),
|
| 372 |
|
|
.portbdataout()
|
| 373 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 374 |
|
|
// synopsys translate_off
|
| 375 |
|
|
`endif
|
| 376 |
|
|
,
|
| 377 |
|
|
.clk1(1'b0),
|
| 378 |
|
|
.clr0(1'b0),
|
| 379 |
|
|
.clr1(1'b0),
|
| 380 |
|
|
.ena1(1'b1),
|
| 381 |
|
|
.ena2(1'b1),
|
| 382 |
|
|
.ena3(1'b1),
|
| 383 |
|
|
.portaaddrstall(1'b0),
|
| 384 |
|
|
.portabyteenamasks({1{1'b1}}),
|
| 385 |
|
|
.portbaddr({1{1'b0}}),
|
| 386 |
|
|
.portbaddrstall(1'b0),
|
| 387 |
|
|
.portbbyteenamasks({1{1'b1}}),
|
| 388 |
|
|
.portbdatain({1{1'b0}}),
|
| 389 |
|
|
.portbre(1'b1),
|
| 390 |
|
|
.portbwe(1'b0)
|
| 391 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 392 |
|
|
// synopsys translate_on
|
| 393 |
|
|
`endif
|
| 394 |
|
|
// synopsys translate_off
|
| 395 |
|
|
,
|
| 396 |
|
|
.devclrn(1'b1),
|
| 397 |
|
|
.devpor(1'b1)
|
| 398 |
|
|
// synopsys translate_on
|
| 399 |
|
|
);
|
| 400 |
|
|
defparam
|
| 401 |
|
|
ram_block1a_2.clk0_core_clock_enable = "ena0",
|
| 402 |
|
|
ram_block1a_2.clk0_input_clock_enable = "none",
|
| 403 |
|
|
ram_block1a_2.clk0_output_clock_enable = "none",
|
| 404 |
|
|
ram_block1a_2.connectivity_checking = "OFF",
|
| 405 |
|
|
ram_block1a_2.init_file = "./bootrom/boot.mif",
|
| 406 |
|
|
ram_block1a_2.init_file_layout = "port_a",
|
| 407 |
|
|
ram_block1a_2.logical_ram_name = "ALTSYNCRAM",
|
| 408 |
|
|
ram_block1a_2.mem_init0 = 2048'h000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000000000000000011008888888888888888888888888888884000110000000000000000000000000000000000000000000000000001CF8000470540E4,
|
| 409 |
|
|
ram_block1a_2.mem_init1 = 2048'h0200200201807880011FC007C0191919191199D91191919117B391131F1111700188020181019191199D9113A091D911DE1D991D911DE1DC091D11919197178E31FB3138F890911195119191173121712101109191119591121F333A091D1100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001119191E1F33B121F33B1010319191110010102101010101119191919191919191919119191911119191919191919191919119191911191111113911995,
|
| 410 |
|
|
ram_block1a_2.mem_init2 = 2048'h010A77788048D99394C084A14480400590840201642120002002C84A0000002C84A800002C875A4400059091910338409B042D001B897D6D123404A404848D0129012123404A404848D01290121234094A84848D3C4940CBC8DB4989211191161EC09D71F5F17D71FDF17D79F1F1F40171FC017C0DF1F1F17C0191401F1FC017401FC017C01F4017C01F4017C01F4017C01F4017C0DF17C01F3401390801119591191D1191919117C01F910111F9102174028111740189317C0189117C01813301290999291917409813321335393141891911195911919191919117401627C0B63736171C0108F33FF19B3F1108733119B911B7B23300081911F31120128120,
|
| 411 |
|
|
ram_block1a_2.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 412 |
|
|
ram_block1a_2.operation_mode = "single_port",
|
| 413 |
|
|
ram_block1a_2.port_a_address_width = 13,
|
| 414 |
|
|
ram_block1a_2.port_a_byte_enable_mask_width = 1,
|
| 415 |
|
|
ram_block1a_2.port_a_byte_size = 1,
|
| 416 |
|
|
ram_block1a_2.port_a_data_out_clear = "none",
|
| 417 |
|
|
ram_block1a_2.port_a_data_out_clock = "clock0",
|
| 418 |
|
|
ram_block1a_2.port_a_data_width = 1,
|
| 419 |
|
|
ram_block1a_2.port_a_first_address = 0,
|
| 420 |
|
|
ram_block1a_2.port_a_first_bit_number = 2,
|
| 421 |
|
|
ram_block1a_2.port_a_last_address = 8191,
|
| 422 |
|
|
ram_block1a_2.port_a_logical_ram_depth = 16384,
|
| 423 |
|
|
ram_block1a_2.port_a_logical_ram_width = 8,
|
| 424 |
|
|
ram_block1a_2.port_a_read_during_write_mode = "new_data_no_nbe_read",
|
| 425 |
|
|
ram_block1a_2.power_up_uninitialized = "false",
|
| 426 |
|
|
ram_block1a_2.ram_block_type = "AUTO",
|
| 427 |
|
|
ram_block1a_2.lpm_type = "cycloneiii_ram_block";
|
| 428 |
|
|
cycloneiii_ram_block ram_block1a_3
|
| 429 |
|
|
(
|
| 430 |
|
|
.clk0(clock0),
|
| 431 |
|
|
.ena0(wire_rden_decode_eq[0]),
|
| 432 |
|
|
.portaaddr({address_a_wire[12:0]}),
|
| 433 |
|
|
.portadatain({data_a[3]}),
|
| 434 |
|
|
.portadataout(wire_ram_block1a_3portadataout[0:0]),
|
| 435 |
|
|
.portare(1'b1),
|
| 436 |
|
|
.portawe(wire_decode3_eq[0]),
|
| 437 |
|
|
.portbdataout()
|
| 438 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 439 |
|
|
// synopsys translate_off
|
| 440 |
|
|
`endif
|
| 441 |
|
|
,
|
| 442 |
|
|
.clk1(1'b0),
|
| 443 |
|
|
.clr0(1'b0),
|
| 444 |
|
|
.clr1(1'b0),
|
| 445 |
|
|
.ena1(1'b1),
|
| 446 |
|
|
.ena2(1'b1),
|
| 447 |
|
|
.ena3(1'b1),
|
| 448 |
|
|
.portaaddrstall(1'b0),
|
| 449 |
|
|
.portabyteenamasks({1{1'b1}}),
|
| 450 |
|
|
.portbaddr({1{1'b0}}),
|
| 451 |
|
|
.portbaddrstall(1'b0),
|
| 452 |
|
|
.portbbyteenamasks({1{1'b1}}),
|
| 453 |
|
|
.portbdatain({1{1'b0}}),
|
| 454 |
|
|
.portbre(1'b1),
|
| 455 |
|
|
.portbwe(1'b0)
|
| 456 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 457 |
|
|
// synopsys translate_on
|
| 458 |
|
|
`endif
|
| 459 |
|
|
// synopsys translate_off
|
| 460 |
|
|
,
|
| 461 |
|
|
.devclrn(1'b1),
|
| 462 |
|
|
.devpor(1'b1)
|
| 463 |
|
|
// synopsys translate_on
|
| 464 |
|
|
);
|
| 465 |
|
|
defparam
|
| 466 |
|
|
ram_block1a_3.clk0_core_clock_enable = "ena0",
|
| 467 |
|
|
ram_block1a_3.clk0_input_clock_enable = "none",
|
| 468 |
|
|
ram_block1a_3.clk0_output_clock_enable = "none",
|
| 469 |
|
|
ram_block1a_3.connectivity_checking = "OFF",
|
| 470 |
|
|
ram_block1a_3.init_file = "./bootrom/boot.mif",
|
| 471 |
|
|
ram_block1a_3.init_file_layout = "port_a",
|
| 472 |
|
|
ram_block1a_3.logical_ram_name = "ALTSYNCRAM",
|
| 473 |
|
|
ram_block1a_3.mem_init0 = 2048'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110000000000000000000000000000001111084100000000000000000000000000000000000000000000000000A4B00030670024,
|
| 474 |
|
|
ram_block1a_3.mem_init1 = 2048'h91B95395B111E1113116111E918008800884905948008800173313030F1030E55111151111180088490514041110D140DE1D110D140DE1DD110D1488009696B630611193FB118841051488000F1123613181119188410514050F1011110D1011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400881E0F001150F001110001C84004511111111111111040880088008800880088008008800040C840C840C840C840C840840C84009800000110008CD,
|
| 475 |
|
|
ram_block1a_3.mem_init2 = 2048'h01C1032CC4C01158C601007768802020008601080000308010100063080101000030801100012344012000803F1B2270AA027D0053BDD80510061408400401850210010061408400401850210010062810C0040199436ACFC01060E809480016369135E06DE0ED60ED606DE9E060E110606110E91DE0606069101311060E11061106110E910E11061106910E910E91069106110E91DE0611060111499918490D14010D9400880006110F911110F9153069130910E110013061100130E91001105971711151110611109115905921699110088490D94800880088000E110E3691363E1E3E191001711DE0133E100171130139118F951163101830F30155111151,
|
| 476 |
|
|
ram_block1a_3.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 477 |
|
|
ram_block1a_3.operation_mode = "single_port",
|
| 478 |
|
|
ram_block1a_3.port_a_address_width = 13,
|
| 479 |
|
|
ram_block1a_3.port_a_byte_enable_mask_width = 1,
|
| 480 |
|
|
ram_block1a_3.port_a_byte_size = 1,
|
| 481 |
|
|
ram_block1a_3.port_a_data_out_clear = "none",
|
| 482 |
|
|
ram_block1a_3.port_a_data_out_clock = "clock0",
|
| 483 |
|
|
ram_block1a_3.port_a_data_width = 1,
|
| 484 |
|
|
ram_block1a_3.port_a_first_address = 0,
|
| 485 |
|
|
ram_block1a_3.port_a_first_bit_number = 3,
|
| 486 |
|
|
ram_block1a_3.port_a_last_address = 8191,
|
| 487 |
|
|
ram_block1a_3.port_a_logical_ram_depth = 16384,
|
| 488 |
|
|
ram_block1a_3.port_a_logical_ram_width = 8,
|
| 489 |
|
|
ram_block1a_3.port_a_read_during_write_mode = "new_data_no_nbe_read",
|
| 490 |
|
|
ram_block1a_3.power_up_uninitialized = "false",
|
| 491 |
|
|
ram_block1a_3.ram_block_type = "AUTO",
|
| 492 |
|
|
ram_block1a_3.lpm_type = "cycloneiii_ram_block";
|
| 493 |
|
|
cycloneiii_ram_block ram_block1a_4
|
| 494 |
|
|
(
|
| 495 |
|
|
.clk0(clock0),
|
| 496 |
|
|
.ena0(wire_rden_decode_eq[0]),
|
| 497 |
|
|
.portaaddr({address_a_wire[12:0]}),
|
| 498 |
|
|
.portadatain({data_a[4]}),
|
| 499 |
|
|
.portadataout(wire_ram_block1a_4portadataout[0:0]),
|
| 500 |
|
|
.portare(1'b1),
|
| 501 |
|
|
.portawe(wire_decode3_eq[0]),
|
| 502 |
|
|
.portbdataout()
|
| 503 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 504 |
|
|
// synopsys translate_off
|
| 505 |
|
|
`endif
|
| 506 |
|
|
,
|
| 507 |
|
|
.clk1(1'b0),
|
| 508 |
|
|
.clr0(1'b0),
|
| 509 |
|
|
.clr1(1'b0),
|
| 510 |
|
|
.ena1(1'b1),
|
| 511 |
|
|
.ena2(1'b1),
|
| 512 |
|
|
.ena3(1'b1),
|
| 513 |
|
|
.portaaddrstall(1'b0),
|
| 514 |
|
|
.portabyteenamasks({1{1'b1}}),
|
| 515 |
|
|
.portbaddr({1{1'b0}}),
|
| 516 |
|
|
.portbaddrstall(1'b0),
|
| 517 |
|
|
.portbbyteenamasks({1{1'b1}}),
|
| 518 |
|
|
.portbdatain({1{1'b0}}),
|
| 519 |
|
|
.portbre(1'b1),
|
| 520 |
|
|
.portbwe(1'b0)
|
| 521 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 522 |
|
|
// synopsys translate_on
|
| 523 |
|
|
`endif
|
| 524 |
|
|
// synopsys translate_off
|
| 525 |
|
|
,
|
| 526 |
|
|
.devclrn(1'b1),
|
| 527 |
|
|
.devpor(1'b1)
|
| 528 |
|
|
// synopsys translate_on
|
| 529 |
|
|
);
|
| 530 |
|
|
defparam
|
| 531 |
|
|
ram_block1a_4.clk0_core_clock_enable = "ena0",
|
| 532 |
|
|
ram_block1a_4.clk0_input_clock_enable = "none",
|
| 533 |
|
|
ram_block1a_4.clk0_output_clock_enable = "none",
|
| 534 |
|
|
ram_block1a_4.connectivity_checking = "OFF",
|
| 535 |
|
|
ram_block1a_4.init_file = "./bootrom/boot.mif",
|
| 536 |
|
|
ram_block1a_4.init_file_layout = "port_a",
|
| 537 |
|
|
ram_block1a_4.logical_ram_name = "ALTSYNCRAM",
|
| 538 |
|
|
ram_block1a_4.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000000000000000000000001445000000000000000000000000000000450110C00000000000000000000000000000000000000000000000000020103044086941,
|
| 539 |
|
|
ram_block1a_4.mem_init1 = 2048'h21925921112AE22205164556C55159D9D15115D9088800001E1101001E10016771000101095D9D15195510050115D100DF1D115D100DF1D8115D90000016169F11699011D91015195D9000001E1041600111000115195D10051E1000515D140100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000161E400151E40015190055111011911100111111510800008888000088880000888000010D115599DD115599DD11559DD11550981018101011095,
|
| 540 |
|
|
ram_block1a_4.mem_init2 = 2048'h004444123E950A8000354280063FB03A0831FF8E82108B1FF81D0410B1FF81D0468B1FF9D0449031FFBA082A04D00F1E11190CBCA58001A24540FB1D0B01503EC742C0540FB1D0B01503EC742C0540F63B2B015001840C0015080431B900001617451D61ED61EDE1EDE16DE1E161645161E451E45D6161616C5101C51616451E451EC51E451E4516C5164516C516451E451EC51E45D616C5161C51590015195510015D9088000016C51E911011E91501E4501921E45119016C51190164511900795951915191164511900591550951C1D9D151955100008888000016C5160E459616361E145182673FE1891E9102E731189101AE951002091021E1023111A152,
|
| 541 |
|
|
ram_block1a_4.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 542 |
|
|
ram_block1a_4.operation_mode = "single_port",
|
| 543 |
|
|
ram_block1a_4.port_a_address_width = 13,
|
| 544 |
|
|
ram_block1a_4.port_a_byte_enable_mask_width = 1,
|
| 545 |
|
|
ram_block1a_4.port_a_byte_size = 1,
|
| 546 |
|
|
ram_block1a_4.port_a_data_out_clear = "none",
|
| 547 |
|
|
ram_block1a_4.port_a_data_out_clock = "clock0",
|
| 548 |
|
|
ram_block1a_4.port_a_data_width = 1,
|
| 549 |
|
|
ram_block1a_4.port_a_first_address = 0,
|
| 550 |
|
|
ram_block1a_4.port_a_first_bit_number = 4,
|
| 551 |
|
|
ram_block1a_4.port_a_last_address = 8191,
|
| 552 |
|
|
ram_block1a_4.port_a_logical_ram_depth = 16384,
|
| 553 |
|
|
ram_block1a_4.port_a_logical_ram_width = 8,
|
| 554 |
|
|
ram_block1a_4.port_a_read_during_write_mode = "new_data_no_nbe_read",
|
| 555 |
|
|
ram_block1a_4.power_up_uninitialized = "false",
|
| 556 |
|
|
ram_block1a_4.ram_block_type = "AUTO",
|
| 557 |
|
|
ram_block1a_4.lpm_type = "cycloneiii_ram_block";
|
| 558 |
|
|
cycloneiii_ram_block ram_block1a_5
|
| 559 |
|
|
(
|
| 560 |
|
|
.clk0(clock0),
|
| 561 |
|
|
.ena0(wire_rden_decode_eq[0]),
|
| 562 |
|
|
.portaaddr({address_a_wire[12:0]}),
|
| 563 |
|
|
.portadatain({data_a[5]}),
|
| 564 |
|
|
.portadataout(wire_ram_block1a_5portadataout[0:0]),
|
| 565 |
|
|
.portare(1'b1),
|
| 566 |
|
|
.portawe(wire_decode3_eq[0]),
|
| 567 |
|
|
.portbdataout()
|
| 568 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 569 |
|
|
// synopsys translate_off
|
| 570 |
|
|
`endif
|
| 571 |
|
|
,
|
| 572 |
|
|
.clk1(1'b0),
|
| 573 |
|
|
.clr0(1'b0),
|
| 574 |
|
|
.clr1(1'b0),
|
| 575 |
|
|
.ena1(1'b1),
|
| 576 |
|
|
.ena2(1'b1),
|
| 577 |
|
|
.ena3(1'b1),
|
| 578 |
|
|
.portaaddrstall(1'b0),
|
| 579 |
|
|
.portabyteenamasks({1{1'b1}}),
|
| 580 |
|
|
.portbaddr({1{1'b0}}),
|
| 581 |
|
|
.portbaddrstall(1'b0),
|
| 582 |
|
|
.portbbyteenamasks({1{1'b1}}),
|
| 583 |
|
|
.portbdatain({1{1'b0}}),
|
| 584 |
|
|
.portbre(1'b1),
|
| 585 |
|
|
.portbwe(1'b0)
|
| 586 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 587 |
|
|
// synopsys translate_on
|
| 588 |
|
|
`endif
|
| 589 |
|
|
// synopsys translate_off
|
| 590 |
|
|
,
|
| 591 |
|
|
.devclrn(1'b1),
|
| 592 |
|
|
.devpor(1'b1)
|
| 593 |
|
|
// synopsys translate_on
|
| 594 |
|
|
);
|
| 595 |
|
|
defparam
|
| 596 |
|
|
ram_block1a_5.clk0_core_clock_enable = "ena0",
|
| 597 |
|
|
ram_block1a_5.clk0_input_clock_enable = "none",
|
| 598 |
|
|
ram_block1a_5.clk0_output_clock_enable = "none",
|
| 599 |
|
|
ram_block1a_5.connectivity_checking = "OFF",
|
| 600 |
|
|
ram_block1a_5.init_file = "./bootrom/boot.mif",
|
| 601 |
|
|
ram_block1a_5.init_file_layout = "port_a",
|
| 602 |
|
|
ram_block1a_5.logical_ram_name = "ALTSYNCRAM",
|
| 603 |
|
|
ram_block1a_5.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000014313131313131313131313131313131F61000030000000000000000000000000000000000000000000000000FDFEFEFEE90EC01,
|
| 604 |
|
|
ram_block1a_5.mem_init1 = 2048'h143301343211E111120E360E3688C40044008062000000022E1003320E1320600211141092200440000E20001000E200EE3EA00E200EE3EB200E20000226261E306AA011C10140000E2000020E1030E23001210340000E20000E3903400E001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008A8A2E0E5B2840E5B2840012CCCC00440404124040406008A8A820202020A8A8A8A8020202000CCC880044440088CCCC8804444001A20808001130006,
|
| 605 |
|
|
ram_block1a_5.mem_init2 = 2048'h007FFFFC3F823F87E1F9E9E007FFBFFFBD01FFFFEF7A0C7FFFFFDE80C7FFFFFDE80C7FFFFDEFF03FFFFFBD0404FF7E1FFF7E0C7FDD807FFFE081FF7FFFF8207FDFFFFE081FF7FFFF8207FDFFFFE081FEFFFFF8207BD00FC3823FF3FFE200020E0E36BEE06EE06EE06EE0EEEA60E0EB60E0E360E36E6060606B6003B60E06B606B606B6063606B60EB60E360E360E360E360EB60E36E606360643600A1320000E20000E200000020EB60E926020E92030E3630920EB6001206B600920636001220A0208A808280EB6801220220A2002B0A0440000EA08880000000206360E16363E060E06036001630CE0030620816300003A83BE902251303320E11244243003,
|
| 606 |
|
|
ram_block1a_5.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 607 |
|
|
ram_block1a_5.operation_mode = "single_port",
|
| 608 |
|
|
ram_block1a_5.port_a_address_width = 13,
|
| 609 |
|
|
ram_block1a_5.port_a_byte_enable_mask_width = 1,
|
| 610 |
|
|
ram_block1a_5.port_a_byte_size = 1,
|
| 611 |
|
|
ram_block1a_5.port_a_data_out_clear = "none",
|
| 612 |
|
|
ram_block1a_5.port_a_data_out_clock = "clock0",
|
| 613 |
|
|
ram_block1a_5.port_a_data_width = 1,
|
| 614 |
|
|
ram_block1a_5.port_a_first_address = 0,
|
| 615 |
|
|
ram_block1a_5.port_a_first_bit_number = 5,
|
| 616 |
|
|
ram_block1a_5.port_a_last_address = 8191,
|
| 617 |
|
|
ram_block1a_5.port_a_logical_ram_depth = 16384,
|
| 618 |
|
|
ram_block1a_5.port_a_logical_ram_width = 8,
|
| 619 |
|
|
ram_block1a_5.port_a_read_during_write_mode = "new_data_no_nbe_read",
|
| 620 |
|
|
ram_block1a_5.power_up_uninitialized = "false",
|
| 621 |
|
|
ram_block1a_5.ram_block_type = "AUTO",
|
| 622 |
|
|
ram_block1a_5.lpm_type = "cycloneiii_ram_block";
|
| 623 |
|
|
cycloneiii_ram_block ram_block1a_6
|
| 624 |
|
|
(
|
| 625 |
|
|
.clk0(clock0),
|
| 626 |
|
|
.ena0(wire_rden_decode_eq[0]),
|
| 627 |
|
|
.portaaddr({address_a_wire[12:0]}),
|
| 628 |
|
|
.portadatain({data_a[6]}),
|
| 629 |
|
|
.portadataout(wire_ram_block1a_6portadataout[0:0]),
|
| 630 |
|
|
.portare(1'b1),
|
| 631 |
|
|
.portawe(wire_decode3_eq[0]),
|
| 632 |
|
|
.portbdataout()
|
| 633 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 634 |
|
|
// synopsys translate_off
|
| 635 |
|
|
`endif
|
| 636 |
|
|
,
|
| 637 |
|
|
.clk1(1'b0),
|
| 638 |
|
|
.clr0(1'b0),
|
| 639 |
|
|
.clr1(1'b0),
|
| 640 |
|
|
.ena1(1'b1),
|
| 641 |
|
|
.ena2(1'b1),
|
| 642 |
|
|
.ena3(1'b1),
|
| 643 |
|
|
.portaaddrstall(1'b0),
|
| 644 |
|
|
.portabyteenamasks({1{1'b1}}),
|
| 645 |
|
|
.portbaddr({1{1'b0}}),
|
| 646 |
|
|
.portbaddrstall(1'b0),
|
| 647 |
|
|
.portbbyteenamasks({1{1'b1}}),
|
| 648 |
|
|
.portbdatain({1{1'b0}}),
|
| 649 |
|
|
.portbre(1'b1),
|
| 650 |
|
|
.portbwe(1'b0)
|
| 651 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 652 |
|
|
// synopsys translate_on
|
| 653 |
|
|
`endif
|
| 654 |
|
|
// synopsys translate_off
|
| 655 |
|
|
,
|
| 656 |
|
|
.devclrn(1'b1),
|
| 657 |
|
|
.devpor(1'b1)
|
| 658 |
|
|
// synopsys translate_on
|
| 659 |
|
|
);
|
| 660 |
|
|
defparam
|
| 661 |
|
|
ram_block1a_6.clk0_core_clock_enable = "ena0",
|
| 662 |
|
|
ram_block1a_6.clk0_input_clock_enable = "none",
|
| 663 |
|
|
ram_block1a_6.clk0_output_clock_enable = "none",
|
| 664 |
|
|
ram_block1a_6.connectivity_checking = "OFF",
|
| 665 |
|
|
ram_block1a_6.init_file = "./bootrom/boot.mif",
|
| 666 |
|
|
ram_block1a_6.init_file_layout = "port_a",
|
| 667 |
|
|
ram_block1a_6.logical_ram_name = "ALTSYNCRAM",
|
| 668 |
|
|
ram_block1a_6.mem_init0 = 2048'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001263311331133113311331133113311338400001200000000000000000000000000000000000000000000000001EFF010776F13F1,
|
| 669 |
|
|
ram_block1a_6.mem_init1 = 2048'h01A01801A002E022062EA64E26551111555521C0520202202E2000220E0220E11222012000611555521C05210421C052EE2EA21C052EE2E2221C0502202E2E8E20E22022C80255521C0502200E0072E22200200055521C05210E0000221C2122000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000500222E0E180A10E10020001211110511010100101018205A88AA88AA88AA00220022022002205DDDDDDD99999911555555511111108000000000A0054,
|
| 670 |
|
|
ram_block1a_6.mem_init2 = 2048'h000F777E047DDBC3F0FCF6F01800601FDEF00107F7BD8380100FEF78380100FEF7838010FEF7F8C0011FDEFB870FBF007FBF0381FE003DEFDF700FBDEFF7DC03EF7BFDF700FBDEFF7DC03EF7BFDF701F7BEFF7DC3DEC07E07DDBEDFDF052202E2EA60EE0EEE0EEE0EEE0EEE260E06A60606A606A6E60E0E0E2600026060E260E260EA60EA60E260EA60EA60E260E260EA60EA60EA6EE06A6061A601A0065521C05221C0502022006260E223020E22120626208206A600820E2600020E26000221A1A182A1A280EA6808221A2162010E021555521C052020202022006A60E26A60E260E262A6000E60CE00026A000E6020002002EA10212000220E00211012010,
|
| 671 |
|
|
ram_block1a_6.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 672 |
|
|
ram_block1a_6.operation_mode = "single_port",
|
| 673 |
|
|
ram_block1a_6.port_a_address_width = 13,
|
| 674 |
|
|
ram_block1a_6.port_a_byte_enable_mask_width = 1,
|
| 675 |
|
|
ram_block1a_6.port_a_byte_size = 1,
|
| 676 |
|
|
ram_block1a_6.port_a_data_out_clear = "none",
|
| 677 |
|
|
ram_block1a_6.port_a_data_out_clock = "clock0",
|
| 678 |
|
|
ram_block1a_6.port_a_data_width = 1,
|
| 679 |
|
|
ram_block1a_6.port_a_first_address = 0,
|
| 680 |
|
|
ram_block1a_6.port_a_first_bit_number = 6,
|
| 681 |
|
|
ram_block1a_6.port_a_last_address = 8191,
|
| 682 |
|
|
ram_block1a_6.port_a_logical_ram_depth = 16384,
|
| 683 |
|
|
ram_block1a_6.port_a_logical_ram_width = 8,
|
| 684 |
|
|
ram_block1a_6.port_a_read_during_write_mode = "new_data_no_nbe_read",
|
| 685 |
|
|
ram_block1a_6.power_up_uninitialized = "false",
|
| 686 |
|
|
ram_block1a_6.ram_block_type = "AUTO",
|
| 687 |
|
|
ram_block1a_6.lpm_type = "cycloneiii_ram_block";
|
| 688 |
|
|
cycloneiii_ram_block ram_block1a_7
|
| 689 |
|
|
(
|
| 690 |
|
|
.clk0(clock0),
|
| 691 |
|
|
.ena0(wire_rden_decode_eq[0]),
|
| 692 |
|
|
.portaaddr({address_a_wire[12:0]}),
|
| 693 |
|
|
.portadatain({data_a[7]}),
|
| 694 |
|
|
.portadataout(wire_ram_block1a_7portadataout[0:0]),
|
| 695 |
|
|
.portare(1'b1),
|
| 696 |
|
|
.portawe(wire_decode3_eq[0]),
|
| 697 |
|
|
.portbdataout()
|
| 698 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 699 |
|
|
// synopsys translate_off
|
| 700 |
|
|
`endif
|
| 701 |
|
|
,
|
| 702 |
|
|
.clk1(1'b0),
|
| 703 |
|
|
.clr0(1'b0),
|
| 704 |
|
|
.clr1(1'b0),
|
| 705 |
|
|
.ena1(1'b1),
|
| 706 |
|
|
.ena2(1'b1),
|
| 707 |
|
|
.ena3(1'b1),
|
| 708 |
|
|
.portaaddrstall(1'b0),
|
| 709 |
|
|
.portabyteenamasks({1{1'b1}}),
|
| 710 |
|
|
.portbaddr({1{1'b0}}),
|
| 711 |
|
|
.portbaddrstall(1'b0),
|
| 712 |
|
|
.portbbyteenamasks({1{1'b1}}),
|
| 713 |
|
|
.portbdatain({1{1'b0}}),
|
| 714 |
|
|
.portbre(1'b1),
|
| 715 |
|
|
.portbwe(1'b0)
|
| 716 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 717 |
|
|
// synopsys translate_on
|
| 718 |
|
|
`endif
|
| 719 |
|
|
// synopsys translate_off
|
| 720 |
|
|
,
|
| 721 |
|
|
.devclrn(1'b1),
|
| 722 |
|
|
.devpor(1'b1)
|
| 723 |
|
|
// synopsys translate_on
|
| 724 |
|
|
);
|
| 725 |
|
|
defparam
|
| 726 |
|
|
ram_block1a_7.clk0_core_clock_enable = "ena0",
|
| 727 |
|
|
ram_block1a_7.clk0_input_clock_enable = "none",
|
| 728 |
|
|
ram_block1a_7.clk0_output_clock_enable = "none",
|
| 729 |
|
|
ram_block1a_7.connectivity_checking = "OFF",
|
| 730 |
|
|
ram_block1a_7.init_file = "./bootrom/boot.mif",
|
| 731 |
|
|
ram_block1a_7.init_file_layout = "port_a",
|
| 732 |
|
|
ram_block1a_7.logical_ram_name = "ALTSYNCRAM",
|
| 733 |
|
|
ram_block1a_7.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000014333311113333111133331111333311141000110000000000000000000000000000000000000000000000000000000000000001,
|
| 734 |
|
|
ram_block1a_7.mem_init1 = 2048'h31131331133161133116140614555555111111D1011331111E1301110E1110E11131111333055111111D10113211D101DE1D911D101DE1D1011D1031111E1E3E10E11011F33111111D1031110E1311E11101130111111D10110E1333211D1010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000033331E0E133310E133320013111100113131B313131B0003331111333311113333111333311005555555555555551111111111111011000800131001D,
|
| 735 |
|
|
ram_block1a_7.mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101111E1E141D606D606D606D606D6160606940606940614DE0E060694001940E069406940614061406140694069406940694061406140614DE0E140E1143193301111D10111D101331110E140E113310E11110E1410110E9400110E9400110E94001111111111311130E14301111111913131305111111D101133113311106140E36141E363E16314003E13F6001361003E1310011011E913133301110E13111311313,
|
| 736 |
|
|
ram_block1a_7.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 737 |
|
|
ram_block1a_7.operation_mode = "single_port",
|
| 738 |
|
|
ram_block1a_7.port_a_address_width = 13,
|
| 739 |
|
|
ram_block1a_7.port_a_byte_enable_mask_width = 1,
|
| 740 |
|
|
ram_block1a_7.port_a_byte_size = 1,
|
| 741 |
|
|
ram_block1a_7.port_a_data_out_clear = "none",
|
| 742 |
|
|
ram_block1a_7.port_a_data_out_clock = "clock0",
|
| 743 |
|
|
ram_block1a_7.port_a_data_width = 1,
|
| 744 |
|
|
ram_block1a_7.port_a_first_address = 0,
|
| 745 |
|
|
ram_block1a_7.port_a_first_bit_number = 7,
|
| 746 |
|
|
ram_block1a_7.port_a_last_address = 8191,
|
| 747 |
|
|
ram_block1a_7.port_a_logical_ram_depth = 16384,
|
| 748 |
|
|
ram_block1a_7.port_a_logical_ram_width = 8,
|
| 749 |
|
|
ram_block1a_7.port_a_read_during_write_mode = "new_data_no_nbe_read",
|
| 750 |
|
|
ram_block1a_7.power_up_uninitialized = "false",
|
| 751 |
|
|
ram_block1a_7.ram_block_type = "AUTO",
|
| 752 |
|
|
ram_block1a_7.lpm_type = "cycloneiii_ram_block";
|
| 753 |
|
|
cycloneiii_ram_block ram_block1a_8
|
| 754 |
|
|
(
|
| 755 |
|
|
.clk0(clock0),
|
| 756 |
|
|
.ena0(wire_rden_decode_eq[1]),
|
| 757 |
|
|
.portaaddr({address_a_wire[12:0]}),
|
| 758 |
|
|
.portadatain({data_a[0]}),
|
| 759 |
|
|
.portadataout(wire_ram_block1a_8portadataout[0:0]),
|
| 760 |
|
|
.portare(1'b1),
|
| 761 |
|
|
.portawe(wire_decode3_eq[1]),
|
| 762 |
|
|
.portbdataout()
|
| 763 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 764 |
|
|
// synopsys translate_off
|
| 765 |
|
|
`endif
|
| 766 |
|
|
,
|
| 767 |
|
|
.clk1(1'b0),
|
| 768 |
|
|
.clr0(1'b0),
|
| 769 |
|
|
.clr1(1'b0),
|
| 770 |
|
|
.ena1(1'b1),
|
| 771 |
|
|
.ena2(1'b1),
|
| 772 |
|
|
.ena3(1'b1),
|
| 773 |
|
|
.portaaddrstall(1'b0),
|
| 774 |
|
|
.portabyteenamasks({1{1'b1}}),
|
| 775 |
|
|
.portbaddr({1{1'b0}}),
|
| 776 |
|
|
.portbaddrstall(1'b0),
|
| 777 |
|
|
.portbbyteenamasks({1{1'b1}}),
|
| 778 |
|
|
.portbdatain({1{1'b0}}),
|
| 779 |
|
|
.portbre(1'b1),
|
| 780 |
|
|
.portbwe(1'b0)
|
| 781 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 782 |
|
|
// synopsys translate_on
|
| 783 |
|
|
`endif
|
| 784 |
|
|
// synopsys translate_off
|
| 785 |
|
|
,
|
| 786 |
|
|
.devclrn(1'b1),
|
| 787 |
|
|
.devpor(1'b1)
|
| 788 |
|
|
// synopsys translate_on
|
| 789 |
|
|
);
|
| 790 |
|
|
defparam
|
| 791 |
|
|
ram_block1a_8.clk0_core_clock_enable = "ena0",
|
| 792 |
|
|
ram_block1a_8.clk0_input_clock_enable = "none",
|
| 793 |
|
|
ram_block1a_8.clk0_output_clock_enable = "none",
|
| 794 |
|
|
ram_block1a_8.connectivity_checking = "OFF",
|
| 795 |
|
|
ram_block1a_8.init_file = "./bootrom/boot.mif",
|
| 796 |
|
|
ram_block1a_8.init_file_layout = "port_a",
|
| 797 |
|
|
ram_block1a_8.logical_ram_name = "ALTSYNCRAM",
|
| 798 |
|
|
ram_block1a_8.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 799 |
|
|
ram_block1a_8.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 800 |
|
|
ram_block1a_8.mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 801 |
|
|
ram_block1a_8.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 802 |
|
|
ram_block1a_8.operation_mode = "single_port",
|
| 803 |
|
|
ram_block1a_8.port_a_address_width = 13,
|
| 804 |
|
|
ram_block1a_8.port_a_byte_enable_mask_width = 1,
|
| 805 |
|
|
ram_block1a_8.port_a_byte_size = 1,
|
| 806 |
|
|
ram_block1a_8.port_a_data_out_clear = "none",
|
| 807 |
|
|
ram_block1a_8.port_a_data_out_clock = "clock0",
|
| 808 |
|
|
ram_block1a_8.port_a_data_width = 1,
|
| 809 |
|
|
ram_block1a_8.port_a_first_address = 8192,
|
| 810 |
|
|
ram_block1a_8.port_a_first_bit_number = 0,
|
| 811 |
|
|
ram_block1a_8.port_a_last_address = 16383,
|
| 812 |
|
|
ram_block1a_8.port_a_logical_ram_depth = 16384,
|
| 813 |
|
|
ram_block1a_8.port_a_logical_ram_width = 8,
|
| 814 |
|
|
ram_block1a_8.port_a_read_during_write_mode = "new_data_no_nbe_read",
|
| 815 |
|
|
ram_block1a_8.power_up_uninitialized = "false",
|
| 816 |
|
|
ram_block1a_8.ram_block_type = "AUTO",
|
| 817 |
|
|
ram_block1a_8.lpm_type = "cycloneiii_ram_block";
|
| 818 |
|
|
cycloneiii_ram_block ram_block1a_9
|
| 819 |
|
|
(
|
| 820 |
|
|
.clk0(clock0),
|
| 821 |
|
|
.ena0(wire_rden_decode_eq[1]),
|
| 822 |
|
|
.portaaddr({address_a_wire[12:0]}),
|
| 823 |
|
|
.portadatain({data_a[1]}),
|
| 824 |
|
|
.portadataout(wire_ram_block1a_9portadataout[0:0]),
|
| 825 |
|
|
.portare(1'b1),
|
| 826 |
|
|
.portawe(wire_decode3_eq[1]),
|
| 827 |
|
|
.portbdataout()
|
| 828 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 829 |
|
|
// synopsys translate_off
|
| 830 |
|
|
`endif
|
| 831 |
|
|
,
|
| 832 |
|
|
.clk1(1'b0),
|
| 833 |
|
|
.clr0(1'b0),
|
| 834 |
|
|
.clr1(1'b0),
|
| 835 |
|
|
.ena1(1'b1),
|
| 836 |
|
|
.ena2(1'b1),
|
| 837 |
|
|
.ena3(1'b1),
|
| 838 |
|
|
.portaaddrstall(1'b0),
|
| 839 |
|
|
.portabyteenamasks({1{1'b1}}),
|
| 840 |
|
|
.portbaddr({1{1'b0}}),
|
| 841 |
|
|
.portbaddrstall(1'b0),
|
| 842 |
|
|
.portbbyteenamasks({1{1'b1}}),
|
| 843 |
|
|
.portbdatain({1{1'b0}}),
|
| 844 |
|
|
.portbre(1'b1),
|
| 845 |
|
|
.portbwe(1'b0)
|
| 846 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 847 |
|
|
// synopsys translate_on
|
| 848 |
|
|
`endif
|
| 849 |
|
|
// synopsys translate_off
|
| 850 |
|
|
,
|
| 851 |
|
|
.devclrn(1'b1),
|
| 852 |
|
|
.devpor(1'b1)
|
| 853 |
|
|
// synopsys translate_on
|
| 854 |
|
|
);
|
| 855 |
|
|
defparam
|
| 856 |
|
|
ram_block1a_9.clk0_core_clock_enable = "ena0",
|
| 857 |
|
|
ram_block1a_9.clk0_input_clock_enable = "none",
|
| 858 |
|
|
ram_block1a_9.clk0_output_clock_enable = "none",
|
| 859 |
|
|
ram_block1a_9.connectivity_checking = "OFF",
|
| 860 |
|
|
ram_block1a_9.init_file = "./bootrom/boot.mif",
|
| 861 |
|
|
ram_block1a_9.init_file_layout = "port_a",
|
| 862 |
|
|
ram_block1a_9.logical_ram_name = "ALTSYNCRAM",
|
| 863 |
|
|
ram_block1a_9.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 864 |
|
|
ram_block1a_9.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 865 |
|
|
ram_block1a_9.mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 866 |
|
|
ram_block1a_9.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 867 |
|
|
ram_block1a_9.operation_mode = "single_port",
|
| 868 |
|
|
ram_block1a_9.port_a_address_width = 13,
|
| 869 |
|
|
ram_block1a_9.port_a_byte_enable_mask_width = 1,
|
| 870 |
|
|
ram_block1a_9.port_a_byte_size = 1,
|
| 871 |
|
|
ram_block1a_9.port_a_data_out_clear = "none",
|
| 872 |
|
|
ram_block1a_9.port_a_data_out_clock = "clock0",
|
| 873 |
|
|
ram_block1a_9.port_a_data_width = 1,
|
| 874 |
|
|
ram_block1a_9.port_a_first_address = 8192,
|
| 875 |
|
|
ram_block1a_9.port_a_first_bit_number = 1,
|
| 876 |
|
|
ram_block1a_9.port_a_last_address = 16383,
|
| 877 |
|
|
ram_block1a_9.port_a_logical_ram_depth = 16384,
|
| 878 |
|
|
ram_block1a_9.port_a_logical_ram_width = 8,
|
| 879 |
|
|
ram_block1a_9.port_a_read_during_write_mode = "new_data_no_nbe_read",
|
| 880 |
|
|
ram_block1a_9.power_up_uninitialized = "false",
|
| 881 |
|
|
ram_block1a_9.ram_block_type = "AUTO",
|
| 882 |
|
|
ram_block1a_9.lpm_type = "cycloneiii_ram_block";
|
| 883 |
|
|
cycloneiii_ram_block ram_block1a_10
|
| 884 |
|
|
(
|
| 885 |
|
|
.clk0(clock0),
|
| 886 |
|
|
.ena0(wire_rden_decode_eq[1]),
|
| 887 |
|
|
.portaaddr({address_a_wire[12:0]}),
|
| 888 |
|
|
.portadatain({data_a[2]}),
|
| 889 |
|
|
.portadataout(wire_ram_block1a_10portadataout[0:0]),
|
| 890 |
|
|
.portare(1'b1),
|
| 891 |
|
|
.portawe(wire_decode3_eq[1]),
|
| 892 |
|
|
.portbdataout()
|
| 893 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 894 |
|
|
// synopsys translate_off
|
| 895 |
|
|
`endif
|
| 896 |
|
|
,
|
| 897 |
|
|
.clk1(1'b0),
|
| 898 |
|
|
.clr0(1'b0),
|
| 899 |
|
|
.clr1(1'b0),
|
| 900 |
|
|
.ena1(1'b1),
|
| 901 |
|
|
.ena2(1'b1),
|
| 902 |
|
|
.ena3(1'b1),
|
| 903 |
|
|
.portaaddrstall(1'b0),
|
| 904 |
|
|
.portabyteenamasks({1{1'b1}}),
|
| 905 |
|
|
.portbaddr({1{1'b0}}),
|
| 906 |
|
|
.portbaddrstall(1'b0),
|
| 907 |
|
|
.portbbyteenamasks({1{1'b1}}),
|
| 908 |
|
|
.portbdatain({1{1'b0}}),
|
| 909 |
|
|
.portbre(1'b1),
|
| 910 |
|
|
.portbwe(1'b0)
|
| 911 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 912 |
|
|
// synopsys translate_on
|
| 913 |
|
|
`endif
|
| 914 |
|
|
// synopsys translate_off
|
| 915 |
|
|
,
|
| 916 |
|
|
.devclrn(1'b1),
|
| 917 |
|
|
.devpor(1'b1)
|
| 918 |
|
|
// synopsys translate_on
|
| 919 |
|
|
);
|
| 920 |
|
|
defparam
|
| 921 |
|
|
ram_block1a_10.clk0_core_clock_enable = "ena0",
|
| 922 |
|
|
ram_block1a_10.clk0_input_clock_enable = "none",
|
| 923 |
|
|
ram_block1a_10.clk0_output_clock_enable = "none",
|
| 924 |
|
|
ram_block1a_10.connectivity_checking = "OFF",
|
| 925 |
|
|
ram_block1a_10.init_file = "./bootrom/boot.mif",
|
| 926 |
|
|
ram_block1a_10.init_file_layout = "port_a",
|
| 927 |
|
|
ram_block1a_10.logical_ram_name = "ALTSYNCRAM",
|
| 928 |
|
|
ram_block1a_10.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 929 |
|
|
ram_block1a_10.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 930 |
|
|
ram_block1a_10.mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 931 |
|
|
ram_block1a_10.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 932 |
|
|
ram_block1a_10.operation_mode = "single_port",
|
| 933 |
|
|
ram_block1a_10.port_a_address_width = 13,
|
| 934 |
|
|
ram_block1a_10.port_a_byte_enable_mask_width = 1,
|
| 935 |
|
|
ram_block1a_10.port_a_byte_size = 1,
|
| 936 |
|
|
ram_block1a_10.port_a_data_out_clear = "none",
|
| 937 |
|
|
ram_block1a_10.port_a_data_out_clock = "clock0",
|
| 938 |
|
|
ram_block1a_10.port_a_data_width = 1,
|
| 939 |
|
|
ram_block1a_10.port_a_first_address = 8192,
|
| 940 |
|
|
ram_block1a_10.port_a_first_bit_number = 2,
|
| 941 |
|
|
ram_block1a_10.port_a_last_address = 16383,
|
| 942 |
|
|
ram_block1a_10.port_a_logical_ram_depth = 16384,
|
| 943 |
|
|
ram_block1a_10.port_a_logical_ram_width = 8,
|
| 944 |
|
|
ram_block1a_10.port_a_read_during_write_mode = "new_data_no_nbe_read",
|
| 945 |
|
|
ram_block1a_10.power_up_uninitialized = "false",
|
| 946 |
|
|
ram_block1a_10.ram_block_type = "AUTO",
|
| 947 |
|
|
ram_block1a_10.lpm_type = "cycloneiii_ram_block";
|
| 948 |
|
|
cycloneiii_ram_block ram_block1a_11
|
| 949 |
|
|
(
|
| 950 |
|
|
.clk0(clock0),
|
| 951 |
|
|
.ena0(wire_rden_decode_eq[1]),
|
| 952 |
|
|
.portaaddr({address_a_wire[12:0]}),
|
| 953 |
|
|
.portadatain({data_a[3]}),
|
| 954 |
|
|
.portadataout(wire_ram_block1a_11portadataout[0:0]),
|
| 955 |
|
|
.portare(1'b1),
|
| 956 |
|
|
.portawe(wire_decode3_eq[1]),
|
| 957 |
|
|
.portbdataout()
|
| 958 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 959 |
|
|
// synopsys translate_off
|
| 960 |
|
|
`endif
|
| 961 |
|
|
,
|
| 962 |
|
|
.clk1(1'b0),
|
| 963 |
|
|
.clr0(1'b0),
|
| 964 |
|
|
.clr1(1'b0),
|
| 965 |
|
|
.ena1(1'b1),
|
| 966 |
|
|
.ena2(1'b1),
|
| 967 |
|
|
.ena3(1'b1),
|
| 968 |
|
|
.portaaddrstall(1'b0),
|
| 969 |
|
|
.portabyteenamasks({1{1'b1}}),
|
| 970 |
|
|
.portbaddr({1{1'b0}}),
|
| 971 |
|
|
.portbaddrstall(1'b0),
|
| 972 |
|
|
.portbbyteenamasks({1{1'b1}}),
|
| 973 |
|
|
.portbdatain({1{1'b0}}),
|
| 974 |
|
|
.portbre(1'b1),
|
| 975 |
|
|
.portbwe(1'b0)
|
| 976 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 977 |
|
|
// synopsys translate_on
|
| 978 |
|
|
`endif
|
| 979 |
|
|
// synopsys translate_off
|
| 980 |
|
|
,
|
| 981 |
|
|
.devclrn(1'b1),
|
| 982 |
|
|
.devpor(1'b1)
|
| 983 |
|
|
// synopsys translate_on
|
| 984 |
|
|
);
|
| 985 |
|
|
defparam
|
| 986 |
|
|
ram_block1a_11.clk0_core_clock_enable = "ena0",
|
| 987 |
|
|
ram_block1a_11.clk0_input_clock_enable = "none",
|
| 988 |
|
|
ram_block1a_11.clk0_output_clock_enable = "none",
|
| 989 |
|
|
ram_block1a_11.connectivity_checking = "OFF",
|
| 990 |
|
|
ram_block1a_11.init_file = "./bootrom/boot.mif",
|
| 991 |
|
|
ram_block1a_11.init_file_layout = "port_a",
|
| 992 |
|
|
ram_block1a_11.logical_ram_name = "ALTSYNCRAM",
|
| 993 |
|
|
ram_block1a_11.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 994 |
|
|
ram_block1a_11.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 995 |
|
|
ram_block1a_11.mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 996 |
|
|
ram_block1a_11.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 997 |
|
|
ram_block1a_11.operation_mode = "single_port",
|
| 998 |
|
|
ram_block1a_11.port_a_address_width = 13,
|
| 999 |
|
|
ram_block1a_11.port_a_byte_enable_mask_width = 1,
|
| 1000 |
|
|
ram_block1a_11.port_a_byte_size = 1,
|
| 1001 |
|
|
ram_block1a_11.port_a_data_out_clear = "none",
|
| 1002 |
|
|
ram_block1a_11.port_a_data_out_clock = "clock0",
|
| 1003 |
|
|
ram_block1a_11.port_a_data_width = 1,
|
| 1004 |
|
|
ram_block1a_11.port_a_first_address = 8192,
|
| 1005 |
|
|
ram_block1a_11.port_a_first_bit_number = 3,
|
| 1006 |
|
|
ram_block1a_11.port_a_last_address = 16383,
|
| 1007 |
|
|
ram_block1a_11.port_a_logical_ram_depth = 16384,
|
| 1008 |
|
|
ram_block1a_11.port_a_logical_ram_width = 8,
|
| 1009 |
|
|
ram_block1a_11.port_a_read_during_write_mode = "new_data_no_nbe_read",
|
| 1010 |
|
|
ram_block1a_11.power_up_uninitialized = "false",
|
| 1011 |
|
|
ram_block1a_11.ram_block_type = "AUTO",
|
| 1012 |
|
|
ram_block1a_11.lpm_type = "cycloneiii_ram_block";
|
| 1013 |
|
|
cycloneiii_ram_block ram_block1a_12
|
| 1014 |
|
|
(
|
| 1015 |
|
|
.clk0(clock0),
|
| 1016 |
|
|
.ena0(wire_rden_decode_eq[1]),
|
| 1017 |
|
|
.portaaddr({address_a_wire[12:0]}),
|
| 1018 |
|
|
.portadatain({data_a[4]}),
|
| 1019 |
|
|
.portadataout(wire_ram_block1a_12portadataout[0:0]),
|
| 1020 |
|
|
.portare(1'b1),
|
| 1021 |
|
|
.portawe(wire_decode3_eq[1]),
|
| 1022 |
|
|
.portbdataout()
|
| 1023 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 1024 |
|
|
// synopsys translate_off
|
| 1025 |
|
|
`endif
|
| 1026 |
|
|
,
|
| 1027 |
|
|
.clk1(1'b0),
|
| 1028 |
|
|
.clr0(1'b0),
|
| 1029 |
|
|
.clr1(1'b0),
|
| 1030 |
|
|
.ena1(1'b1),
|
| 1031 |
|
|
.ena2(1'b1),
|
| 1032 |
|
|
.ena3(1'b1),
|
| 1033 |
|
|
.portaaddrstall(1'b0),
|
| 1034 |
|
|
.portabyteenamasks({1{1'b1}}),
|
| 1035 |
|
|
.portbaddr({1{1'b0}}),
|
| 1036 |
|
|
.portbaddrstall(1'b0),
|
| 1037 |
|
|
.portbbyteenamasks({1{1'b1}}),
|
| 1038 |
|
|
.portbdatain({1{1'b0}}),
|
| 1039 |
|
|
.portbre(1'b1),
|
| 1040 |
|
|
.portbwe(1'b0)
|
| 1041 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 1042 |
|
|
// synopsys translate_on
|
| 1043 |
|
|
`endif
|
| 1044 |
|
|
// synopsys translate_off
|
| 1045 |
|
|
,
|
| 1046 |
|
|
.devclrn(1'b1),
|
| 1047 |
|
|
.devpor(1'b1)
|
| 1048 |
|
|
// synopsys translate_on
|
| 1049 |
|
|
);
|
| 1050 |
|
|
defparam
|
| 1051 |
|
|
ram_block1a_12.clk0_core_clock_enable = "ena0",
|
| 1052 |
|
|
ram_block1a_12.clk0_input_clock_enable = "none",
|
| 1053 |
|
|
ram_block1a_12.clk0_output_clock_enable = "none",
|
| 1054 |
|
|
ram_block1a_12.connectivity_checking = "OFF",
|
| 1055 |
|
|
ram_block1a_12.init_file = "./bootrom/boot.mif",
|
| 1056 |
|
|
ram_block1a_12.init_file_layout = "port_a",
|
| 1057 |
|
|
ram_block1a_12.logical_ram_name = "ALTSYNCRAM",
|
| 1058 |
|
|
ram_block1a_12.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 1059 |
|
|
ram_block1a_12.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 1060 |
|
|
ram_block1a_12.mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 1061 |
|
|
ram_block1a_12.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 1062 |
|
|
ram_block1a_12.operation_mode = "single_port",
|
| 1063 |
|
|
ram_block1a_12.port_a_address_width = 13,
|
| 1064 |
|
|
ram_block1a_12.port_a_byte_enable_mask_width = 1,
|
| 1065 |
|
|
ram_block1a_12.port_a_byte_size = 1,
|
| 1066 |
|
|
ram_block1a_12.port_a_data_out_clear = "none",
|
| 1067 |
|
|
ram_block1a_12.port_a_data_out_clock = "clock0",
|
| 1068 |
|
|
ram_block1a_12.port_a_data_width = 1,
|
| 1069 |
|
|
ram_block1a_12.port_a_first_address = 8192,
|
| 1070 |
|
|
ram_block1a_12.port_a_first_bit_number = 4,
|
| 1071 |
|
|
ram_block1a_12.port_a_last_address = 16383,
|
| 1072 |
|
|
ram_block1a_12.port_a_logical_ram_depth = 16384,
|
| 1073 |
|
|
ram_block1a_12.port_a_logical_ram_width = 8,
|
| 1074 |
|
|
ram_block1a_12.port_a_read_during_write_mode = "new_data_no_nbe_read",
|
| 1075 |
|
|
ram_block1a_12.power_up_uninitialized = "false",
|
| 1076 |
|
|
ram_block1a_12.ram_block_type = "AUTO",
|
| 1077 |
|
|
ram_block1a_12.lpm_type = "cycloneiii_ram_block";
|
| 1078 |
|
|
cycloneiii_ram_block ram_block1a_13
|
| 1079 |
|
|
(
|
| 1080 |
|
|
.clk0(clock0),
|
| 1081 |
|
|
.ena0(wire_rden_decode_eq[1]),
|
| 1082 |
|
|
.portaaddr({address_a_wire[12:0]}),
|
| 1083 |
|
|
.portadatain({data_a[5]}),
|
| 1084 |
|
|
.portadataout(wire_ram_block1a_13portadataout[0:0]),
|
| 1085 |
|
|
.portare(1'b1),
|
| 1086 |
|
|
.portawe(wire_decode3_eq[1]),
|
| 1087 |
|
|
.portbdataout()
|
| 1088 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 1089 |
|
|
// synopsys translate_off
|
| 1090 |
|
|
`endif
|
| 1091 |
|
|
,
|
| 1092 |
|
|
.clk1(1'b0),
|
| 1093 |
|
|
.clr0(1'b0),
|
| 1094 |
|
|
.clr1(1'b0),
|
| 1095 |
|
|
.ena1(1'b1),
|
| 1096 |
|
|
.ena2(1'b1),
|
| 1097 |
|
|
.ena3(1'b1),
|
| 1098 |
|
|
.portaaddrstall(1'b0),
|
| 1099 |
|
|
.portabyteenamasks({1{1'b1}}),
|
| 1100 |
|
|
.portbaddr({1{1'b0}}),
|
| 1101 |
|
|
.portbaddrstall(1'b0),
|
| 1102 |
|
|
.portbbyteenamasks({1{1'b1}}),
|
| 1103 |
|
|
.portbdatain({1{1'b0}}),
|
| 1104 |
|
|
.portbre(1'b1),
|
| 1105 |
|
|
.portbwe(1'b0)
|
| 1106 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 1107 |
|
|
// synopsys translate_on
|
| 1108 |
|
|
`endif
|
| 1109 |
|
|
// synopsys translate_off
|
| 1110 |
|
|
,
|
| 1111 |
|
|
.devclrn(1'b1),
|
| 1112 |
|
|
.devpor(1'b1)
|
| 1113 |
|
|
// synopsys translate_on
|
| 1114 |
|
|
);
|
| 1115 |
|
|
defparam
|
| 1116 |
|
|
ram_block1a_13.clk0_core_clock_enable = "ena0",
|
| 1117 |
|
|
ram_block1a_13.clk0_input_clock_enable = "none",
|
| 1118 |
|
|
ram_block1a_13.clk0_output_clock_enable = "none",
|
| 1119 |
|
|
ram_block1a_13.connectivity_checking = "OFF",
|
| 1120 |
|
|
ram_block1a_13.init_file = "./bootrom/boot.mif",
|
| 1121 |
|
|
ram_block1a_13.init_file_layout = "port_a",
|
| 1122 |
|
|
ram_block1a_13.logical_ram_name = "ALTSYNCRAM",
|
| 1123 |
|
|
ram_block1a_13.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 1124 |
|
|
ram_block1a_13.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 1125 |
|
|
ram_block1a_13.mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 1126 |
|
|
ram_block1a_13.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 1127 |
|
|
ram_block1a_13.operation_mode = "single_port",
|
| 1128 |
|
|
ram_block1a_13.port_a_address_width = 13,
|
| 1129 |
|
|
ram_block1a_13.port_a_byte_enable_mask_width = 1,
|
| 1130 |
|
|
ram_block1a_13.port_a_byte_size = 1,
|
| 1131 |
|
|
ram_block1a_13.port_a_data_out_clear = "none",
|
| 1132 |
|
|
ram_block1a_13.port_a_data_out_clock = "clock0",
|
| 1133 |
|
|
ram_block1a_13.port_a_data_width = 1,
|
| 1134 |
|
|
ram_block1a_13.port_a_first_address = 8192,
|
| 1135 |
|
|
ram_block1a_13.port_a_first_bit_number = 5,
|
| 1136 |
|
|
ram_block1a_13.port_a_last_address = 16383,
|
| 1137 |
|
|
ram_block1a_13.port_a_logical_ram_depth = 16384,
|
| 1138 |
|
|
ram_block1a_13.port_a_logical_ram_width = 8,
|
| 1139 |
|
|
ram_block1a_13.port_a_read_during_write_mode = "new_data_no_nbe_read",
|
| 1140 |
|
|
ram_block1a_13.power_up_uninitialized = "false",
|
| 1141 |
|
|
ram_block1a_13.ram_block_type = "AUTO",
|
| 1142 |
|
|
ram_block1a_13.lpm_type = "cycloneiii_ram_block";
|
| 1143 |
|
|
cycloneiii_ram_block ram_block1a_14
|
| 1144 |
|
|
(
|
| 1145 |
|
|
.clk0(clock0),
|
| 1146 |
|
|
.ena0(wire_rden_decode_eq[1]),
|
| 1147 |
|
|
.portaaddr({address_a_wire[12:0]}),
|
| 1148 |
|
|
.portadatain({data_a[6]}),
|
| 1149 |
|
|
.portadataout(wire_ram_block1a_14portadataout[0:0]),
|
| 1150 |
|
|
.portare(1'b1),
|
| 1151 |
|
|
.portawe(wire_decode3_eq[1]),
|
| 1152 |
|
|
.portbdataout()
|
| 1153 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 1154 |
|
|
// synopsys translate_off
|
| 1155 |
|
|
`endif
|
| 1156 |
|
|
,
|
| 1157 |
|
|
.clk1(1'b0),
|
| 1158 |
|
|
.clr0(1'b0),
|
| 1159 |
|
|
.clr1(1'b0),
|
| 1160 |
|
|
.ena1(1'b1),
|
| 1161 |
|
|
.ena2(1'b1),
|
| 1162 |
|
|
.ena3(1'b1),
|
| 1163 |
|
|
.portaaddrstall(1'b0),
|
| 1164 |
|
|
.portabyteenamasks({1{1'b1}}),
|
| 1165 |
|
|
.portbaddr({1{1'b0}}),
|
| 1166 |
|
|
.portbaddrstall(1'b0),
|
| 1167 |
|
|
.portbbyteenamasks({1{1'b1}}),
|
| 1168 |
|
|
.portbdatain({1{1'b0}}),
|
| 1169 |
|
|
.portbre(1'b1),
|
| 1170 |
|
|
.portbwe(1'b0)
|
| 1171 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 1172 |
|
|
// synopsys translate_on
|
| 1173 |
|
|
`endif
|
| 1174 |
|
|
// synopsys translate_off
|
| 1175 |
|
|
,
|
| 1176 |
|
|
.devclrn(1'b1),
|
| 1177 |
|
|
.devpor(1'b1)
|
| 1178 |
|
|
// synopsys translate_on
|
| 1179 |
|
|
);
|
| 1180 |
|
|
defparam
|
| 1181 |
|
|
ram_block1a_14.clk0_core_clock_enable = "ena0",
|
| 1182 |
|
|
ram_block1a_14.clk0_input_clock_enable = "none",
|
| 1183 |
|
|
ram_block1a_14.clk0_output_clock_enable = "none",
|
| 1184 |
|
|
ram_block1a_14.connectivity_checking = "OFF",
|
| 1185 |
|
|
ram_block1a_14.init_file = "./bootrom/boot.mif",
|
| 1186 |
|
|
ram_block1a_14.init_file_layout = "port_a",
|
| 1187 |
|
|
ram_block1a_14.logical_ram_name = "ALTSYNCRAM",
|
| 1188 |
|
|
ram_block1a_14.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 1189 |
|
|
ram_block1a_14.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 1190 |
|
|
ram_block1a_14.mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 1191 |
|
|
ram_block1a_14.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 1192 |
|
|
ram_block1a_14.operation_mode = "single_port",
|
| 1193 |
|
|
ram_block1a_14.port_a_address_width = 13,
|
| 1194 |
|
|
ram_block1a_14.port_a_byte_enable_mask_width = 1,
|
| 1195 |
|
|
ram_block1a_14.port_a_byte_size = 1,
|
| 1196 |
|
|
ram_block1a_14.port_a_data_out_clear = "none",
|
| 1197 |
|
|
ram_block1a_14.port_a_data_out_clock = "clock0",
|
| 1198 |
|
|
ram_block1a_14.port_a_data_width = 1,
|
| 1199 |
|
|
ram_block1a_14.port_a_first_address = 8192,
|
| 1200 |
|
|
ram_block1a_14.port_a_first_bit_number = 6,
|
| 1201 |
|
|
ram_block1a_14.port_a_last_address = 16383,
|
| 1202 |
|
|
ram_block1a_14.port_a_logical_ram_depth = 16384,
|
| 1203 |
|
|
ram_block1a_14.port_a_logical_ram_width = 8,
|
| 1204 |
|
|
ram_block1a_14.port_a_read_during_write_mode = "new_data_no_nbe_read",
|
| 1205 |
|
|
ram_block1a_14.power_up_uninitialized = "false",
|
| 1206 |
|
|
ram_block1a_14.ram_block_type = "AUTO",
|
| 1207 |
|
|
ram_block1a_14.lpm_type = "cycloneiii_ram_block";
|
| 1208 |
|
|
cycloneiii_ram_block ram_block1a_15
|
| 1209 |
|
|
(
|
| 1210 |
|
|
.clk0(clock0),
|
| 1211 |
|
|
.ena0(wire_rden_decode_eq[1]),
|
| 1212 |
|
|
.portaaddr({address_a_wire[12:0]}),
|
| 1213 |
|
|
.portadatain({data_a[7]}),
|
| 1214 |
|
|
.portadataout(wire_ram_block1a_15portadataout[0:0]),
|
| 1215 |
|
|
.portare(1'b1),
|
| 1216 |
|
|
.portawe(wire_decode3_eq[1]),
|
| 1217 |
|
|
.portbdataout()
|
| 1218 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 1219 |
|
|
// synopsys translate_off
|
| 1220 |
|
|
`endif
|
| 1221 |
|
|
,
|
| 1222 |
|
|
.clk1(1'b0),
|
| 1223 |
|
|
.clr0(1'b0),
|
| 1224 |
|
|
.clr1(1'b0),
|
| 1225 |
|
|
.ena1(1'b1),
|
| 1226 |
|
|
.ena2(1'b1),
|
| 1227 |
|
|
.ena3(1'b1),
|
| 1228 |
|
|
.portaaddrstall(1'b0),
|
| 1229 |
|
|
.portabyteenamasks({1{1'b1}}),
|
| 1230 |
|
|
.portbaddr({1{1'b0}}),
|
| 1231 |
|
|
.portbaddrstall(1'b0),
|
| 1232 |
|
|
.portbbyteenamasks({1{1'b1}}),
|
| 1233 |
|
|
.portbdatain({1{1'b0}}),
|
| 1234 |
|
|
.portbre(1'b1),
|
| 1235 |
|
|
.portbwe(1'b0)
|
| 1236 |
|
|
`ifndef FORMAL_VERIFICATION
|
| 1237 |
|
|
// synopsys translate_on
|
| 1238 |
|
|
`endif
|
| 1239 |
|
|
// synopsys translate_off
|
| 1240 |
|
|
,
|
| 1241 |
|
|
.devclrn(1'b1),
|
| 1242 |
|
|
.devpor(1'b1)
|
| 1243 |
|
|
// synopsys translate_on
|
| 1244 |
|
|
);
|
| 1245 |
|
|
defparam
|
| 1246 |
|
|
ram_block1a_15.clk0_core_clock_enable = "ena0",
|
| 1247 |
|
|
ram_block1a_15.clk0_input_clock_enable = "none",
|
| 1248 |
|
|
ram_block1a_15.clk0_output_clock_enable = "none",
|
| 1249 |
|
|
ram_block1a_15.connectivity_checking = "OFF",
|
| 1250 |
|
|
ram_block1a_15.init_file = "./bootrom/boot.mif",
|
| 1251 |
|
|
ram_block1a_15.init_file_layout = "port_a",
|
| 1252 |
|
|
ram_block1a_15.logical_ram_name = "ALTSYNCRAM",
|
| 1253 |
|
|
ram_block1a_15.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 1254 |
|
|
ram_block1a_15.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 1255 |
|
|
ram_block1a_15.mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 1256 |
|
|
ram_block1a_15.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
|
| 1257 |
|
|
ram_block1a_15.operation_mode = "single_port",
|
| 1258 |
|
|
ram_block1a_15.port_a_address_width = 13,
|
| 1259 |
|
|
ram_block1a_15.port_a_byte_enable_mask_width = 1,
|
| 1260 |
|
|
ram_block1a_15.port_a_byte_size = 1,
|
| 1261 |
|
|
ram_block1a_15.port_a_data_out_clear = "none",
|
| 1262 |
|
|
ram_block1a_15.port_a_data_out_clock = "clock0",
|
| 1263 |
|
|
ram_block1a_15.port_a_data_width = 1,
|
| 1264 |
|
|
ram_block1a_15.port_a_first_address = 8192,
|
| 1265 |
|
|
ram_block1a_15.port_a_first_bit_number = 7,
|
| 1266 |
|
|
ram_block1a_15.port_a_last_address = 16383,
|
| 1267 |
|
|
ram_block1a_15.port_a_logical_ram_depth = 16384,
|
| 1268 |
|
|
ram_block1a_15.port_a_logical_ram_width = 8,
|
| 1269 |
|
|
ram_block1a_15.port_a_read_during_write_mode = "new_data_no_nbe_read",
|
| 1270 |
|
|
ram_block1a_15.power_up_uninitialized = "false",
|
| 1271 |
|
|
ram_block1a_15.ram_block_type = "AUTO",
|
| 1272 |
|
|
ram_block1a_15.lpm_type = "cycloneiii_ram_block";
|
| 1273 |
|
|
assign
|
| 1274 |
|
|
address_a_sel = address_a[13],
|
| 1275 |
|
|
address_a_wire = address_a,
|
| 1276 |
|
|
q_a = wire_mux2_result,
|
| 1277 |
|
|
rden_decode_addr_sel_a = address_a_wire[13];
|
| 1278 |
|
|
initial/*synthesis enable_verilog_initial_construct*/
|
| 1279 |
|
|
begin
|
| 1280 |
|
|
$display("Warning: Memory initialization file ./bootrom/boot.mif is not of the dimensions 16384 X 8, the resulting memory design may not produce consistent simulation results.");
|
| 1281 |
|
|
end
|
| 1282 |
|
|
endmodule //altera_ram_altsyncram
|
| 1283 |
|
|
//VALID FILE
|
| 1284 |
|
|
|
| 1285 |
|
|
|
| 1286 |
|
|
// synopsys translate_off
|
| 1287 |
|
|
`timescale 1 ps / 1 ps
|
| 1288 |
|
|
// synopsys translate_on
|
| 1289 |
|
|
module altera_ram (
|
| 1290 |
|
|
address,
|
| 1291 |
|
|
clock,
|
| 1292 |
|
|
data,
|
| 1293 |
|
|
wren,
|
| 1294 |
|
|
q)/* synthesis synthesis_clearbox = 1 */;
|
| 1295 |
|
|
|
| 1296 |
|
|
input [13:0] address;
|
| 1297 |
|
|
input clock;
|
| 1298 |
|
|
input [7:0] data;
|
| 1299 |
|
|
input wren;
|
| 1300 |
|
|
output [7:0] q;
|
| 1301 |
|
|
`ifndef ALTERA_RESERVED_QIS
|
| 1302 |
|
|
// synopsys translate_off
|
| 1303 |
|
|
`endif
|
| 1304 |
|
|
tri1 clock;
|
| 1305 |
|
|
`ifndef ALTERA_RESERVED_QIS
|
| 1306 |
|
|
// synopsys translate_on
|
| 1307 |
|
|
`endif
|
| 1308 |
|
|
|
| 1309 |
|
|
wire [7:0] sub_wire0;
|
| 1310 |
|
|
wire [7:0] q = sub_wire0[7:0];
|
| 1311 |
|
|
|
| 1312 |
|
|
altera_ram_altsyncram altera_ram_altsyncram_component (
|
| 1313 |
|
|
.wren_a (wren),
|
| 1314 |
|
|
.clock0 (clock),
|
| 1315 |
|
|
.address_a (address),
|
| 1316 |
|
|
.data_a (data),
|
| 1317 |
|
|
.q_a (sub_wire0));
|
| 1318 |
|
|
|
| 1319 |
|
|
endmodule
|
| 1320 |
|
|
|
| 1321 |
|
|
// ============================================================
|
| 1322 |
|
|
// CNX file retrieval info
|
| 1323 |
|
|
// ============================================================
|
| 1324 |
|
|
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
| 1325 |
|
|
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
|
| 1326 |
|
|
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
|
| 1327 |
|
|
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
|
| 1328 |
|
|
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
|
| 1329 |
|
|
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
|
| 1330 |
|
|
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
| 1331 |
|
|
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
|
| 1332 |
|
|
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
| 1333 |
|
|
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
| 1334 |
|
|
// Retrieval info: PRIVATE: Clken NUMERIC "0"
|
| 1335 |
|
|
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
|
| 1336 |
|
|
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "1"
|
| 1337 |
|
|
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
|
| 1338 |
|
|
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
| 1339 |
|
|
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
| 1340 |
|
|
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
| 1341 |
|
|
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
| 1342 |
|
|
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
| 1343 |
|
|
// Retrieval info: PRIVATE: MIFfilename STRING "./bootrom/boot.mif"
|
| 1344 |
|
|
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384"
|
| 1345 |
|
|
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
| 1346 |
|
|
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
|
| 1347 |
|
|
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
|
| 1348 |
|
|
// Retrieval info: PRIVATE: RegData NUMERIC "1"
|
| 1349 |
|
|
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
|
| 1350 |
|
|
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
|
| 1351 |
|
|
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
|
| 1352 |
|
|
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
|
| 1353 |
|
|
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
|
| 1354 |
|
|
// Retrieval info: PRIVATE: WidthAddr NUMERIC "14"
|
| 1355 |
|
|
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
|
| 1356 |
|
|
// Retrieval info: PRIVATE: rden NUMERIC "0"
|
| 1357 |
|
|
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
| 1358 |
|
|
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
|
| 1359 |
|
|
// Retrieval info: CONSTANT: INIT_FILE STRING "./bootrom/boot.mif"
|
| 1360 |
|
|
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
| 1361 |
|
|
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
| 1362 |
|
|
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
| 1363 |
|
|
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
|
| 1364 |
|
|
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
|
| 1365 |
|
|
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
|
| 1366 |
|
|
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
|
| 1367 |
|
|
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
|
| 1368 |
|
|
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
|
| 1369 |
|
|
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
|
| 1370 |
|
|
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
|
| 1371 |
|
|
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
| 1372 |
|
|
// Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL address[13..0]
|
| 1373 |
|
|
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
|
| 1374 |
|
|
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
|
| 1375 |
|
|
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
|
| 1376 |
|
|
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
|
| 1377 |
|
|
// Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0
|
| 1378 |
|
|
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
|
| 1379 |
|
|
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
|
| 1380 |
|
|
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
|
| 1381 |
|
|
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
|
| 1382 |
|
|
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
| 1383 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram.v TRUE
|
| 1384 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram.inc FALSE
|
| 1385 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram.cmp FALSE
|
| 1386 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram.bsf TRUE FALSE
|
| 1387 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram_inst.v TRUE
|
| 1388 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram_bb.v TRUE
|
| 1389 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram_waveforms.html TRUE
|
| 1390 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram_wave*.jpg FALSE
|
| 1391 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram_syn.v TRUE
|
| 1392 |
|
|
// Retrieval info: LIB_FILE: altera_mf
|
