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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [altera_ram/] [altera_ram_top.v] - Blame information for rev 12

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//===============================================================================
//
//          FILE:  altera_ram_top.v
// 
//         USAGE:  ./altera_ram_top.v 
// 
//   DESCRIPTION:  Wishbone bridge for Altera RAM core
// 
//       OPTIONS:  ---
//  REQUIREMENTS:  ---
//          BUGS:  ---
//         NOTES:  ---
//        AUTHOR:  Xianfeng Zeng (ZXF), xianfeng.zeng@gmail.com
//                                      xianfeng.zeng@SierraAtlantic.com
//       COMPANY:  
//       VERSION:  1.0
//       CREATED:  10/10/2009 06:15:19 PM HKT
//      REVISION:  ---
//===============================================================================
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
 
module altera_ram_top (
  wb_clk_i, wb_rst_i,
 
  wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
  wb_stb_i, wb_ack_o, wb_err_o
 
);
 
//
// Paraneters
//
parameter       Idle  = 12'b100000000000,
                Read0 = 12'b010000000000,
                Read1 = 12'b001000000000,
                Read2 = 12'b000100000000,
                Read3 = 12'b000010000000,
                Write0= 12'b000001000000,
                Write1= 12'b000000100000,
                Write2= 12'b000000010000,
                Write3= 12'b000000001000,
                Ack   = 12'b000000000100,
                Read_done  = 12'b000000000010,
                Write_done =  12'b000000000001;
 
//
// I/O Ports
//
input                   wb_clk_i;
input                   wb_rst_i;
 
//
// WB slave i/f
//
input   [31:0]           wb_dat_i;
output  [31:0]           wb_dat_o;
input   [31:0]           wb_adr_i;
input   [3:0]            wb_sel_i;
input                   wb_we_i;
input                   wb_cyc_i;
input                   wb_stb_i;
output                  wb_ack_o;
output                  wb_err_o;
 
 
//
// Internal regs and wires
//
reg             ack_we;
reg             wren;
reg [31:0]       adr;
reg [31:0]       cur_adr;
reg [31:0]       data_save;
reg [3:0]       sel;
 
wire            wb_err;
 
reg             clk;
integer         i;
wire [7:0]       data_q;
reg  [7:0]       data;
 
reg [11:0]       State;
 
wire            bit_shift;
 
//
// Aliases and simple assignments
//
assign wb_err = wb_cyc_i & wb_stb_i & (|wb_adr_i[20:14]);       // If Access to > 16KB (4-bit leading prefix ignored)
assign wb_err_o = wb_err;
 
//
// Use State Machine to 32->8 or 8->32
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
        if (wb_rst_i) begin
                State <= Idle;
                wren <= 1'b0;
        end
        else
                case (State)
                        Idle: begin
                                if (wb_cyc_i & wb_stb_i) begin
                                        adr <= {5'b0000,wb_adr_i[26:2],2'b00};
                                        cur_adr <= {5'b0000,wb_adr_i[26:2],2'b00};
                                        sel <= wb_sel_i;
                                        if (wb_we_i) begin
                                                data_save <= wb_dat_i;
                                                State <= Write0;
                                            end
                                        else
                                                State <= Read0;
                                end
                                wren <= 1'b0;
                        end
                        Read0: begin
                                State <= Read1;
                                cur_adr <= adr + 1;
//                              data_save[31:24] <= data_q;
                        end
                        Read1: begin
                                State <= Read2;
                                cur_adr <= adr + 2;
                                data_save[31:24] <= data_q;
                        end
                        Read2: begin
                                State <= Read3;
                                cur_adr <= adr + 3;
                                data_save[23:16] <= data_q;
                        end
                        Read3: begin
                                State <= Read_done;
                                data_save[15:8] <= data_q;
                        end
                        Read_done: begin
                             data_save[7:0] <= data_q;
                                State <= Ack;
                        end
                        Ack: begin
                                State <= Idle;
                                wren <= 1'b0;
                        end
                        Write0: begin
                                if (sel[3]) begin
                                        data <= data_save[31:24];
                                        wren <= 1'b1;
                                end else
                                        wren <= 1'b0;
                                cur_adr <= adr;
                                State <= Write1;
                        end
                        Write1: begin
                                if (sel[2]) begin
                                        data <= data_save[23:16];
                                        wren <= 1'b1;
                                end else
                                        wren <= 1'b0;
                                cur_adr <= adr + 1;
                                State <= Write2;
                        end
                        Write2: begin
                                if (sel[1]) begin
                                        data <= data_save[15:8];
                                        wren <= 1'b1;
                                end else
                                        wren <= 1'b0;
                                cur_adr <= adr + 2;
                                State <= Write3;
                        end
                        Write3: begin
                                if (sel[0]) begin
                                        data <= data_save[7:0];
                                        wren <= 1'b1;
                                end else
                                        wren <= 1'b0;
                                cur_adr <= adr + 3;
                                State <= Ack;
                        end
                        default: State <= Idle;
                endcase
end
 
assign wb_dat_o = data_save;
assign wb_ack_o = (State == Ack) ? 1'b1 : 1'b0;
 
//
// Connect to altera 1-port RAM
//
altera_ram      altera_ram_inst (
        .address        ( cur_adr[13:0] ),
        .clock          ( wb_clk_i ),
        .data           ( data ),
        .wren           ( wren ),
        .q              ( data_q )
        );
 
//
// SRAM i/f monitor
//
// synopsys translate_off
integer fsram;
initial begin
        fsram = $fopen("sram.log");
end
always @(posedge wb_clk_i)
        if (wb_cyc_i)
                if (State == Ack)
                        if (wb_we_i)
                                $fdisplay(fsram, "%t [%h] <- write %h, byte sel %b", $time, wb_adr_i, wb_dat_i, wb_sel_i);
                        else
                                $fdisplay(fsram, "%t [%h] -> read %h, byte sel %b", $time, wb_adr_i, wb_dat_o, wb_sel_i);
// synopsys translate_on
 
endmodule
 
 

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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [altera_ram/] [altera_ram_top.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	xianfeng	`//===============================================================================`
2			`//`
3			`// FILE: altera_ram_top.v`
4			`//`
5			`// USAGE: ./altera_ram_top.v`
6			`//`
7			`// DESCRIPTION: Wishbone bridge for Altera RAM core`
8			`//`
9			`// OPTIONS: ---`
10			`// REQUIREMENTS: ---`
11			`// BUGS: ---`
12			`// NOTES: ---`
13			`// AUTHOR: Xianfeng Zeng (ZXF), xianfeng.zeng@gmail.com`
14			`// xianfeng.zeng@SierraAtlantic.com`
15			`// COMPANY:`
16			`// VERSION: 1.0`
17			`// CREATED: 10/10/2009 06:15:19 PM HKT`
18			`// REVISION: ---`
19			`//===============================================================================`
20
21			`// synopsys translate_off`
22			`include "timescale.v"
23			`// synopsys translate_on`
24
25
26			`module altera_ram_top (`
27			`wb_clk_i, wb_rst_i,`
28
29			`wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,`
30			`wb_stb_i, wb_ack_o, wb_err_o`
31
32			`);`
33
34			`//`
35			`// Paraneters`
36			`//`
37			`parameter Idle = 12'b100000000000,`
38			`Read0 = 12'b010000000000,`
39			`Read1 = 12'b001000000000,`
40			`Read2 = 12'b000100000000,`
41			`Read3 = 12'b000010000000,`
42			`Write0= 12'b000001000000,`
43			`Write1= 12'b000000100000,`
44			`Write2= 12'b000000010000,`
45			`Write3= 12'b000000001000,`
46			`Ack = 12'b000000000100,`
47			`Read_done = 12'b000000000010,`
48			`Write_done = 12'b000000000001;`
49
50			`//`
51			`// I/O Ports`
52			`//`
53			`input wb_clk_i;`
54			`input wb_rst_i;`
55
56			`//`
57			`// WB slave i/f`
58			`//`
59			`input [31:0] wb_dat_i;`
60			`output [31:0] wb_dat_o;`
61			`input [31:0] wb_adr_i;`
62			`input [3:0] wb_sel_i;`
63			`input wb_we_i;`
64			`input wb_cyc_i;`
65			`input wb_stb_i;`
66			`output wb_ack_o;`
67			`output wb_err_o;`
68
69
70			`//`
71			`// Internal regs and wires`
72			`//`
73			`reg ack_we;`
74			`reg wren;`
75			`reg [31:0] adr;`
76			`reg [31:0] cur_adr;`
77			`reg [31:0] data_save;`
78			`reg [3:0] sel;`
79
80			`wire wb_err;`
81
82			`reg clk;`
83			`integer i;`
84			`wire [7:0] data_q;`
85			`reg [7:0] data;`
86
87			`reg [11:0] State;`
88
89			`wire bit_shift;`
90
91			`//`
92			`// Aliases and simple assignments`
93			`//`
94			`assign wb_err = wb_cyc_i & wb_stb_i & (\|wb_adr_i[20:14]); // If Access to > 16KB (4-bit leading prefix ignored)`
95			`assign wb_err_o = wb_err;`
96
97			`//`
98			`// Use State Machine to 32->8 or 8->32`
99			`//`
100			`always @ (negedge wb_clk_i or posedge wb_rst_i)`
101			`begin`
102			`if (wb_rst_i) begin`
103			`State <= Idle;`
104			`wren <= 1'b0;`
105			`end`
106			`else`
107			`case (State)`
108			`Idle: begin`
109			`if (wb_cyc_i & wb_stb_i) begin`
110			`adr <= {5'b0000,wb_adr_i[26:2],2'b00};`
111			`cur_adr <= {5'b0000,wb_adr_i[26:2],2'b00};`
112			`sel <= wb_sel_i;`
113			`if (wb_we_i) begin`
114			`data_save <= wb_dat_i;`
115			`State <= Write0;`
116			`end`
117			`else`
118			`State <= Read0;`
119			`end`
120			`wren <= 1'b0;`
121			`end`
122			`Read0: begin`
123			`State <= Read1;`
124			`cur_adr <= adr + 1;`
125			`// data_save[31:24] <= data_q;`
126			`end`
127			`Read1: begin`
128			`State <= Read2;`
129			`cur_adr <= adr + 2;`
130			`data_save[31:24] <= data_q;`
131			`end`
132			`Read2: begin`
133			`State <= Read3;`
134			`cur_adr <= adr + 3;`
135			`data_save[23:16] <= data_q;`
136			`end`
137			`Read3: begin`
138			`State <= Read_done;`
139			`data_save[15:8] <= data_q;`
140			`end`
141			`Read_done: begin`
142			`data_save[7:0] <= data_q;`
143			`State <= Ack;`
144			`end`
145			`Ack: begin`
146			`State <= Idle;`
147			`wren <= 1'b0;`
148			`end`
149			`Write0: begin`
150			`if (sel[3]) begin`
151			`data <= data_save[31:24];`
152			`wren <= 1'b1;`
153			`end else`
154			`wren <= 1'b0;`
155			`cur_adr <= adr;`
156			`State <= Write1;`
157			`end`
158			`Write1: begin`
159			`if (sel[2]) begin`
160			`data <= data_save[23:16];`
161			`wren <= 1'b1;`
162			`end else`
163			`wren <= 1'b0;`
164			`cur_adr <= adr + 1;`
165			`State <= Write2;`
166			`end`
167			`Write2: begin`
168			`if (sel[1]) begin`
169			`data <= data_save[15:8];`
170			`wren <= 1'b1;`
171			`end else`
172			`wren <= 1'b0;`
173			`cur_adr <= adr + 2;`
174			`State <= Write3;`
175			`end`
176			`Write3: begin`
177			`if (sel[0]) begin`
178			`data <= data_save[7:0];`
179			`wren <= 1'b1;`
180			`end else`
181			`wren <= 1'b0;`
182			`cur_adr <= adr + 3;`
183			`State <= Ack;`
184			`end`
185			`default: State <= Idle;`
186			`endcase`
187			`end`
188
189			`assign wb_dat_o = data_save;`
190			`assign wb_ack_o = (State == Ack) ? 1'b1 : 1'b0;`
191
192			`//`
193			`// Connect to altera 1-port RAM`
194			`//`
195			`altera_ram altera_ram_inst (`
196			`.address ( cur_adr[13:0] ),`
197			`.clock ( wb_clk_i ),`
198			`.data ( data ),`
199			`.wren ( wren ),`
200			`.q ( data_q )`
201			`);`
202
203			`//`
204			`// SRAM i/f monitor`
205			`//`
206			`// synopsys translate_off`
207			`integer fsram;`
208			`initial begin`
209			`fsram = $fopen("sram.log");`
210			`end`
211			`always @(posedge wb_clk_i)`
212			`if (wb_cyc_i)`
213			`if (State == Ack)`
214			`if (wb_we_i)`
215			`$fdisplay(fsram, "%t [%h] <- write %h, byte sel %b", $time, wb_adr_i, wb_dat_i, wb_sel_i);`
216			`else`
217			`$fdisplay(fsram, "%t [%h] -> read %h, byte sel %b", $time, wb_adr_i, wb_dat_o, wb_sel_i);`
218			`// synopsys translate_on`
219
220			`endmodule`
221
222