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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [dbg_interface/] [rtl/] [verilog/] [dbg_cpu_registers.v] - Blame information for rev 12

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_cpu_registers.v                                         ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC Debug Interface.               ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2004 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5  2004/03/22 16:35:46  igorm
// Temp version before changing dbg interface.
//
// Revision 1.4  2004/01/25 14:04:18  mohor
// All flipflops are reset.
//
// Revision 1.3  2004/01/22 10:16:08  mohor
// cpu_stall_o activated as soon as bp occurs.
//
// Revision 1.2  2004/01/17 17:01:14  mohor
// Almost finished.
//
// Revision 1.1  2004/01/16 14:53:33  mohor
// *** empty log message ***
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_cpu_defines.v"
 
module dbg_cpu_registers  (
                            data_i,
                            we_i,
                            tck_i,
                            bp_i,
                            rst_i,
                            cpu_clk_i,
                            ctrl_reg_o,
                            cpu_stall_o,
                            cpu_rst_o
                          );
 
 
input  [`DBG_CPU_CTRL_LEN -1:0] data_i;
input                   we_i;
input                   tck_i;
input                   bp_i;
input                   rst_i;
input                   cpu_clk_i;
 
output [`DBG_CPU_CTRL_LEN -1:0]ctrl_reg_o;
output                  cpu_stall_o;
output                  cpu_rst_o;
 
reg                     cpu_reset;
wire             [2:1]  cpu_op_out;
 
reg                     stall_bp, stall_bp_csff, stall_bp_tck;
reg                     stall_reg, stall_reg_csff, stall_reg_cpu;
reg                     cpu_reset_csff;
reg                     cpu_rst_o;
 
 
 
// Breakpoint is latched and synchronized. Stall is set and latched.
always @ (posedge cpu_clk_i or posedge rst_i)
begin
  if(rst_i)
    stall_bp <= #1 1'b0;
  else if(bp_i)
    stall_bp <= #1 1'b1;
  else if(stall_reg_cpu)
    stall_bp <= #1 1'b0;
end
 
 
// Synchronizing
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      stall_bp_csff <= #1 1'b0;
      stall_bp_tck  <= #1 1'b0;
    end
  else
    begin
      stall_bp_csff <= #1 stall_bp;
      stall_bp_tck  <= #1 stall_bp_csff;
    end
end
 
 
always @ (posedge cpu_clk_i or posedge rst_i)
begin
  if (rst_i)
    begin
      stall_reg_csff <= #1 1'b0;
      stall_reg_cpu  <= #1 1'b0;
    end
  else
    begin
      stall_reg_csff <= #1 stall_reg;
      stall_reg_cpu  <= #1 stall_reg_csff;
    end
end
 
 
assign cpu_stall_o = bp_i | stall_bp | stall_reg_cpu;
 
 
// Writing data to the control registers (stall)
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    stall_reg <= #1 1'b0;
  else if (stall_bp_tck)
    stall_reg <= #1 1'b1;
  else if (we_i)
    stall_reg <= #1 data_i[0];
end
 
 
// Writing data to the control registers (reset)
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    cpu_reset  <= #1 1'b0;
  else if(we_i)
    cpu_reset  <= #1 data_i[1];
end
 
 
// Synchronizing signals from registers
always @ (posedge cpu_clk_i or posedge rst_i)
begin
  if (rst_i)
    begin
      cpu_reset_csff      <= #1 1'b0;
      cpu_rst_o           <= #1 1'b0;
    end
  else
    begin
      cpu_reset_csff      <= #1 cpu_reset;
      cpu_rst_o           <= #1 cpu_reset_csff;
    end
end
 
 
 
// Value for read back
assign ctrl_reg_o = {cpu_reset, stall_reg};
 
 
endmodule
 

Line No.	Rev	Author	Line
1	12	xianfeng	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_cpu_registers.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC Debug Interface. ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2004 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46			`// Revision 1.5 2004/03/22 16:35:46 igorm`
47			`// Temp version before changing dbg interface.`
48			`//`
49			`// Revision 1.4 2004/01/25 14:04:18 mohor`
50			`// All flipflops are reset.`
51			`//`
52			`// Revision 1.3 2004/01/22 10:16:08 mohor`
53			`// cpu_stall_o activated as soon as bp occurs.`
54			`//`
55			`// Revision 1.2 2004/01/17 17:01:14 mohor`
56			`// Almost finished.`
57			`//`
58			`// Revision 1.1 2004/01/16 14:53:33 mohor`
59			`// * empty log message *`
60			`//`
61			`//`
62			`//`
63
64			`// synopsys translate_off`
65			`include "timescale.v"
66			`// synopsys translate_on`
67			`include "dbg_cpu_defines.v"
68
69			`module dbg_cpu_registers (`
70			`data_i,`
71			`we_i,`
72			`tck_i,`
73			`bp_i,`
74			`rst_i,`
75			`cpu_clk_i,`
76			`ctrl_reg_o,`
77			`cpu_stall_o,`
78			`cpu_rst_o`
79			`);`
80
81
82			input [`DBG_CPU_CTRL_LEN -1:0] data_i;
83			`input we_i;`
84			`input tck_i;`
85			`input bp_i;`
86			`input rst_i;`
87			`input cpu_clk_i;`
88
89			output [`DBG_CPU_CTRL_LEN -1:0]ctrl_reg_o;
90			`output cpu_stall_o;`
91			`output cpu_rst_o;`
92
93			`reg cpu_reset;`
94			`wire [2:1] cpu_op_out;`
95
96			`reg stall_bp, stall_bp_csff, stall_bp_tck;`
97			`reg stall_reg, stall_reg_csff, stall_reg_cpu;`
98			`reg cpu_reset_csff;`
99			`reg cpu_rst_o;`
100
101
102
103			`// Breakpoint is latched and synchronized. Stall is set and latched.`
104			`always @ (posedge cpu_clk_i or posedge rst_i)`
105			`begin`
106			`if(rst_i)`
107			`stall_bp <= #1 1'b0;`
108			`else if(bp_i)`
109			`stall_bp <= #1 1'b1;`
110			`else if(stall_reg_cpu)`
111			`stall_bp <= #1 1'b0;`
112			`end`
113
114
115			`// Synchronizing`
116			`always @ (posedge tck_i or posedge rst_i)`
117			`begin`
118			`if (rst_i)`
119			`begin`
120			`stall_bp_csff <= #1 1'b0;`
121			`stall_bp_tck <= #1 1'b0;`
122			`end`
123			`else`
124			`begin`
125			`stall_bp_csff <= #1 stall_bp;`
126			`stall_bp_tck <= #1 stall_bp_csff;`
127			`end`
128			`end`
129
130
131			`always @ (posedge cpu_clk_i or posedge rst_i)`
132			`begin`
133			`if (rst_i)`
134			`begin`
135			`stall_reg_csff <= #1 1'b0;`
136			`stall_reg_cpu <= #1 1'b0;`
137			`end`
138			`else`
139			`begin`
140			`stall_reg_csff <= #1 stall_reg;`
141			`stall_reg_cpu <= #1 stall_reg_csff;`
142			`end`
143			`end`
144
145
146			`assign cpu_stall_o = bp_i \| stall_bp \| stall_reg_cpu;`
147
148
149			`// Writing data to the control registers (stall)`
150			`always @ (posedge tck_i or posedge rst_i)`
151			`begin`
152			`if (rst_i)`
153			`stall_reg <= #1 1'b0;`
154			`else if (stall_bp_tck)`
155			`stall_reg <= #1 1'b1;`
156			`else if (we_i)`
157			`stall_reg <= #1 data_i[0];`
158			`end`
159
160
161			`// Writing data to the control registers (reset)`
162			`always @ (posedge tck_i or posedge rst_i)`
163			`begin`
164			`if (rst_i)`
165			`cpu_reset <= #1 1'b0;`
166			`else if(we_i)`
167			`cpu_reset <= #1 data_i[1];`
168			`end`
169
170
171			`// Synchronizing signals from registers`
172			`always @ (posedge cpu_clk_i or posedge rst_i)`
173			`begin`
174			`if (rst_i)`
175			`begin`
176			`cpu_reset_csff <= #1 1'b0;`
177			`cpu_rst_o <= #1 1'b0;`
178			`end`
179			`else`
180			`begin`
181			`cpu_reset_csff <= #1 cpu_reset;`
182			`cpu_rst_o <= #1 cpu_reset_csff;`
183			`end`
184			`end`
185
186
187
188			`// Value for read back`
189			`assign ctrl_reg_o = {cpu_reset, stall_reg};`
190
191
192			`endmodule`
193

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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [dbg_interface/] [rtl/] [verilog/] [dbg_cpu_registers.v] - Blame information for rev 12