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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [flash_sram/] [sram_top.v.orig] - Blame information for rev 12

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  XESS SRAM interface                                         ////
////                                                              ////
////  This file is part of the OR1K test application              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Connects the SoC to SRAM. It does RMW for byte accesses     ////
////  because XSV board has WEs on a 16-bit basis.                ////
////                                                              ////
////  To Do:                                                      ////
////   - nothing really                                           ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Srot, simons@opencores.org                      ////
////      - Igor Mohor, igorm@opencores.org                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: sram_top.v,v $
// Revision 1.7  2004/04/05 08:44:55  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.5  2002/09/16 02:51:23  lampret
// Delayed wb_err_o. Disabled wb_ack_o when wb_err_o is asserted.
//
// Revision 1.4  2002/08/18 19:55:30  lampret
// Added variable delay for SRAM.
//
// Revision 1.3  2002/08/14 06:24:43  lampret
// Fixed size of generic flash/sram to exactly 2MB
//
// Revision 1.2  2002/08/12 05:34:06  lampret
// Added SRAM_GENERIC
//
// Revision 1.1.1.1  2002/03/21 16:55:44  lampret
// First import of the "new" XESS XSV environment.
//
//
// Revision 1.3  2002/01/23 07:50:44  lampret
// Added wb_err_o to flash and sram i/f for testing the buserr exception.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1.1.1  2001/11/04 19:00:09  lampret
// First import.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
`ifdef SRAM_GENERIC
 
module sram_top (
  wb_clk_i, wb_rst_i,
 
  wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
  wb_stb_i, wb_ack_o, wb_err_o,
 
  r_cen, r0_wen, r1_wen, r_oen, r_a, r_d_i, r_d_o, d_oe,
  l_cen, l0_wen, l1_wen, l_oen, l_a, l_d_i, l_d_o
);
 
//
// Paraneters
//
parameter               aw = 19;
 
//
// I/O Ports
//
input                   wb_clk_i;
input                   wb_rst_i;
 
//
// WB slave i/f
//
input   [31:0]          wb_dat_i;
output  [31:0]          wb_dat_o;
input   [31:0]          wb_adr_i;
input   [3:0]           wb_sel_i;
input                   wb_we_i;
input                   wb_cyc_i;
input                   wb_stb_i;
output                  wb_ack_o;
output                  wb_err_o;
 
//
// Right SRAM bank
//
output                  r_oen;
output                  r0_wen;
output                  r1_wen;
output                  r_cen;
input   [15:0]          r_d_i;
output  [15:0]          r_d_o;
output  [aw-1:0]        r_a;
 
//
// Left SRAM bank
//
output                  l_oen;
output                  l0_wen;
output                  l1_wen;
output                  l_cen;
input   [15:0]          l_d_i;
output  [15:0]          l_d_o;
output  [aw-1:0]        l_a;
 
//
// Common SRAM signals
//
output                  d_oe;
 
//
// Internal wires and regs
//
reg     [7:0]           mem [16*1024*1024-1:0];
integer                 i;
wire    [31:0]          adr;
`ifdef SRAM_GENERIC_REGISTERED
reg                     wb_err_o;
reg     [31:0]          prev_adr;
reg     [1:0]           delay;
`else
wire    [1:0]           delay;
`endif
wire                    wb_err;
 
//
// Aliases and simple assignments
//
assign wb_err = wb_cyc_i & wb_stb_i & (delay == 2'd0) & (|wb_adr_i[26:24]);     // If Access to > 16MB (8-bit leading prefix ignored)
assign adr = {5'b00000, wb_adr_i[26:2], 2'b00};
 
//
// Reading from SRAM model
//
assign wb_dat_o[7:0] = mem[adr+3];
assign wb_dat_o[15:8] = mem[adr+2];
assign wb_dat_o[23:16] = mem[adr+1];
assign wb_dat_o[31:24] = mem[adr+0];
 
//
// Writing to SRAM model
//
always @(posedge wb_rst_i or posedge wb_clk_i)
        if (wb_cyc_i & wb_stb_i & wb_we_i) begin
                if (wb_sel_i[0])
                        mem[adr+3] <= #1 wb_dat_i[7:0];
                if (wb_sel_i[1])
                        mem[adr+2] <= #1 wb_dat_i[15:8];
                if (wb_sel_i[2])
                        mem[adr+1] <= #1 wb_dat_i[23:16];
                if (wb_sel_i[3])
                        mem[adr+0] <= #1 wb_dat_i[31:24];
        end
 
`ifdef SRAM_GENERIC_REGISTERED
//
// WB Acknowledge
//
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i) begin
                delay <= #1 2'd3;
                prev_adr <= #1 32'h0000_0000;
        end
        else if (delay && (wb_adr_i == prev_adr) && wb_cyc_i && wb_stb_i)
                delay <= #1 delay - 2'd1;
        else if (wb_ack_o || wb_err_o || (wb_adr_i != prev_adr) || ~wb_stb_i) begin
                delay <= #1 2'd2;       // delay ... can range from 3 to 0
                prev_adr <= #1 wb_adr_i;
        end
`else
assign delay = 2'd0;
`endif
 
assign wb_ack_o = wb_cyc_i & wb_stb_i & ~wb_err & (delay == 2'd0)
`ifdef SRAM_GENERIC_REGISTERED
        & (wb_adr_i == prev_adr)
`endif
        ;
 
`ifdef SRAM_GENERIC_REGISTERED
//
// WB Error
//
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_err_o <= #1 1'b0;
        else
                wb_err_o <= #1 wb_err & !wb_err_o;
`else
assign wb_err_o = wb_err;
`endif
 
//
// SRAM i/f monitor
//
// synopsys translate_off
integer fsram;
initial begin
        fsram = $fopen("sram.log");
 
        $display("Cleaning SRAM.....");
//      for (i = 0; i < 16777216; i = i + 1)
//              mem[i] = 0;
 
        $readmemh("../src/sram.in", mem, 0);
end
always @(posedge wb_clk_i)
        if (wb_cyc_i)
                if (wb_stb_i & wb_we_i) begin
                        if (wb_sel_i[3])
                                mem[{wb_adr_i[23:2], 2'b00}+0] = wb_dat_i[31:24];
                        if (wb_sel_i[2])
                                mem[{wb_adr_i[23:2], 2'b00}+1] = wb_dat_i[23:16];
                        if (wb_sel_i[1])
                                mem[{wb_adr_i[23:2], 2'b00}+2] = wb_dat_i[15:8];
                        if (wb_sel_i[0])
                                mem[{wb_adr_i[23:2], 2'b00}+3] = wb_dat_i[7:0];
                        $fdisplay(fsram, "%t [%h] <- write %h, byte sel %b", $time, wb_adr_i, wb_dat_i, wb_sel_i);
                end else if (wb_ack_o)
                        $fdisplay(fsram, "%t [%h] -> read %h", $time, wb_adr_i, wb_dat_o);
// synopsys translate_on
 
endmodule
 
`else
 
module sram_top (
  wb_clk_i, wb_rst_i,
 
  wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
  wb_stb_i, wb_ack_o, wb_err_o,
 
  r_cen, r0_wen, r1_wen, r_oen, r_a, r_d_i, r_d_o, d_oe,
  l_cen, l0_wen, l1_wen, l_oen, l_a, l_d_i, l_d_o
);
 
//
// Paraneters
//
parameter               aw = 19;
 
//
// I/O Ports
//
input                   wb_clk_i;
input                   wb_rst_i;
 
//
// WB slave i/f
//
input   [31:0]          wb_dat_i;
output  [31:0]          wb_dat_o;
input   [31:0]          wb_adr_i;
input   [3:0]           wb_sel_i;
input                   wb_we_i;
input                   wb_cyc_i;
input                   wb_stb_i;
output                  wb_ack_o;
output                  wb_err_o;
 
//
// Right SRAM bank
//
output                  r_oen;
output                  r0_wen;
output                  r1_wen;
output                  r_cen;
input   [15:0]          r_d_i;
output  [15:0]          r_d_o;
output  [aw-1:0]        r_a;
 
//
// Left SRAM bank
//
output                  l_oen;
output                  l0_wen;
output                  l1_wen;
output                  l_cen;
input   [15:0]          l_d_i;
output  [15:0]          l_d_o;
output  [aw-1:0]        l_a;
 
//
// Common SRAM signals
//
output                  d_oe;
 
//
// Internal regs and wires
//
reg     [15:0]          r_data;
reg     [15:0]          l_data;
reg                     l0_wen;
wire                    l1_wen = l0_wen;
reg                     r0_wen;
wire                    r1_wen = r0_wen;
reg     [31:0]          latch_data;
reg                     ack_we;
wire                    l_oe;
wire                    r_oe;
wire                    r_ack;
reg                     Mux;
reg     [aw-1:0]        LatchedAddr;
reg     [15:0]          l_read;
reg     [15:0]          r_read;
reg                     d_oe;
reg     [15:0]          l_mux;
reg     [15:0]          r_mux;
 
//
// Aliases and simple assignments
//
assign wb_dat_o = {r_d_i, l_d_i};
assign l_oen = ~l_oe;
assign r_oen = ~r_oe;
assign l_a = Mux ? LatchedAddr : wb_adr_i[aw+1:2];
assign r_a = l_a;
assign l_d_o = l_mux;
assign r_d_o = r_mux;
assign l_oe = wb_cyc_i & wb_stb_i & l0_wen;
assign r_oe = wb_cyc_i & wb_stb_i & r0_wen;
assign l_cen = ~(wb_cyc_i & wb_stb_i);
assign r_cen = l_cen;
assign wb_ack_o = (wb_cyc_i & wb_stb_i & ~wb_err & ~wb_we_i) | ack_we;
assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[27:21]);    // If Access to > 2MB (4-bit leading prefix ignored)
 
//
// RMW mux control
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    Mux <= 1'b0;
  else
  if (ack_we)
    Mux <= #1 1'b1;
  else
    Mux <= #1 1'b0;
end
 
//
// Latch address
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    LatchedAddr <= 'h0;
  else
  if (wb_cyc_i & wb_stb_i)
    LatchedAddr <= #1 wb_adr_i[aw+1:2];
end
 
//
// Latch data from RAM (read data)
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    begin
      l_read <= 16'h0;
      r_read <= 16'h0;
    end
  else
  if (wb_cyc_i & wb_stb_i)
    begin
      l_read <= #1 l_d_i[15:0];
      r_read <= #1 r_d_i[15:0];
    end
end
 
//
// Mux and latch data for writing left SRAM bank (bytes 0 and 1)
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    l_mux <= 16'h0;
  else
  if (~l0_wen)
    begin
      if (wb_sel_i[0])
        l_mux[7:0]  <= #1 wb_dat_i[7:0];
      else
        l_mux[7:0]  <= #1 l_read[7:0];
      if (wb_sel_i[1])
        l_mux[15:8] <= #1 wb_dat_i[15:8];
      else
        l_mux[15:8] <= #1 l_read[15:8];
    end
  else
    l_mux[15:0]  <= #1 16'hz;
end
 
//
// Mux and latch data for writing right SRAM bank (bytes 2 and 3)
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    r_mux <= 16'h0;
  else
  if (~r0_wen)
    begin
      if (wb_sel_i[2])
        r_mux[7:0]  <= #1 wb_dat_i[23:16];
      else
        r_mux[7:0]  <= #1 r_read[7:0];
      if (wb_sel_i[3])
        r_mux[15:8]  <= #1 wb_dat_i[31:24];
      else
        r_mux[15:8]  <= #1 r_read[15:8];
    end
  else
    r_mux <= #1 16'hz;
end
 
//
// Left WE
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    l0_wen <= 1'b1;
  else
  if (wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[1:0]) & ~wb_ack_o)
    l0_wen <= #1 1'b0;
  else
    l0_wen <= #1 1'b1;
end
 
//
// Right WE
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    r0_wen <= 1'b1;
  else
  if (wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:2]) & ~wb_ack_o)
    r0_wen <= #1 1'b0;
  else
    r0_wen <= #1 1'b1;
end
 
//
// Write acknowledge
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    ack_we <= 1'b0;
  else
  if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)
    ack_we <= #1 1'b1;
  else
    ack_we <= #1 1'b0;
end
 
//
// Generate d_oe signal (tristate control)
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    d_oe <= 1'b0;
  else
  if (~l0_wen | ~r0_wen)
    d_oe <= 1'b1;
  else
    d_oe <= 1'b0;
end
 
//
// SRAM i/f monitor
//
// synopsys translate_off
integer fsram;
initial fsram = $fopen("sram.log");
always @(posedge wb_clk_i)
begin
  if (~l0_wen | ~r0_wen)
    $fdisplay(fsram, "%t [%h] <- write %h", $time, wb_adr_i, {r_d_o, l_d_o});
  else
  if ((l_oe | r_oe) & ~wb_we_i)
    $fdisplay(fsram, "%t [%h] -> read %h", $time, wb_adr_i, {r_d_i, l_d_i});
end
// synopsys translate_on
 
endmodule
 
`endif

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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [flash_sram/] [sram_top.v.orig] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	xianfeng	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// XESS SRAM interface ////`
4			`//// ////`
5			`//// This file is part of the OR1K test application ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Connects the SoC to SRAM. It does RMW for byte accesses ////`
10			`//// because XSV board has WEs on a 16-bit basis. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// - nothing really ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Simon Srot, simons@opencores.org ////`
17			`//// - Igor Mohor, igorm@opencores.org ////`
18			`//// ////`
19			`//////////////////////////////////////////////////////////////////////`
20			`//// ////`
21			`//// Copyright (C) 2001 Authors ////`
22			`//// ////`
23			`//// This source file may be used and distributed without ////`
24			`//// restriction provided that this copyright statement is not ////`
25			`//// removed from the file and that any derivative work contains ////`
26			`//// the original copyright notice and the associated disclaimer. ////`
27			`//// ////`
28			`//// This source file is free software; you can redistribute it ////`
29			`//// and/or modify it under the terms of the GNU Lesser General ////`
30			`//// Public License as published by the Free Software Foundation; ////`
31			`//// either version 2.1 of the License, or (at your option) any ////`
32			`//// later version. ////`
33			`//// ////`
34			`//// This source is distributed in the hope that it will be ////`
35			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
36			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
37			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
38			`//// details. ////`
39			`//// ////`
40			`//// You should have received a copy of the GNU Lesser General ////`
41			`//// Public License along with this source; if not, download it ////`
42			`//// from http://www.opencores.org/lgpl.shtml ////`
43			`//// ////`
44			`//////////////////////////////////////////////////////////////////////`
45			`//`
46			`// CVS Revision History`
47			`//`
48			`// $Log: sram_top.v,v $`
49			`// Revision 1.7 2004/04/05 08:44:55 lampret`
50			`// Merged branch_qmem into main tree.`
51			`//`
52			`// Revision 1.5 2002/09/16 02:51:23 lampret`
53			`// Delayed wb_err_o. Disabled wb_ack_o when wb_err_o is asserted.`
54			`//`
55			`// Revision 1.4 2002/08/18 19:55:30 lampret`
56			`// Added variable delay for SRAM.`
57			`//`
58			`// Revision 1.3 2002/08/14 06:24:43 lampret`
59			`// Fixed size of generic flash/sram to exactly 2MB`
60			`//`
61			`// Revision 1.2 2002/08/12 05:34:06 lampret`
62			`// Added SRAM_GENERIC`
63			`//`
64			`// Revision 1.1.1.1 2002/03/21 16:55:44 lampret`
65			`// First import of the "new" XESS XSV environment.`
66			`//`
67			`//`
68			`// Revision 1.3 2002/01/23 07:50:44 lampret`
69			`// Added wb_err_o to flash and sram i/f for testing the buserr exception.`
70			`//`
71			`// Revision 1.2 2002/01/14 06:18:22 lampret`
72			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
73			`//`
74			`// Revision 1.1.1.1 2001/11/04 19:00:09 lampret`
75			`// First import.`
76			`//`
77			`//`
78
79			`// synopsys translate_off`
80			`include "timescale.v"
81			`// synopsys translate_on`
82
83			`ifdef SRAM_GENERIC
84
85			`module sram_top (`
86			`wb_clk_i, wb_rst_i,`
87
88			`wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,`
89			`wb_stb_i, wb_ack_o, wb_err_o,`
90
91			`r_cen, r0_wen, r1_wen, r_oen, r_a, r_d_i, r_d_o, d_oe,`
92			`l_cen, l0_wen, l1_wen, l_oen, l_a, l_d_i, l_d_o`
93			`);`
94
95			`//`
96			`// Paraneters`
97			`//`
98			`parameter aw = 19;`
99
100			`//`
101			`// I/O Ports`
102			`//`
103			`input wb_clk_i;`
104			`input wb_rst_i;`
105
106			`//`
107			`// WB slave i/f`
108			`//`
109			`input [31:0] wb_dat_i;`
110			`output [31:0] wb_dat_o;`
111			`input [31:0] wb_adr_i;`
112			`input [3:0] wb_sel_i;`
113			`input wb_we_i;`
114			`input wb_cyc_i;`
115			`input wb_stb_i;`
116			`output wb_ack_o;`
117			`output wb_err_o;`
118
119			`//`
120			`// Right SRAM bank`
121			`//`
122			`output r_oen;`
123			`output r0_wen;`
124			`output r1_wen;`
125			`output r_cen;`
126			`input [15:0] r_d_i;`
127			`output [15:0] r_d_o;`
128			`output [aw-1:0] r_a;`
129
130			`//`
131			`// Left SRAM bank`
132			`//`
133			`output l_oen;`
134			`output l0_wen;`
135			`output l1_wen;`
136			`output l_cen;`
137			`input [15:0] l_d_i;`
138			`output [15:0] l_d_o;`
139			`output [aw-1:0] l_a;`
140
141			`//`
142			`// Common SRAM signals`
143			`//`
144			`output d_oe;`
145
146			`//`
147			`// Internal wires and regs`
148			`//`
149			`reg [7:0] mem [1610241024-1:0];`
150			`integer i;`
151			`wire [31:0] adr;`
152			`ifdef SRAM_GENERIC_REGISTERED
153			`reg wb_err_o;`
154			`reg [31:0] prev_adr;`
155			`reg [1:0] delay;`
156			`else
157			`wire [1:0] delay;`
158			`endif
159			`wire wb_err;`
160
161			`//`
162			`// Aliases and simple assignments`
163			`//`
164			`assign wb_err = wb_cyc_i & wb_stb_i & (delay == 2'd0) & (\|wb_adr_i[26:24]); // If Access to > 16MB (8-bit leading prefix ignored)`
165			`assign adr = {5'b00000, wb_adr_i[26:2], 2'b00};`
166
167			`//`
168			`// Reading from SRAM model`
169			`//`
170			`assign wb_dat_o[7:0] = mem[adr+3];`
171			`assign wb_dat_o[15:8] = mem[adr+2];`
172			`assign wb_dat_o[23:16] = mem[adr+1];`
173			`assign wb_dat_o[31:24] = mem[adr+0];`
174
175			`//`
176			`// Writing to SRAM model`
177			`//`
178			`always @(posedge wb_rst_i or posedge wb_clk_i)`
179			`if (wb_cyc_i & wb_stb_i & wb_we_i) begin`
180			`if (wb_sel_i[0])`
181			`mem[adr+3] <= #1 wb_dat_i[7:0];`
182			`if (wb_sel_i[1])`
183			`mem[adr+2] <= #1 wb_dat_i[15:8];`
184			`if (wb_sel_i[2])`
185			`mem[adr+1] <= #1 wb_dat_i[23:16];`
186			`if (wb_sel_i[3])`
187			`mem[adr+0] <= #1 wb_dat_i[31:24];`
188			`end`
189
190			`ifdef SRAM_GENERIC_REGISTERED
191			`//`
192			`// WB Acknowledge`
193			`//`
194			`always @(posedge wb_clk_i or posedge wb_rst_i)`
195			`if (wb_rst_i) begin`
196			`delay <= #1 2'd3;`
197			`prev_adr <= #1 32'h0000_0000;`
198			`end`
199			`else if (delay && (wb_adr_i == prev_adr) && wb_cyc_i && wb_stb_i)`
200			`delay <= #1 delay - 2'd1;`
201			`else if (wb_ack_o \|\| wb_err_o \|\| (wb_adr_i != prev_adr) \|\| ~wb_stb_i) begin`
202			`delay <= #1 2'd2; // delay ... can range from 3 to 0`
203			`prev_adr <= #1 wb_adr_i;`
204			`end`
205			`else
206			`assign delay = 2'd0;`
207			`endif
208
209			`assign wb_ack_o = wb_cyc_i & wb_stb_i & ~wb_err & (delay == 2'd0)`
210			`ifdef SRAM_GENERIC_REGISTERED
211			`& (wb_adr_i == prev_adr)`
212			`endif
213			`;`
214
215			`ifdef SRAM_GENERIC_REGISTERED
216			`//`
217			`// WB Error`
218			`//`
219			`always @(posedge wb_clk_i or posedge wb_rst_i)`
220			`if (wb_rst_i)`
221			`wb_err_o <= #1 1'b0;`
222			`else`
223			`wb_err_o <= #1 wb_err & !wb_err_o;`
224			`else
225			`assign wb_err_o = wb_err;`
226			`endif
227
228			`//`
229			`// SRAM i/f monitor`
230			`//`
231			`// synopsys translate_off`
232			`integer fsram;`
233			`initial begin`
234			`fsram = $fopen("sram.log");`
235
236			`$display("Cleaning SRAM.....");`
237			`// for (i = 0; i < 16777216; i = i + 1)`
238			`// mem[i] = 0;`
239
240			`$readmemh("../src/sram.in", mem, 0);`
241			`end`
242			`always @(posedge wb_clk_i)`
243			`if (wb_cyc_i)`
244			`if (wb_stb_i & wb_we_i) begin`
245			`if (wb_sel_i[3])`
246			`mem[{wb_adr_i[23:2], 2'b00}+0] = wb_dat_i[31:24];`
247			`if (wb_sel_i[2])`
248			`mem[{wb_adr_i[23:2], 2'b00}+1] = wb_dat_i[23:16];`
249			`if (wb_sel_i[1])`
250			`mem[{wb_adr_i[23:2], 2'b00}+2] = wb_dat_i[15:8];`
251			`if (wb_sel_i[0])`
252			`mem[{wb_adr_i[23:2], 2'b00}+3] = wb_dat_i[7:0];`
253			`$fdisplay(fsram, "%t [%h] <- write %h, byte sel %b", $time, wb_adr_i, wb_dat_i, wb_sel_i);`
254			`end else if (wb_ack_o)`
255			`$fdisplay(fsram, "%t [%h] -> read %h", $time, wb_adr_i, wb_dat_o);`
256			`// synopsys translate_on`
257
258			`endmodule`
259
260			`else
261
262			`module sram_top (`
263			`wb_clk_i, wb_rst_i,`
264
265			`wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,`
266			`wb_stb_i, wb_ack_o, wb_err_o,`
267
268			`r_cen, r0_wen, r1_wen, r_oen, r_a, r_d_i, r_d_o, d_oe,`
269			`l_cen, l0_wen, l1_wen, l_oen, l_a, l_d_i, l_d_o`
270			`);`
271
272			`//`
273			`// Paraneters`
274			`//`
275			`parameter aw = 19;`
276
277			`//`
278			`// I/O Ports`
279			`//`
280			`input wb_clk_i;`
281			`input wb_rst_i;`
282
283			`//`
284			`// WB slave i/f`
285			`//`
286			`input [31:0] wb_dat_i;`
287			`output [31:0] wb_dat_o;`
288			`input [31:0] wb_adr_i;`
289			`input [3:0] wb_sel_i;`
290			`input wb_we_i;`
291			`input wb_cyc_i;`
292			`input wb_stb_i;`
293			`output wb_ack_o;`
294			`output wb_err_o;`
295
296			`//`
297			`// Right SRAM bank`
298			`//`
299			`output r_oen;`
300			`output r0_wen;`
301			`output r1_wen;`
302			`output r_cen;`
303			`input [15:0] r_d_i;`
304			`output [15:0] r_d_o;`
305			`output [aw-1:0] r_a;`
306
307			`//`
308			`// Left SRAM bank`
309			`//`
310			`output l_oen;`
311			`output l0_wen;`
312			`output l1_wen;`
313			`output l_cen;`
314			`input [15:0] l_d_i;`
315			`output [15:0] l_d_o;`
316			`output [aw-1:0] l_a;`
317
318			`//`
319			`// Common SRAM signals`
320			`//`
321			`output d_oe;`
322
323			`//`
324			`// Internal regs and wires`
325			`//`
326			`reg [15:0] r_data;`
327			`reg [15:0] l_data;`
328			`reg l0_wen;`
329			`wire l1_wen = l0_wen;`
330			`reg r0_wen;`
331			`wire r1_wen = r0_wen;`
332			`reg [31:0] latch_data;`
333			`reg ack_we;`
334			`wire l_oe;`
335			`wire r_oe;`
336			`wire r_ack;`
337			`reg Mux;`
338			`reg [aw-1:0] LatchedAddr;`
339			`reg [15:0] l_read;`
340			`reg [15:0] r_read;`
341			`reg d_oe;`
342			`reg [15:0] l_mux;`
343			`reg [15:0] r_mux;`
344
345			`//`
346			`// Aliases and simple assignments`
347			`//`
348			`assign wb_dat_o = {r_d_i, l_d_i};`
349			`assign l_oen = ~l_oe;`
350			`assign r_oen = ~r_oe;`
351			`assign l_a = Mux ? LatchedAddr : wb_adr_i[aw+1:2];`
352			`assign r_a = l_a;`
353			`assign l_d_o = l_mux;`
354			`assign r_d_o = r_mux;`
355			`assign l_oe = wb_cyc_i & wb_stb_i & l0_wen;`
356			`assign r_oe = wb_cyc_i & wb_stb_i & r0_wen;`
357			`assign l_cen = ~(wb_cyc_i & wb_stb_i);`
358			`assign r_cen = l_cen;`
359			`assign wb_ack_o = (wb_cyc_i & wb_stb_i & ~wb_err & ~wb_we_i) \| ack_we;`
360			`assign wb_err_o = wb_cyc_i & wb_stb_i & (\|wb_adr_i[27:21]); // If Access to > 2MB (4-bit leading prefix ignored)`
361
362			`//`
363			`// RMW mux control`
364			`//`
365			`always @ (negedge wb_clk_i or posedge wb_rst_i)`
366			`begin`
367			`if (wb_rst_i)`
368			`Mux <= 1'b0;`
369			`else`
370			`if (ack_we)`
371			`Mux <= #1 1'b1;`
372			`else`
373			`Mux <= #1 1'b0;`
374			`end`
375
376			`//`
377			`// Latch address`
378			`//`
379			`always @ (negedge wb_clk_i or posedge wb_rst_i)`
380			`begin`
381			`if (wb_rst_i)`
382			`LatchedAddr <= 'h0;`
383			`else`
384			`if (wb_cyc_i & wb_stb_i)`
385			`LatchedAddr <= #1 wb_adr_i[aw+1:2];`
386			`end`
387
388			`//`
389			`// Latch data from RAM (read data)`
390			`//`
391			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
392			`begin`
393			`if (wb_rst_i)`
394			`begin`
395			`l_read <= 16'h0;`
396			`r_read <= 16'h0;`
397			`end`
398			`else`
399			`if (wb_cyc_i & wb_stb_i)`
400			`begin`
401			`l_read <= #1 l_d_i[15:0];`
402			`r_read <= #1 r_d_i[15:0];`
403			`end`
404			`end`
405
406			`//`
407			`// Mux and latch data for writing left SRAM bank (bytes 0 and 1)`
408			`//`
409			`always @ (negedge wb_clk_i or posedge wb_rst_i)`
410			`begin`
411			`if (wb_rst_i)`
412			`l_mux <= 16'h0;`
413			`else`
414			`if (~l0_wen)`
415			`begin`
416			`if (wb_sel_i[0])`
417			`l_mux[7:0] <= #1 wb_dat_i[7:0];`
418			`else`
419			`l_mux[7:0] <= #1 l_read[7:0];`
420			`if (wb_sel_i[1])`
421			`l_mux[15:8] <= #1 wb_dat_i[15:8];`
422			`else`
423			`l_mux[15:8] <= #1 l_read[15:8];`
424			`end`
425			`else`
426			`l_mux[15:0] <= #1 16'hz;`
427			`end`
428
429			`//`
430			`// Mux and latch data for writing right SRAM bank (bytes 2 and 3)`
431			`//`
432			`always @ (negedge wb_clk_i or posedge wb_rst_i)`
433			`begin`
434			`if (wb_rst_i)`
435			`r_mux <= 16'h0;`
436			`else`
437			`if (~r0_wen)`
438			`begin`
439			`if (wb_sel_i[2])`
440			`r_mux[7:0] <= #1 wb_dat_i[23:16];`
441			`else`
442			`r_mux[7:0] <= #1 r_read[7:0];`
443			`if (wb_sel_i[3])`
444			`r_mux[15:8] <= #1 wb_dat_i[31:24];`
445			`else`
446			`r_mux[15:8] <= #1 r_read[15:8];`
447			`end`
448			`else`
449			`r_mux <= #1 16'hz;`
450			`end`
451
452			`//`
453			`// Left WE`
454			`//`
455			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
456			`begin`
457			`if (wb_rst_i)`
458			`l0_wen <= 1'b1;`
459			`else`
460			`if (wb_cyc_i & wb_stb_i & wb_we_i & (\|wb_sel_i[1:0]) & ~wb_ack_o)`
461			`l0_wen <= #1 1'b0;`
462			`else`
463			`l0_wen <= #1 1'b1;`
464			`end`
465
466			`//`
467			`// Right WE`
468			`//`
469			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
470			`begin`
471			`if (wb_rst_i)`
472			`r0_wen <= 1'b1;`
473			`else`
474			`if (wb_cyc_i & wb_stb_i & wb_we_i & (\|wb_sel_i[3:2]) & ~wb_ack_o)`
475			`r0_wen <= #1 1'b0;`
476			`else`
477			`r0_wen <= #1 1'b1;`
478			`end`
479
480			`//`
481			`// Write acknowledge`
482			`//`
483			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
484			`begin`
485			`if (wb_rst_i)`
486			`ack_we <= 1'b0;`
487			`else`
488			`if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)`
489			`ack_we <= #1 1'b1;`
490			`else`
491			`ack_we <= #1 1'b0;`
492			`end`
493
494			`//`
495			`// Generate d_oe signal (tristate control)`
496			`//`
497			`always @ (negedge wb_clk_i or posedge wb_rst_i)`
498			`begin`
499			`if (wb_rst_i)`
500			`d_oe <= 1'b0;`
501			`else`
502			`if (~l0_wen \| ~r0_wen)`
503			`d_oe <= 1'b1;`
504			`else`
505			`d_oe <= 1'b0;`
506			`end`
507
508			`//`
509			`// SRAM i/f monitor`
510			`//`
511			`// synopsys translate_off`
512			`integer fsram;`
513			`initial fsram = $fopen("sram.log");`
514			`always @(posedge wb_clk_i)`
515			`begin`
516			`if (~l0_wen \| ~r0_wen)`
517			`$fdisplay(fsram, "%t [%h] <- write %h", $time, wb_adr_i, {r_d_o, l_d_o});`
518			`else`
519			`if ((l_oe \| r_oe) & ~wb_we_i)`
520			`$fdisplay(fsram, "%t [%h] -> read %h", $time, wb_adr_i, {r_d_i, l_d_i});`
521			`end`
522			`// synopsys translate_on`
523
524			`endmodule`
525
526			`endif