OpenCores
URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [gpio/] [rtl/] [verilog/] [gpio_top.v] - Blame information for rev 12

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 12 xianfeng 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  WISHBONE General-Purpose I/O                                ////
4 
////                                                              ////
5 
////  This file is part of the GPIO project                       ////
6 
////  http://www.opencores.org/cores/gpio/                        ////
7 
////                                                              ////
8 
////  Description                                                 ////
9 
////  Implementation of GPIO IP core according to                 ////
10 
////  GPIO IP core specification document.                        ////
11 
////                                                              ////
12 
////  To Do:                                                      ////
13 
////   Nothing                                                    ////
14 
////                                                              ////
15 
////  Author(s):                                                  ////
16 
////      - Damjan Lampret, lampret@opencores.org                 ////
17 
////                                                              ////
18 
//////////////////////////////////////////////////////////////////////
19 
////                                                              ////
20 
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
21 
////                                                              ////
22 
//// This source file may be used and distributed without         ////
23 
//// restriction provided that this copyright statement is not    ////
24 
//// removed from the file and that any derivative work contains  ////
25 
//// the original copyright notice and the associated disclaimer. ////
26 
////                                                              ////
27 
//// This source file is free software; you can redistribute it   ////
28 
//// and/or modify it under the terms of the GNU Lesser General   ////
29 
//// Public License as published by the Free Software Foundation; ////
30 
//// either version 2.1 of the License, or (at your option) any   ////
31 
//// later version.                                               ////
32 
////                                                              ////
33 
//// This source is distributed in the hope that it will be       ////
34 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37 
//// details.                                                     ////
38 
////                                                              ////
39 
//// You should have received a copy of the GNU Lesser General    ////
40 
//// Public License along with this source; if not, download it   ////
41 
//// from http://www.opencores.org/lgpl.shtml                     ////
42 
////                                                              ////
43 
//////////////////////////////////////////////////////////////////////
44 
//
45 
// CVS Revision History
46 
//
47 
// $Log: not supported by cvs2svn $
48 
// Revision 1.17  2004/05/05 08:21:00  andreje
49 
// Bugfixes when GPIO_RGPIO_ECLK/GPIO_RGPIO_NEC disabled, gpio oe name change and set to active-high according to spec
50 
//
51 
// Revision 1.16  2003/12/17 13:00:52  gorand
52 
// added ECLK and NEC registers, all tests passed.
53 
//
54 
// Revision 1.15  2003/11/10 23:21:22  gorand
55 
// bug fixed. all tests passed.
56 
//
57 
// Revision 1.14  2003/11/06 13:59:07  gorand
58 
// added support for 8-bit access to registers.
59 
//
60 
// Revision 1.13  2002/11/18 22:35:18  lampret
61 
// Bug fix. Interrupts were also asserted when condition was not met.
62 
//
63 
// Revision 1.12  2002/11/11 21:36:28  lampret
64 
// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC].
65 
//
66 
// Revision 1.11  2002/03/13 20:56:28  lampret
67 
// Removed zero padding as per Avi Shamli suggestion.
68 
//
69 
// Revision 1.10  2002/03/13 20:47:57  lampret
70 
// Ports changed per Ran Aviram suggestions.
71 
//
72 
// Revision 1.9  2002/03/09 03:43:27  lampret
73 
// Interrupt is asserted only when an input changes (code patch by Jacob Gorban)
74 
//
75 
// Revision 1.8  2002/01/14 19:06:28  lampret
76 
// Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification.
77 
//
78 
// Revision 1.7  2001/12/25 17:21:21  lampret
79 
// Fixed two typos.
80 
//
81 
// Revision 1.6  2001/12/25 17:12:35  lampret
82 
// Added RGPIO_INTS.
83 
//
84 
// Revision 1.5  2001/12/12 20:35:53  lampret
85 
// Fixing style.
86 
//
87 
// Revision 1.4  2001/12/12 07:12:58  lampret
88 
// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS)
89 
//
90 
// Revision 1.3  2001/11/15 02:24:37  lampret
91 
// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.
92 
//
93 
// Revision 1.2  2001/10/31 02:26:51  lampret
94 
// Fixed wb_err_o.
95 
//
96 
// Revision 1.1  2001/09/18 18:49:07  lampret
97 
// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.
98 
//
99 
// Revision 1.1  2001/08/21 21:39:28  lampret
100 
// Changed directory structure, port names and drfines.
101 
//
102 
// Revision 1.2  2001/07/14 20:39:26  lampret
103 
// Better configurability.
104 
//
105 
// Revision 1.1  2001/06/05 07:45:26  lampret
106 
// Added initial RTL and test benches. There are still some issues with these files.
107 
//
108 
//
109 
 
110 
// synopsys translate_off
111 
//`include "timescale.v";
112 
`timescale 1ns / 1ns;
113 
// synopsys translate_on
114 
`include "gpio_defines.v"
115 
 
116 
module gpio_top(
117 
        // WISHBONE Interface
118 
        wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,
119 
        wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,
120 
 
121 
`ifdef GPIO_AUX_IMPLEMENT
122 
        // Auxiliary inputs interface
123 
        aux_i,
124 
`endif //  GPIO_AUX_IMPLEMENT
125 
 
126 
        // External GPIO Interface
127 
        ext_pad_i, ext_pad_o, ext_padoe_o
128 
`ifdef GPIO_CLKPAD
129 
  , clk_pad_i
130 
`endif
131 
);
132 
 
133 
parameter dw = 32;
134 
parameter aw = `GPIO_ADDRHH+1;
135 
parameter gw = `GPIO_IOS;
136 
//
137 
// WISHBONE Interface
138 
//
139 
input             wb_clk_i;     // Clock
140 
input             wb_rst_i;     // Reset
141 
input             wb_cyc_i;     // cycle valid input
142 
input   [aw-1:0] wb_adr_i;       // address bus inputs
143 
input   [dw-1:0] wb_dat_i;       // input data bus
144 
input     [3:0]     wb_sel_i;    // byte select inputs
145 
input             wb_we_i;      // indicates write transfer
146 
input             wb_stb_i;     // strobe input
147 
output  [dw-1:0]  wb_dat_o;      // output data bus
148 
output            wb_ack_o;     // normal termination
149 
output            wb_err_o;     // termination w/ error
150 
output            wb_inta_o;    // Interrupt request output
151 
 
152 
`ifdef GPIO_AUX_IMPLEMENT
153 
// Auxiliary Inputs Interface
154 
input     [gw-1:0]  aux_i;               // Auxiliary inputs
155 
`endif // GPIO_AUX_IMPLEMENT
156 
 
157 
//
158 
// External GPIO Interface
159 
//
160 
input   [gw-1:0]  ext_pad_i;     // GPIO Inputs
161 
`ifdef GPIO_CLKPAD
162 
input             clk_pad_i;    // GPIO Eclk
163 
`endif //  GPIO_CLKPAD
164 
output  [gw-1:0]  ext_pad_o;     // GPIO Outputs
165 
output  [gw-1:0]  ext_padoe_o;   // GPIO output drivers enables
166 
 
167 
`ifdef GPIO_IMPLEMENTED
168 
 
169 
//
170 
// GPIO Input Register (or no register)
171 
//
172 
`ifdef GPIO_RGPIO_IN
173 
reg     [gw-1:0] rgpio_in;       // RGPIO_IN register
174 
`else
175 
wire    [gw-1:0] rgpio_in;       // No register
176 
`endif
177 
 
178 
//
179 
// GPIO Output Register (or no register)
180 
//
181 
`ifdef GPIO_RGPIO_OUT
182 
reg     [gw-1:0] rgpio_out;      // RGPIO_OUT register
183 
`else
184 
wire    [gw-1:0] rgpio_out;      // No register
185 
`endif
186 
 
187 
//
188 
// GPIO Output Driver Enable Register (or no register)
189 
//
190 
`ifdef GPIO_RGPIO_OE
191 
reg     [gw-1:0] rgpio_oe;       // RGPIO_OE register
192 
`else
193 
wire    [gw-1:0] rgpio_oe;       // No register
194 
`endif
195 
 
196 
//
197 
// GPIO Interrupt Enable Register (or no register)
198 
//
199 
`ifdef GPIO_RGPIO_INTE
200 
reg     [gw-1:0] rgpio_inte;     // RGPIO_INTE register
201 
`else
202 
wire    [gw-1:0] rgpio_inte;     // No register
203 
`endif
204 
 
205 
//
206 
// GPIO Positive edge Triggered Register (or no register)
207 
//
208 
`ifdef GPIO_RGPIO_PTRIG
209 
reg     [gw-1:0] rgpio_ptrig;    // RGPIO_PTRIG register
210 
`else
211 
wire    [gw-1:0] rgpio_ptrig;    // No register
212 
`endif
213 
 
214 
//
215 
// GPIO Auxiliary select Register (or no register)
216 
//
217 
`ifdef GPIO_RGPIO_AUX
218 
reg     [gw-1:0] rgpio_aux;      // RGPIO_AUX register
219 
`else
220 
wire    [gw-1:0] rgpio_aux;      // No register
221 
`endif
222 
 
223 
//
224 
// GPIO Control Register (or no register)
225 
//
226 
`ifdef GPIO_RGPIO_CTRL
227 
reg     [1:0]            rgpio_ctrl;     // RGPIO_CTRL register
228 
`else
229 
wire    [1:0]            rgpio_ctrl;     // No register
230 
`endif
231 
 
232 
//
233 
// GPIO Interrupt Status Register (or no register)
234 
//
235 
`ifdef GPIO_RGPIO_INTS
236 
reg     [gw-1:0] rgpio_ints;     // RGPIO_INTS register
237 
`else
238 
wire    [gw-1:0] rgpio_ints;     // No register
239 
`endif
240 
 
241 
//
242 
// GPIO Enable Clock  Register (or no register)
243 
//
244 
`ifdef GPIO_RGPIO_ECLK
245 
reg     [gw-1:0] rgpio_eclk;     // RGPIO_ECLK register
246 
`else
247 
wire    [gw-1:0] rgpio_eclk;     // No register
248 
`endif
249 
 
250 
//
251 
// GPIO Active Negative Edge  Register (or no register)
252 
//
253 
`ifdef GPIO_RGPIO_NEC
254 
reg     [gw-1:0] rgpio_nec;      // RGPIO_NEC register
255 
`else
256 
wire    [gw-1:0] rgpio_nec;      // No register
257 
`endif
258 
 
259 
 
260 
//
261 
// Synchronization flops for input signals
262 
//
263 
`ifdef GPIO_SYNC_IN_WB
264 
reg  [gw-1:0]  sync      ,
265 
               ext_pad_s ;
266 
`else
267 
wire [gw-1:0]  ext_pad_s ;
268 
`endif
269 
 
270 
 
271 
 
272 
//
273 
// Internal wires & regs
274 
//
275 
wire            rgpio_out_sel;  // RGPIO_OUT select
276 
wire            rgpio_oe_sel; // RGPIO_OE select
277 
wire            rgpio_inte_sel; // RGPIO_INTE select
278 
wire            rgpio_ptrig_sel;// RGPIO_PTRIG select
279 
wire            rgpio_aux_sel;  // RGPIO_AUX select
280 
wire            rgpio_ctrl_sel; // RGPIO_CTRL select
281 
wire            rgpio_ints_sel; // RGPIO_INTS select
282 
wire            rgpio_eclk_sel ;
283 
wire            rgpio_nec_sel ;
284 
wire            full_decoding;  // Full address decoding qualification
285 
wire  [gw-1:0]  in_muxed; // Muxed inputs
286 
wire            wb_ack;   // WB Acknowledge
287 
wire            wb_err;   // WB Error
288 
wire            wb_inta;  // WB Interrupt
289 
reg   [dw-1:0]  wb_dat;   // WB Data out
290 
`ifdef GPIO_REGISTERED_WB_OUTPUTS
291 
reg             wb_ack_o; // WB Acknowledge
292 
reg             wb_err_o; // WB Error
293 
reg             wb_inta_o;  // WB Interrupt
294 
reg   [dw-1:0]  wb_dat_o; // WB Data out
295 
`endif
296 
wire  [gw-1:0]  out_pad;  // GPIO Outputs
297 
`ifdef GPIO_REGISTERED_IO_OUTPUTS
298 
reg   [gw-1:0]  ext_pad_o;  // GPIO Outputs
299 
`endif
300 
`ifdef GPIO_CLKPAD
301 
wire  [gw-1:0]  extc_in;  // Muxed inputs sampled by external clock
302 
wire  [gw-1:0]  pext_clk; // External clock for posedge flops
303 
reg   [gw-1:0]  pextc_sampled;  // Posedge external clock sampled inputs
304 
`ifdef GPIO_NO_NEGEDGE_FLOPS
305 
`ifdef GPIO_NO_CLKPAD_LOGIC
306 
`else
307 
reg   [gw-1:0]  nextc_sampled;  // Negedge external clock sampled inputs
308 
`endif //  GPIO_NO_CLKPAD_LOGIC
309 
`else
310 
reg   [gw-1:0]  nextc_sampled;  // Negedge external clock sampled inputs
311 
`endif
312 
`endif //  GPIO_CLKPAD
313 
 
314 
 
315 
//
316 
// All WISHBONE transfer terminations are successful except when:
317 
// a) full address decoding is enabled and address doesn't match
318 
//    any of the GPIO registers
319 
// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero
320 
//
321 
 
322 
//
323 
// WB Acknowledge
324 
//
325 
assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o;
326 
 
327 
//
328 
// Optional registration of WB Ack
329 
//
330 
`ifdef GPIO_REGISTERED_WB_OUTPUTS
331 
always @(posedge wb_clk_i or posedge wb_rst_i)
332 
        if (wb_rst_i)
333 
                wb_ack_o <= #1 1'b0;
334 
        else
335 
                wb_ack_o <= #1 wb_ack & ~wb_ack_o & (!wb_err) ;
336 
`else
337 
assign wb_ack_o = wb_ack;
338 
`endif
339 
 
340 
//
341 
// WB Error
342 
//
343 
`ifdef GPIO_FULL_DECODE
344 
`ifdef GPIO_STRICT_32BIT_ACCESS
345 
assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111));
346 
`else
347 
assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding;
348 
`endif
349 
`else
350 
`ifdef GPIO_STRICT_32BIT_ACCESS
351 
assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);
352 
`else
353 
assign wb_err = 1'b0;
354 
`endif
355 
`endif
356 
 
357 
//
358 
// Optional registration of WB error
359 
//
360 
`ifdef GPIO_REGISTERED_WB_OUTPUTS
361 
always @(posedge wb_clk_i or posedge wb_rst_i)
362 
        if (wb_rst_i)
363 
                wb_err_o <= #1 1'b0;
364 
        else
365 
                wb_err_o <= #1 wb_err & ~wb_err_o;
366 
`else
367 
assign wb_err_o = wb_err;
368 
`endif
369 
 
370 
//
371 
// Full address decoder
372 
//
373 
`ifdef GPIO_FULL_DECODE
374 
assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &
375 
                        (wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});
376 
`else
377 
assign full_decoding = 1'b1;
378 
`endif
379 
 
380 
//
381 
// GPIO registers address decoder
382 
//
383 
`ifdef GPIO_RGPIO_OUT
384 
assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;
385 
`endif
386 
`ifdef GPIO_RGPIO_OE
387 
assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
388 
`endif
389 
`ifdef GPIO_RGPIO_INTE
390 
assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
391 
`endif
392 
`ifdef GPIO_RGPIO_PTRIG
393 
assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
394 
`endif
395 
`ifdef GPIO_RGPIO_AUX
396 
assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
397 
`endif
398 
`ifdef GPIO_RGPIO_CTRL
399 
assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
400 
`endif
401 
`ifdef GPIO_RGPIO_INTS
402 
assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding;
403 
`endif
404 
`ifdef GPIO_RGPIO_ECLK
405 
assign rgpio_eclk_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_ECLK) & full_decoding;
406 
`endif
407 
`ifdef GPIO_RGPIO_NEC
408 
assign rgpio_nec_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_NEC) & full_decoding;
409 
`endif
410 
 
411 
 
412 
//
413 
// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit
414 
//
415 
`ifdef GPIO_RGPIO_CTRL
416 
always @(posedge wb_clk_i or posedge wb_rst_i)
417 
        if (wb_rst_i)
418 
                rgpio_ctrl <= #1 2'b0;
419 
        else if (rgpio_ctrl_sel && wb_we_i)
420 
                rgpio_ctrl <= #1 wb_dat_i[1:0];
421 
        else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
422 
                rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] | wb_inta_o;
423 
`else
424 
assign rgpio_ctrl = 2'h01;      // RGPIO_CTRL[EN] = 1
425 
`endif
426 
 
427 
//
428 
// Write to RGPIO_OUT
429 
//
430 
`ifdef GPIO_RGPIO_OUT
431 
always @(posedge wb_clk_i or posedge wb_rst_i)
432 
        if (wb_rst_i)
433 
                rgpio_out <= #1 {gw{1'b0}};
434 
        else if (rgpio_out_sel && wb_we_i)
435 
    begin
436 
`ifdef GPIO_STRICT_32BIT_ACCESS
437 
                rgpio_out <= #1 wb_dat_i[gw-1:0];
438 
`endif
439 
 
440 
`ifdef GPIO_WB_BYTES4
441 
     if ( wb_sel_i [3] == 1'b1 )
442 
       rgpio_out [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
443 
     if ( wb_sel_i [2] == 1'b1 )
444 
       rgpio_out [23:16] <= #1 wb_dat_i [23:16] ;
445 
     if ( wb_sel_i [1] == 1'b1 )
446 
       rgpio_out [15:8] <= #1 wb_dat_i [15:8] ;
447 
     if ( wb_sel_i [0] == 1'b1 )
448 
       rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;
449 
`endif
450 
`ifdef GPIO_WB_BYTES3
451 
     if ( wb_sel_i [2] == 1'b1 )
452 
       rgpio_out [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
453 
     if ( wb_sel_i [1] == 1'b1 )
454 
       rgpio_out [15:8] <= #1 wb_dat_i [15:8] ;
455 
     if ( wb_sel_i [0] == 1'b1 )
456 
       rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;
457 
`endif
458 
`ifdef GPIO_WB_BYTES2
459 
     if ( wb_sel_i [1] == 1'b1 )
460 
       rgpio_out [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
461 
     if ( wb_sel_i [0] == 1'b1 )
462 
       rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;
463 
`endif
464 
`ifdef GPIO_WB_BYTES1
465 
     if ( wb_sel_i [0] == 1'b1 )
466 
       rgpio_out [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
467 
`endif
468 
   end
469 
 
470 
`else
471 
assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0
472 
`endif
473 
 
474 
//
475 
// Write to RGPIO_OE.
476 
//
477 
`ifdef GPIO_RGPIO_OE
478 
always @(posedge wb_clk_i or posedge wb_rst_i)
479 
        if (wb_rst_i)
480 
                rgpio_oe <= #1 {gw{1'b0}};
481 
        else if (rgpio_oe_sel && wb_we_i)
482 
  begin
483 
`ifdef GPIO_STRICT_32BIT_ACCESS
484 
                rgpio_oe <= #1 wb_dat_i[gw-1:0];
485 
`endif
486 
 
487 
`ifdef GPIO_WB_BYTES4
488 
     if ( wb_sel_i [3] == 1'b1 )
489 
       rgpio_oe [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
490 
     if ( wb_sel_i [2] == 1'b1 )
491 
       rgpio_oe [23:16] <= #1 wb_dat_i [23:16] ;
492 
     if ( wb_sel_i [1] == 1'b1 )
493 
       rgpio_oe [15:8] <= #1 wb_dat_i [15:8] ;
494 
     if ( wb_sel_i [0] == 1'b1 )
495 
       rgpio_oe [7:0] <= #1 wb_dat_i [7:0] ;
496 
`endif
497 
`ifdef GPIO_WB_BYTES3
498 
     if ( wb_sel_i [2] == 1'b1 )
499 
       rgpio_oe [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
500 
     if ( wb_sel_i [1] == 1'b1 )
501 
       rgpio_oe [15:8] <= #1 wb_dat_i [15:8] ;
502 
     if ( wb_sel_i [0] == 1'b1 )
503 
       rgpio_oe [7:0] <= #1 wb_dat_i [7:0] ;
504 
`endif
505 
`ifdef GPIO_WB_BYTES2
506 
     if ( wb_sel_i [1] == 1'b1 )
507 
       rgpio_oe [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
508 
     if ( wb_sel_i [0] == 1'b1 )
509 
       rgpio_oe [7:0] <= #1 wb_dat_i [7:0] ;
510 
`endif
511 
`ifdef GPIO_WB_BYTES1
512 
     if ( wb_sel_i [0] == 1'b1 )
513 
       rgpio_oe [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
514 
`endif
515 
   end
516 
 
517 
`else
518 
assign rgpio_oe = `GPIO_DEF_RGPIO_OE;   // RGPIO_OE = 0x0
519 
`endif
520 
 
521 
//
522 
// Write to RGPIO_INTE
523 
//
524 
`ifdef GPIO_RGPIO_INTE
525 
always @(posedge wb_clk_i or posedge wb_rst_i)
526 
        if (wb_rst_i)
527 
                rgpio_inte <= #1 {gw{1'b0}};
528 
        else if (rgpio_inte_sel && wb_we_i)
529 
  begin
530 
`ifdef GPIO_STRICT_32BIT_ACCESS
531 
                rgpio_inte <= #1 wb_dat_i[gw-1:0];
532 
`endif
533 
 
534 
`ifdef GPIO_WB_BYTES4
535 
     if ( wb_sel_i [3] == 1'b1 )
536 
       rgpio_inte [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
537 
     if ( wb_sel_i [2] == 1'b1 )
538 
       rgpio_inte [23:16] <= #1 wb_dat_i [23:16] ;
539 
     if ( wb_sel_i [1] == 1'b1 )
540 
       rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ;
541 
     if ( wb_sel_i [0] == 1'b1 )
542 
       rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;
543 
`endif
544 
`ifdef GPIO_WB_BYTES3
545 
     if ( wb_sel_i [2] == 1'b1 )
546 
       rgpio_inte [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
547 
     if ( wb_sel_i [1] == 1'b1 )
548 
       rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ;
549 
     if ( wb_sel_i [0] == 1'b1 )
550 
       rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;
551 
`endif
552 
`ifdef GPIO_WB_BYTES2
553 
     if ( wb_sel_i [1] == 1'b1 )
554 
       rgpio_inte [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
555 
     if ( wb_sel_i [0] == 1'b1 )
556 
       rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;
557 
`endif
558 
`ifdef GPIO_WB_BYTES1
559 
     if ( wb_sel_i [0] == 1'b1 )
560 
       rgpio_inte [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
561 
`endif
562 
   end
563 
 
564 
 
565 
`else
566 
assign rgpio_inte = `GPIO_DEF_RGPIO_INTE;       // RGPIO_INTE = 0x0
567 
`endif
568 
 
569 
//
570 
// Write to RGPIO_PTRIG
571 
//
572 
`ifdef GPIO_RGPIO_PTRIG
573 
always @(posedge wb_clk_i or posedge wb_rst_i)
574 
        if (wb_rst_i)
575 
                rgpio_ptrig <= #1 {gw{1'b0}};
576 
        else if (rgpio_ptrig_sel && wb_we_i)
577 
  begin
578 
`ifdef GPIO_STRICT_32BIT_ACCESS
579 
                rgpio_ptrig <= #1 wb_dat_i[gw-1:0];
580 
`endif
581 
 
582 
`ifdef GPIO_WB_BYTES4
583 
     if ( wb_sel_i [3] == 1'b1 )
584 
       rgpio_ptrig [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
585 
     if ( wb_sel_i [2] == 1'b1 )
586 
       rgpio_ptrig [23:16] <= #1 wb_dat_i [23:16] ;
587 
     if ( wb_sel_i [1] == 1'b1 )
588 
       rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ;
589 
     if ( wb_sel_i [0] == 1'b1 )
590 
       rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;
591 
`endif
592 
`ifdef GPIO_WB_BYTES3
593 
     if ( wb_sel_i [2] == 1'b1 )
594 
       rgpio_ptrig [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
595 
     if ( wb_sel_i [1] == 1'b1 )
596 
       rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ;
597 
     if ( wb_sel_i [0] == 1'b1 )
598 
       rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;
599 
`endif
600 
`ifdef GPIO_WB_BYTES2
601 
     if ( wb_sel_i [1] == 1'b1 )
602 
       rgpio_ptrig [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
603 
     if ( wb_sel_i [0] == 1'b1 )
604 
       rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;
605 
`endif
606 
`ifdef GPIO_WB_BYTES1
607 
     if ( wb_sel_i [0] == 1'b1 )
608 
       rgpio_ptrig [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
609 
`endif
610 
   end
611 
 
612 
`else
613 
assign rgpio_ptrig = `GPIO_DEF_RGPIO_PTRIG;     // RGPIO_PTRIG = 0x0
614 
`endif
615 
 
616 
//
617 
// Write to RGPIO_AUX
618 
//
619 
`ifdef GPIO_RGPIO_AUX
620 
always @(posedge wb_clk_i or posedge wb_rst_i)
621 
        if (wb_rst_i)
622 
                rgpio_aux <= #1 {gw{1'b0}};
623 
        else if (rgpio_aux_sel && wb_we_i)
624 
  begin
625 
`ifdef GPIO_STRICT_32BIT_ACCESS
626 
                rgpio_aux <= #1 wb_dat_i[gw-1:0];
627 
`endif
628 
 
629 
`ifdef GPIO_WB_BYTES4
630 
     if ( wb_sel_i [3] == 1'b1 )
631 
       rgpio_aux [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
632 
     if ( wb_sel_i [2] == 1'b1 )
633 
       rgpio_aux [23:16] <= #1 wb_dat_i [23:16] ;
634 
     if ( wb_sel_i [1] == 1'b1 )
635 
       rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ;
636 
     if ( wb_sel_i [0] == 1'b1 )
637 
       rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;
638 
`endif
639 
`ifdef GPIO_WB_BYTES3
640 
     if ( wb_sel_i [2] == 1'b1 )
641 
       rgpio_aux [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
642 
     if ( wb_sel_i [1] == 1'b1 )
643 
       rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ;
644 
     if ( wb_sel_i [0] == 1'b1 )
645 
       rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;
646 
`endif
647 
`ifdef GPIO_WB_BYTES2
648 
     if ( wb_sel_i [1] == 1'b1 )
649 
       rgpio_aux [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
650 
     if ( wb_sel_i [0] == 1'b1 )
651 
       rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;
652 
`endif
653 
`ifdef GPIO_WB_BYTES1
654 
     if ( wb_sel_i [0] == 1'b1 )
655 
       rgpio_aux [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
656 
`endif
657 
   end
658 
 
659 
`else
660 
assign rgpio_aux = `GPIO_DEF_RGPIO_AUX; // RGPIO_AUX = 0x0
661 
`endif
662 
 
663 
 
664 
//
665 
// Write to RGPIO_ECLK
666 
//
667 
`ifdef GPIO_RGPIO_ECLK
668 
always @(posedge wb_clk_i or posedge wb_rst_i)
669 
        if (wb_rst_i)
670 
                rgpio_eclk <= #1 {gw{1'b0}};
671 
        else if (rgpio_eclk_sel && wb_we_i)
672 
  begin
673 
`ifdef GPIO_STRICT_32BIT_ACCESS
674 
                rgpio_eclk <= #1 wb_dat_i[gw-1:0];
675 
`endif
676 
 
677 
`ifdef GPIO_WB_BYTES4
678 
     if ( wb_sel_i [3] == 1'b1 )
679 
       rgpio_eclk [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
680 
     if ( wb_sel_i [2] == 1'b1 )
681 
       rgpio_eclk [23:16] <= #1 wb_dat_i [23:16] ;
682 
     if ( wb_sel_i [1] == 1'b1 )
683 
       rgpio_eclk [15:8] <= #1 wb_dat_i [15:8] ;
684 
     if ( wb_sel_i [0] == 1'b1 )
685 
       rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ;
686 
`endif
687 
`ifdef GPIO_WB_BYTES3
688 
     if ( wb_sel_i [2] == 1'b1 )
689 
       rgpio_eclk [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
690 
     if ( wb_sel_i [1] == 1'b1 )
691 
       rgpio_eclk [15:8] <= #1 wb_dat_i [15:8] ;
692 
     if ( wb_sel_i [0] == 1'b1 )
693 
       rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ;
694 
`endif
695 
`ifdef GPIO_WB_BYTES2
696 
     if ( wb_sel_i [1] == 1'b1 )
697 
       rgpio_eclk [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
698 
     if ( wb_sel_i [0] == 1'b1 )
699 
       rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ;
700 
`endif
701 
`ifdef GPIO_WB_BYTES1
702 
     if ( wb_sel_i [0] == 1'b1 )
703 
       rgpio_eclk [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
704 
`endif
705 
   end
706 
 
707 
 
708 
`else
709 
assign rgpio_eclk = `GPIO_DEF_RGPIO_ECLK;       // RGPIO_ECLK = 0x0
710 
`endif
711 
 
712 
 
713 
 
714 
//
715 
// Write to RGPIO_NEC
716 
//
717 
`ifdef GPIO_RGPIO_NEC
718 
always @(posedge wb_clk_i or posedge wb_rst_i)
719 
        if (wb_rst_i)
720 
                rgpio_nec <= #1 {gw{1'b0}};
721 
        else if (rgpio_nec_sel && wb_we_i)
722 
  begin
723 
`ifdef GPIO_STRICT_32BIT_ACCESS
724 
                rgpio_nec <= #1 wb_dat_i[gw-1:0];
725 
`endif
726 
 
727 
`ifdef GPIO_WB_BYTES4
728 
     if ( wb_sel_i [3] == 1'b1 )
729 
       rgpio_nec [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
730 
     if ( wb_sel_i [2] == 1'b1 )
731 
       rgpio_nec [23:16] <= #1 wb_dat_i [23:16] ;
732 
     if ( wb_sel_i [1] == 1'b1 )
733 
       rgpio_nec [15:8] <= #1 wb_dat_i [15:8] ;
734 
     if ( wb_sel_i [0] == 1'b1 )
735 
       rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ;
736 
`endif
737 
`ifdef GPIO_WB_BYTES3
738 
     if ( wb_sel_i [2] == 1'b1 )
739 
       rgpio_nec [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
740 
     if ( wb_sel_i [1] == 1'b1 )
741 
       rgpio_nec [15:8] <= #1 wb_dat_i [15:8] ;
742 
     if ( wb_sel_i [0] == 1'b1 )
743 
       rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ;
744 
`endif
745 
`ifdef GPIO_WB_BYTES2
746 
     if ( wb_sel_i [1] == 1'b1 )
747 
       rgpio_nec [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
748 
     if ( wb_sel_i [0] == 1'b1 )
749 
       rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ;
750 
`endif
751 
`ifdef GPIO_WB_BYTES1
752 
     if ( wb_sel_i [0] == 1'b1 )
753 
       rgpio_nec [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
754 
`endif
755 
   end
756 
 
757 
 
758 
`else
759 
assign rgpio_nec = `GPIO_DEF_RGPIO_NEC; // RGPIO_NEC = 0x0
760 
`endif
761 
 
762 
//
763 
// synchronize inputs to systam clock
764 
//
765 
`ifdef  GPIO_SYNC_IN_WB
766 
always @(posedge wb_clk_i or posedge wb_rst_i)
767 
  if (wb_rst_i) begin
768 
    sync      <= #1 {gw{1'b0}} ;
769 
    ext_pad_s <= #1 {gw{1'b0}} ;
770 
  end else begin
771 
    sync      <= #1 ext_pad_i  ;
772 
    ext_pad_s <= #1 sync       ;
773 
  end
774 
`else
775 
assign  ext_pad_s = ext_pad_i;
776 
`endif // GPIO_SYNC_IN_WB
777 
 
778 
//
779 
// Latch into RGPIO_IN
780 
//
781 
`ifdef GPIO_RGPIO_IN
782 
always @(posedge wb_clk_i or posedge wb_rst_i)
783 
        if (wb_rst_i)
784 
                rgpio_in <= #1 {gw{1'b0}};
785 
        else
786 
                rgpio_in <= #1 in_muxed;
787 
`else
788 
assign rgpio_in = in_muxed;
789 
`endif
790 
 
791 
`ifdef GPIO_CLKPAD
792 
 
793 
`ifdef GPIO_SYNC_CLK_WB
794 
//
795 
// external clock enabled
796 
// synchronized to system clock
797 
// (one clock domain)
798 
//
799 
 
800 
reg  sync_clk,
801 
     clk_s   ,
802 
     clk_r   ;
803 
wire pedge   ,
804 
     nedge   ;
805 
wire [gw-1:0] pedge_vec   ,
806 
              nedge_vec   ;
807 
wire [gw-1:0] in_lach     ;
808 
 
809 
assign pedge =  clk_s & !clk_r ;
810 
assign nedge = !clk_s &  clk_r ;
811 
assign pedge_vec = {gw{pedge}} ;
812 
assign nedge_vec = {gw{nedge}} ;
813 
 
814 
assign in_lach = (~rgpio_nec & pedge_vec) | (rgpio_nec & nedge_vec) ;
815 
assign extc_in = (in_lach & ext_pad_s) | (~in_lach & pextc_sampled) ;
816 
 
817 
always @(posedge wb_clk_i or posedge wb_rst_i)
818 
  if (wb_rst_i) begin
819 
    sync_clk <= #1 1'b0 ;
820 
    clk_s    <= #1 1'b0 ;
821 
    clk_r    <= #1 1'b0 ;
822 
  end else begin
823 
    sync_clk <= #1 clk_pad_i ;
824 
    clk_s    <= #1 sync_clk  ;
825 
    clk_r    <= #1 clk_s     ;
826 
  end
827 
 
828 
always @(posedge wb_clk_i or posedge wb_rst_i)
829 
  if (wb_rst_i) begin
830 
    pextc_sampled <= #1 {gw{1'b0}};
831 
  end else begin
832 
    pextc_sampled <= #1 extc_in ;
833 
  end
834 
 
835 
assign in_muxed = (rgpio_eclk & pextc_sampled) | (~rgpio_eclk & ext_pad_s) ;
836 
 
837 
`else
838 
//
839 
// external clock enabled
840 
// not  synchronized to system clock
841 
// (two clock domains)
842 
//
843 
 
844 
`ifdef GPIO_SYNC_IN_CLK_WB
845 
 
846 
reg [gw-1:0] syn_extc  ,
847 
             extc_s    ;
848 
 
849 
always @(posedge wb_clk_i or posedge wb_rst_i)
850 
  if (wb_rst_i) begin
851 
    syn_extc  <= #1 {gw{1'b0}};
852 
    extc_s    <= #1 {gw{1'b0}};
853 
  end else begin
854 
    syn_extc  <= #1 extc_in ;
855 
    extc_s    <= #1 syn_extc;
856 
  end
857 
 
858 
`else
859 
 
860 
wire [gw-1:0] extc_s   ;
861 
assign extc_s = syn_extc ;
862 
 
863 
`endif // GPIO_SYNC_IN_CLK_WB
864 
 
865 
`ifdef GPIO_SYNC_IN_CLK
866 
reg [gw-1:0] syn_pclk    ,
867 
             ext_pad_spc ;
868 
 
869 
always @(posedge clk_pad_i or posedge wb_rst_i)
870 
  if (wb_rst_i) begin
871 
    syn_pclk    <= #1 {gw{1'b0}} ;
872 
    ext_pad_spc <= #1 {gw{1'b0}} ;
873 
  end else begin
874 
    syn_pclk    <= #1 ext_pad_i ;
875 
    ext_pad_spc <= #1 syn_pclk  ;
876 
  end
877 
 
878 
`else
879 
 
880 
wire [gw-1:0] ext_pad_spc      ;
881 
assign ext_pad_spc = ext_pad_i ;
882 
 
883 
`endif // GPIO_SYNC_IN_CLK
884 
 
885 
always @(posedge clk_pad_i or posedge wb_rst_i)
886 
  if (wb_rst_i) begin
887 
    pextc_sampled <= #1 {gw{1'b0}};
888 
  end else begin
889 
    pextc_sampled <= #1 ext_pad_spc ;
890 
  end
891 
 
892 
 
893 
`ifdef GPIO_NO_NEGEDGE_FLOPS
894 
 
895 
`ifdef GPIO_NO_CLKPAD_LOGIC
896 
 
897 
assign extc_in = pextc_sampled;
898 
 
899 
`else
900 
 
901 
wire  clk_n;
902 
assign clk_n = !clk_pad_i;
903 
 
904 
`ifdef GPIO_SYNC_IN_CLK
905 
reg [gw-1:0] syn_nclk    ,
906 
             ext_pad_snc ;
907 
 
908 
always @(posedge clk_n or posedge wb_rst_i)
909 
  if (wb_rst_i) begin
910 
    syn_nclk    <= #1 {gw{1'b0}} ;
911 
    ext_pad_snc <= #1 {gw{1'b0}} ;
912 
  end else begin
913 
    syn_nclk    <= #1 ext_pad_i ;
914 
    ext_pad_snc <= #1 syn_nclk  ;
915 
  end
916 
 
917 
`else
918 
 
919 
wire [gw-1:0] ext_pad_snc      ;
920 
assign ext_pad_snc = ext_pad_i ;
921 
 
922 
`endif // GPIO_SYNC_IN_CLK
923 
 
924 
always @(posedge clk_n or posedge wb_rst_i)
925 
  if (wb_rst_i) begin
926 
    nextc_sampled <= #1 {gw{1'b0}};
927 
  end else begin
928 
    nextc_sampled <= #1 ext_pad_snc ;
929 
  end
930 
 
931 
assign extc_in = (~rgpio_nec & pextc_sampled) | (rgpio_nec & nextc_sampled) ;
932 
 
933 
`endif //  GPIO_NO_CLKPAD_LOGIC
934 
 
935 
 
936 
`else
937 
 
938 
`ifdef GPIO_SYNC_IN_CLK
939 
reg [gw-1:0] syn_nclk    ,
940 
             ext_pad_snc ;
941 
 
942 
always @(negedge clk_n or posedge wb_rst_i)
943 
  if (wb_rst_i) begin
944 
    syn_nclk    <= #1 {gw{1'b0}} ;
945 
    ext_pad_snc <= #1 {gw{1'b0}} ;
946 
  end else begin
947 
    syn_nclk    <= #1 ext_pad_i ;
948 
    ext_pad_snc <= #1 syn_nclk  ;
949 
  end
950 
 
951 
`else
952 
 
953 
wire [gw-1:0] ext_pad_snc      ;
954 
assign ext_pad_snc = ext_pad_i ;
955 
 
956 
`endif // GPIO_SYNC_IN_CLK
957 
 
958 
always @(negedge clk_pad_i or posedge wb_rst_i)
959 
  if (wb_rst_i) begin
960 
    nextc_sampled <= #1 {gw{1'b0}};
961 
  end else begin
962 
    nextc_sampled <= #1 ext_pad_snc ;
963 
  end
964 
 
965 
assign extc_in = (~rgpio_nec & pextc_sampled) | (rgpio_nec & nextc_sampled) ;
966 
 
967 
`endif //  GPIO_NO_NEGEDGE_FLOPS
968 
 
969 
assign in_muxed = (rgpio_eclk & extc_s)      | (~rgpio_eclk & ext_pad_s) ;
970 
 
971 
 
972 
`endif //  GPIO_SYNC_CLK_WB
973 
 
974 
 
975 
`else
976 
 
977 
assign  in_muxed  = ext_pad_s ;
978 
 
979 
`endif //  GPIO_CLKPAD
980 
 
981 
 
982 
 
983 
//
984 
// Mux all registers when doing a read of GPIO registers
985 
//
986 
always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or
987 
                rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints or rgpio_eclk or rgpio_nec)
988 
        case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
989 
`ifdef GPIO_READREGS
990 
  `ifdef GPIO_RGPIO_OUT
991 
        `GPIO_RGPIO_OUT: begin
992 
                        wb_dat[dw-1:0] = rgpio_out;
993 
                end
994 
  `endif
995 
  `ifdef GPIO_RGPIO_OE
996 
                `GPIO_RGPIO_OE: begin
997 
                        wb_dat[dw-1:0] = rgpio_oe;
998 
                end
999 
  `endif
1000 
  `ifdef GPIO_RGPIO_INTE
1001 
                `GPIO_RGPIO_INTE: begin
1002 
                        wb_dat[dw-1:0] = rgpio_inte;
1003 
                end
1004 
  `endif
1005 
  `ifdef GPIO_RGPIO_PTRIG
1006 
                `GPIO_RGPIO_PTRIG: begin
1007 
                        wb_dat[dw-1:0] = rgpio_ptrig;
1008 
                end
1009 
  `endif
1010 
  `ifdef GPIO_RGPIO_NEC
1011 
                `GPIO_RGPIO_NEC: begin
1012 
                        wb_dat[dw-1:0] = rgpio_nec;
1013 
                end
1014 
  `endif
1015 
  `ifdef GPIO_RGPIO_ECLK
1016 
                `GPIO_RGPIO_ECLK: begin
1017 
                        wb_dat[dw-1:0] = rgpio_eclk;
1018 
                end
1019 
  `endif
1020 
  `ifdef GPIO_RGPIO_AUX
1021 
                `GPIO_RGPIO_AUX: begin
1022 
                        wb_dat[dw-1:0] = rgpio_aux;
1023 
                end
1024 
  `endif
1025 
  `ifdef GPIO_RGPIO_CTRL
1026 
                `GPIO_RGPIO_CTRL: begin
1027 
                        wb_dat[1:0] = rgpio_ctrl;
1028 
                        wb_dat[dw-1:2] = {dw-2{1'b0}};
1029 
                end
1030 
  `endif
1031 
`endif
1032 
  `ifdef GPIO_RGPIO_INTS
1033 
                `GPIO_RGPIO_INTS: begin
1034 
                        wb_dat[dw-1:0] = rgpio_ints;
1035 
                end
1036 
  `endif
1037 
                default: begin
1038 
                        wb_dat[dw-1:0] = rgpio_in;
1039 
                end
1040 
        endcase
1041 
 
1042 
//
1043 
// WB data output
1044 
//
1045 
`ifdef GPIO_REGISTERED_WB_OUTPUTS
1046 
always @(posedge wb_clk_i or posedge wb_rst_i)
1047 
        if (wb_rst_i)
1048 
                wb_dat_o <= #1 {dw{1'b0}};
1049 
        else
1050 
                wb_dat_o <= #1 wb_dat;
1051 
`else
1052 
assign wb_dat_o = wb_dat;
1053 
`endif
1054 
 
1055 
//
1056 
// RGPIO_INTS
1057 
//
1058 
`ifdef GPIO_RGPIO_INTS
1059 
always @(posedge wb_clk_i or posedge wb_rst_i)
1060 
        if (wb_rst_i)
1061 
                rgpio_ints <= #1 {gw{1'b0}};
1062 
        else if (rgpio_ints_sel && wb_we_i)
1063 
                rgpio_ints <= #1 wb_dat_i[gw-1:0];
1064 
        else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
1065 
                rgpio_ints <= #1 (rgpio_ints | ((in_muxed ^ rgpio_in) & ~(in_muxed ^ rgpio_ptrig)) & rgpio_inte);
1066 
`else
1067 
assign rgpio_ints = (rgpio_ints | ((in_muxed ^ rgpio_in) & ~(in_muxed ^ rgpio_ptrig)) & rgpio_inte);
1068 
`endif
1069 
 
1070 
//
1071 
// Generate interrupt request
1072 
//
1073 
assign wb_inta = |rgpio_ints ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;
1074 
 
1075 
//
1076 
// Optional registration of WB interrupt
1077 
//
1078 
`ifdef GPIO_REGISTERED_WB_OUTPUTS
1079 
always @(posedge wb_clk_i or posedge wb_rst_i)
1080 
        if (wb_rst_i)
1081 
                wb_inta_o <= #1 1'b0;
1082 
        else
1083 
                wb_inta_o <= #1 wb_inta;
1084 
`else
1085 
assign wb_inta_o = wb_inta;
1086 
`endif // GPIO_REGISTERED_WB_OUTPUTS
1087 
 
1088 
//
1089 
// Output enables are RGPIO_OE bits
1090 
//
1091 
assign ext_padoe_o = rgpio_oe;
1092 
 
1093 
//
1094 
// Generate GPIO outputs
1095 
//
1096 
`ifdef GPIO_AUX_IMPLEMENT
1097 
assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;
1098 
`else
1099 
assign out_pad = rgpio_out ;
1100 
`endif //  GPIO_AUX_IMPLEMENT
1101 
 
1102 
//
1103 
// Optional registration of GPIO outputs
1104 
//
1105 
`ifdef GPIO_REGISTERED_IO_OUTPUTS
1106 
always @(posedge wb_clk_i or posedge wb_rst_i)
1107 
        if (wb_rst_i)
1108 
                ext_pad_o <= #1 {gw{1'b0}};
1109 
        else
1110 
                ext_pad_o <= #1 out_pad;
1111 
`else
1112 
assign ext_pad_o = out_pad;
1113 
`endif // GPIO_REGISTERED_IO_OUTPUTS
1114 
 
1115 
 
1116 
`else
1117 
 
1118 
//
1119 
// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL
1120 
// is cleared and WISHBONE transfers complete with errors
1121 
//
1122 
assign wb_inta_o = 1'b0;
1123 
assign wb_ack_o = 1'b0;
1124 
assign wb_err_o = wb_cyc_i & wb_stb_i;
1125 
assign ext_padoe_o = {gw{1'b1}};
1126 
assign ext_pad_o = {gw{1'b0}};
1127 
 
1128 
//
1129 
// Read GPIO registers
1130 
//
1131 
assign wb_dat_o = {dw{1'b0}};
1132 
 
1133 
`endif //  GPIO_IMPLEMENTED
1134 
 
1135 
endmodule
1136 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.