Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

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////                                                             ////

////  WISHBONE Memory Controller                                 ////

////  Parametarized, Pipelined Incrementer                       ////

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////                                                             ////

////  Author: Rudolf Usselmann                                   ////

////          rudi@asics.ws                                      ////

////                                                             ////

////                                                             ////

////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////

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//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////

////                         www.asics.ws                        ////

////                         rudi@asics.ws                       ////

////                                                             ////

//// This source file may be used and distributed without        ////

//// restriction provided that this copyright statement is not   ////

//// removed from the file and that any derivative work contains ////

//// the original copyright notice and the associated disclaimer.////

////                                                             ////

////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////

//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////

//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////

//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////

//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////

//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////

//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////

//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////

//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////

//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////

//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////

//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////

//// POSSIBILITY OF SUCH DAMAGE.                                 ////

////                                                             ////

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//  CVS Log

//

//  $Id: mc_incn_r.v,v 1.2 2002-01-21 13:08:52 rudi Exp $

//

//  $Date: 2002-01-21 13:08:52 $

//  $Revision: 1.2 $

//  $Author: rudi $

//  $Locker:  $

//  $State: Exp $

//

// Change History:

//               $Log: not supported by cvs2svn $

//               Revision 1.1  2001/07/29 07:34:41  rudi

//

//

//               1) Changed Directory Structure

//               2) Fixed several minor bugs

//

//               Revision 1.1  2001/06/12 15:18:47  rudi

//

//

//               This is a pipelined primitive incrementor.

//

//

//

//

//

`include "mc_defines.v"

//

// USAGE: incN_r #(<WIDTH>) uN(clk, input, output);

//

module mc_incn_r(clk, inc_in, inc_out);

parameter       incN_width = 32;

input           clk;

input   [incN_width-1:0] inc_in;

output  [incN_width-1:0] inc_out;

parameter       incN_center = incN_width / 2;

reg     [incN_center:0]          out_r;

wire    [31:0]                   tmp_zeros = 32'h0;

wire    [incN_center-1:0]        inc_next;

always @(posedge clk)

        out_r <= #1 inc_in[incN_center - 1:0] + {tmp_zeros[incN_center-2:0], 1'h1};

assign inc_out[incN_width-1:incN_center] = inc_in[incN_width-1:incN_center] + inc_next;

assign inc_next = out_r[incN_center] ?

                        {tmp_zeros[incN_center-2:0], 1'h1} : tmp_zeros[incN_center-2:0];

assign inc_out[incN_center-1:0]  = out_r;

endmodule