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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [mem_if/] [rtl/] [verilog/] [mc_obct_top.v] - Blame information for rev 12

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Memory Controller                                 ////
////  Open Bank & Row Tracking Block Top Level                   ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: mc_obct_top.v,v 1.4 2002-01-21 13:08:52 rudi Exp $
//
//  $Date: 2002-01-21 13:08:52 $
//  $Revision: 1.4 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.3  2001/12/21 05:09:29  rudi
//
//               - Fixed combinatorial loops in synthesis
//               - Fixed byte select bug
//
//               Revision 1.2  2001/08/10 08:16:21  rudi
//
//               - Changed IO names to be more clear.
//               - Uniquifyed define names to be core specific.
//               - Removed "Refresh Early" configuration
//
//               Revision 1.1  2001/07/29 07:34:41  rudi
//
//
//               1) Changed Directory Structure
//               2) Fixed several minor bugs
//
//               Revision 1.1.1.1  2001/05/13 09:39:47  rudi
//               Created Directory Structure
//
//
//
//
 
`include "mc_defines.v"
 
module mc_obct_top(clk, rst, cs, row_adr, bank_adr, bank_set, bank_clr, bank_clr_all,
                bank_open, any_bank_open, row_same, rfr_ack);
input           clk, rst;
input   [7:0]    cs;
input   [12:0]   row_adr;
input   [1:0]    bank_adr;
input           bank_set;
input           bank_clr;
input           bank_clr_all;
output          bank_open;
output          any_bank_open;
output          row_same;
input           rfr_ack;
 
////////////////////////////////////////////////////////////////////
//
// Local Registers & Wires
//
 
reg             bank_open;
reg             row_same;
reg             any_bank_open;
 
wire            bank_set_0;
wire            bank_clr_0;
wire            bank_clr_all_0;
wire            bank_open_0;
wire            row_same_0;
wire            any_bank_open_0;
 
wire            bank_set_1;
wire            bank_clr_1;
wire            bank_clr_all_1;
wire            bank_open_1;
wire            row_same_1;
wire            any_bank_open_1;
 
wire            bank_set_2;
wire            bank_clr_2;
wire            bank_clr_all_2;
wire            bank_open_2;
wire            row_same_2;
wire            any_bank_open_2;
 
wire            bank_set_3;
wire            bank_clr_3;
wire            bank_clr_all_3;
wire            bank_open_3;
wire            row_same_3;
wire            any_bank_open_3;
 
wire            bank_set_4;
wire            bank_clr_4;
wire            bank_clr_all_4;
wire            bank_open_4;
wire            row_same_4;
wire            any_bank_open_4;
 
wire            bank_set_5;
wire            bank_clr_5;
wire            bank_clr_all_5;
wire            bank_open_5;
wire            row_same_5;
wire            any_bank_open_5;
 
wire            bank_set_6;
wire            bank_clr_6;
wire            bank_clr_all_6;
wire            bank_open_6;
wire            row_same_6;
wire            any_bank_open_6;
 
wire            bank_set_7;
wire            bank_clr_7;
wire            bank_clr_all_7;
wire            bank_open_7;
wire            row_same_7;
wire            any_bank_open_7;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign bank_set_0 = cs[0] & bank_set;
assign bank_set_1 = cs[1] & bank_set;
assign bank_set_2 = cs[2] & bank_set;
assign bank_set_3 = cs[3] & bank_set;
assign bank_set_4 = cs[4] & bank_set;
assign bank_set_5 = cs[5] & bank_set;
assign bank_set_6 = cs[6] & bank_set;
assign bank_set_7 = cs[7] & bank_set;
 
assign bank_clr_0 = cs[0] & bank_clr;
assign bank_clr_1 = cs[1] & bank_clr;
assign bank_clr_2 = cs[2] & bank_clr;
assign bank_clr_3 = cs[3] & bank_clr;
assign bank_clr_4 = cs[4] & bank_clr;
assign bank_clr_5 = cs[5] & bank_clr;
assign bank_clr_6 = cs[6] & bank_clr;
assign bank_clr_7 = cs[7] & bank_clr;
 
assign bank_clr_all_0 = (cs[0] & bank_clr_all) | rfr_ack;
assign bank_clr_all_1 = (cs[1] & bank_clr_all) | rfr_ack;
assign bank_clr_all_2 = (cs[2] & bank_clr_all) | rfr_ack;
assign bank_clr_all_3 = (cs[3] & bank_clr_all) | rfr_ack;
assign bank_clr_all_4 = (cs[4] & bank_clr_all) | rfr_ack;
assign bank_clr_all_5 = (cs[5] & bank_clr_all) | rfr_ack;
assign bank_clr_all_6 = (cs[6] & bank_clr_all) | rfr_ack;
assign bank_clr_all_7 = (cs[7] & bank_clr_all) | rfr_ack;
 
always @(posedge clk)
        bank_open <= #1 (cs[0] & bank_open_0) | (cs[1] & bank_open_1) |
                        (cs[2] & bank_open_2) | (cs[3] & bank_open_3) |
                        (cs[4] & bank_open_4) | (cs[5] & bank_open_5) |
                        (cs[6] & bank_open_6) | (cs[7] & bank_open_7);
 
always @(posedge clk)
        row_same <= #1  (cs[0] & row_same_0) | (cs[1] & row_same_1) |
                        (cs[2] & row_same_2) | (cs[3] & row_same_3) |
                        (cs[4] & row_same_4) | (cs[5] & row_same_5) |
                        (cs[6] & row_same_6) | (cs[7] & row_same_7);
 
always @(posedge clk)
        any_bank_open <= #1     (cs[0] & any_bank_open_0) | (cs[1] & any_bank_open_1) |
                                (cs[2] & any_bank_open_2) | (cs[3] & any_bank_open_3) |
                                (cs[4] & any_bank_open_4) | (cs[5] & any_bank_open_5) |
                                (cs[6] & any_bank_open_6) | (cs[7] & any_bank_open_7);
 
 
////////////////////////////////////////////////////////////////////
//
// OBCT Modules for each Chip Select
//
 
mc_obct u0(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_0      ),
                .bank_clr(      bank_clr_0      ),
                .bank_clr_all(  bank_clr_all_0  ),
                .bank_open(     bank_open_0     ),
                .any_bank_open( any_bank_open_0 ),
                .row_same(      row_same_0      )
                );
 
`ifdef MC_HAVE_CS1
mc_obct u1(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_1      ),
                .bank_clr(      bank_clr_1      ),
                .bank_clr_all(  bank_clr_all_1  ),
                .bank_open(     bank_open_1     ),
                .any_bank_open( any_bank_open_1 ),
                .row_same(      row_same_1      )
                );
`else
mc_obct_dummy   u1(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_1      ),
                .bank_clr(      bank_clr_1      ),
                .bank_clr_all(  bank_clr_all_1  ),
                .bank_open(     bank_open_1     ),
                .any_bank_open( any_bank_open_1 ),
                .row_same(      row_same_1      )
                );
`endif
 
`ifdef MC_HAVE_CS2
mc_obct u2(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_2      ),
                .bank_clr(      bank_clr_2      ),
                .bank_clr_all(  bank_clr_all_2  ),
                .bank_open(     bank_open_2     ),
                .any_bank_open( any_bank_open_2 ),
                .row_same(      row_same_2      )
                );
`else
mc_obct_dummy   u2(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_2      ),
                .bank_clr(      bank_clr_2      ),
                .bank_clr_all(  bank_clr_all_2  ),
                .bank_open(     bank_open_2     ),
                .any_bank_open( any_bank_open_2 ),
                .row_same(      row_same_2      )
                );
`endif
 
`ifdef MC_HAVE_CS3
mc_obct u3(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_3      ),
                .bank_clr(      bank_clr_3      ),
                .bank_clr_all(  bank_clr_all_3  ),
                .bank_open(     bank_open_3     ),
                .any_bank_open( any_bank_open_3 ),
                .row_same(      row_same_3      )
                );
`else
mc_obct_dummy   u3(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_3      ),
                .bank_clr(      bank_clr_3      ),
                .bank_clr_all(  bank_clr_all_3  ),
                .bank_open(     bank_open_3     ),
                .any_bank_open( any_bank_open_3 ),
                .row_same(      row_same_3      )
                );
`endif
 
`ifdef MC_HAVE_CS4
mc_obct u4(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_4      ),
                .bank_clr(      bank_clr_4      ),
                .bank_clr_all(  bank_clr_all_4  ),
                .bank_open(     bank_open_4     ),
                .any_bank_open( any_bank_open_4 ),
                .row_same(      row_same_4      )
                );
`else
mc_obct_dummy   u4(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_4      ),
                .bank_clr(      bank_clr_4      ),
                .bank_clr_all(  bank_clr_all_4  ),
                .bank_open(     bank_open_4     ),
                .any_bank_open( any_bank_open_4 ),
                .row_same(      row_same_4      )
                );
`endif
 
`ifdef MC_HAVE_CS5
mc_obct u5(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_5      ),
                .bank_clr(      bank_clr_5      ),
                .bank_clr_all(  bank_clr_all_5  ),
                .bank_open(     bank_open_5     ),
                .any_bank_open( any_bank_open_5 ),
                .row_same(      row_same_5      )
                );
`else
mc_obct_dummy   u5(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_5      ),
                .bank_clr(      bank_clr_5      ),
                .bank_clr_all(  bank_clr_all_5  ),
                .bank_open(     bank_open_5     ),
                .any_bank_open( any_bank_open_5 ),
                .row_same(      row_same_5      )
                );
`endif
 
`ifdef MC_HAVE_CS6
mc_obct u6(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_6      ),
                .bank_clr(      bank_clr_6      ),
                .bank_clr_all(  bank_clr_all_6  ),
                .bank_open(     bank_open_6     ),
                .any_bank_open( any_bank_open_6 ),
                .row_same(      row_same_6      )
                );
`else
mc_obct_dummy   u6(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_6      ),
                .bank_clr(      bank_clr_6      ),
                .bank_clr_all(  bank_clr_all_6  ),
                .bank_open(     bank_open_6     ),
                .any_bank_open( any_bank_open_6 ),
                .row_same(      row_same_6      )
                );
`endif
 
`ifdef MC_HAVE_CS7
mc_obct u7(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_7      ),
                .bank_clr(      bank_clr_7      ),
                .bank_clr_all(  bank_clr_all_7  ),
                .bank_open(     bank_open_7     ),
                .any_bank_open( any_bank_open_7 ),
                .row_same(      row_same_7      )
                );
`else
mc_obct_dummy   u7(
                .clk(           clk             ),
                .rst(           rst             ),
                .row_adr(       row_adr         ),
                .bank_adr(      bank_adr        ),
                .bank_set(      bank_set_7      ),
                .bank_clr(      bank_clr_7      ),
                .bank_clr_all(  bank_clr_all_7  ),
                .bank_open(     bank_open_7     ),
                .any_bank_open( any_bank_open_7 ),
                .row_same(      row_same_7      )
                );
`endif
 
endmodule

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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [mem_if/] [rtl/] [verilog/] [mc_obct_top.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	xianfeng	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Memory Controller ////`
4			`//// Open Bank & Row Tracking Block Top Level ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
16			`//// www.asics.ws ////`
17			`//// rudi@asics.ws ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer.////`
23			`//// ////`
24			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
25			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
26			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
27			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
28			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
29			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
30			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
31			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
32			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
33			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
34			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
35			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
36			`//// POSSIBILITY OF SUCH DAMAGE. ////`
37			`//// ////`
38			`/////////////////////////////////////////////////////////////////////`
39
40			`// CVS Log`
41			`//`
42			`// $Id: mc_obct_top.v,v 1.4 2002-01-21 13:08:52 rudi Exp $`
43			`//`
44			`// $Date: 2002-01-21 13:08:52 $`
45			`// $Revision: 1.4 $`
46			`// $Author: rudi $`
47			`// $Locker: $`
48			`// $State: Exp $`
49			`//`
50			`// Change History:`
51			`// $Log: not supported by cvs2svn $`
52			`// Revision 1.3 2001/12/21 05:09:29 rudi`
53			`//`
54			`// - Fixed combinatorial loops in synthesis`
55			`// - Fixed byte select bug`
56			`//`
57			`// Revision 1.2 2001/08/10 08:16:21 rudi`
58			`//`
59			`// - Changed IO names to be more clear.`
60			`// - Uniquifyed define names to be core specific.`
61			`// - Removed "Refresh Early" configuration`
62			`//`
63			`// Revision 1.1 2001/07/29 07:34:41 rudi`
64			`//`
65			`//`
66			`// 1) Changed Directory Structure`
67			`// 2) Fixed several minor bugs`
68			`//`
69			`// Revision 1.1.1.1 2001/05/13 09:39:47 rudi`
70			`// Created Directory Structure`
71			`//`
72			`//`
73			`//`
74			`//`
75
76			`include "mc_defines.v"
77
78			`module mc_obct_top(clk, rst, cs, row_adr, bank_adr, bank_set, bank_clr, bank_clr_all,`
79			`bank_open, any_bank_open, row_same, rfr_ack);`
80			`input clk, rst;`
81			`input [7:0] cs;`
82			`input [12:0] row_adr;`
83			`input [1:0] bank_adr;`
84			`input bank_set;`
85			`input bank_clr;`
86			`input bank_clr_all;`
87			`output bank_open;`
88			`output any_bank_open;`
89			`output row_same;`
90			`input rfr_ack;`
91
92			`////////////////////////////////////////////////////////////////////`
93			`//`
94			`// Local Registers & Wires`
95			`//`
96
97			`reg bank_open;`
98			`reg row_same;`
99			`reg any_bank_open;`
100
101			`wire bank_set_0;`
102			`wire bank_clr_0;`
103			`wire bank_clr_all_0;`
104			`wire bank_open_0;`
105			`wire row_same_0;`
106			`wire any_bank_open_0;`
107
108			`wire bank_set_1;`
109			`wire bank_clr_1;`
110			`wire bank_clr_all_1;`
111			`wire bank_open_1;`
112			`wire row_same_1;`
113			`wire any_bank_open_1;`
114
115			`wire bank_set_2;`
116			`wire bank_clr_2;`
117			`wire bank_clr_all_2;`
118			`wire bank_open_2;`
119			`wire row_same_2;`
120			`wire any_bank_open_2;`
121
122			`wire bank_set_3;`
123			`wire bank_clr_3;`
124			`wire bank_clr_all_3;`
125			`wire bank_open_3;`
126			`wire row_same_3;`
127			`wire any_bank_open_3;`
128
129			`wire bank_set_4;`
130			`wire bank_clr_4;`
131			`wire bank_clr_all_4;`
132			`wire bank_open_4;`
133			`wire row_same_4;`
134			`wire any_bank_open_4;`
135
136			`wire bank_set_5;`
137			`wire bank_clr_5;`
138			`wire bank_clr_all_5;`
139			`wire bank_open_5;`
140			`wire row_same_5;`
141			`wire any_bank_open_5;`
142
143			`wire bank_set_6;`
144			`wire bank_clr_6;`
145			`wire bank_clr_all_6;`
146			`wire bank_open_6;`
147			`wire row_same_6;`
148			`wire any_bank_open_6;`
149
150			`wire bank_set_7;`
151			`wire bank_clr_7;`
152			`wire bank_clr_all_7;`
153			`wire bank_open_7;`
154			`wire row_same_7;`
155			`wire any_bank_open_7;`
156
157			`////////////////////////////////////////////////////////////////////`
158			`//`
159			`// Misc Logic`
160			`//`
161
162			`assign bank_set_0 = cs[0] & bank_set;`
163			`assign bank_set_1 = cs[1] & bank_set;`
164			`assign bank_set_2 = cs[2] & bank_set;`
165			`assign bank_set_3 = cs[3] & bank_set;`
166			`assign bank_set_4 = cs[4] & bank_set;`
167			`assign bank_set_5 = cs[5] & bank_set;`
168			`assign bank_set_6 = cs[6] & bank_set;`
169			`assign bank_set_7 = cs[7] & bank_set;`
170
171			`assign bank_clr_0 = cs[0] & bank_clr;`
172			`assign bank_clr_1 = cs[1] & bank_clr;`
173			`assign bank_clr_2 = cs[2] & bank_clr;`
174			`assign bank_clr_3 = cs[3] & bank_clr;`
175			`assign bank_clr_4 = cs[4] & bank_clr;`
176			`assign bank_clr_5 = cs[5] & bank_clr;`
177			`assign bank_clr_6 = cs[6] & bank_clr;`
178			`assign bank_clr_7 = cs[7] & bank_clr;`
179
180			`assign bank_clr_all_0 = (cs[0] & bank_clr_all) \| rfr_ack;`
181			`assign bank_clr_all_1 = (cs[1] & bank_clr_all) \| rfr_ack;`
182			`assign bank_clr_all_2 = (cs[2] & bank_clr_all) \| rfr_ack;`
183			`assign bank_clr_all_3 = (cs[3] & bank_clr_all) \| rfr_ack;`
184			`assign bank_clr_all_4 = (cs[4] & bank_clr_all) \| rfr_ack;`
185			`assign bank_clr_all_5 = (cs[5] & bank_clr_all) \| rfr_ack;`
186			`assign bank_clr_all_6 = (cs[6] & bank_clr_all) \| rfr_ack;`
187			`assign bank_clr_all_7 = (cs[7] & bank_clr_all) \| rfr_ack;`
188
189			`always @(posedge clk)`
190			`bank_open <= #1 (cs[0] & bank_open_0) \| (cs[1] & bank_open_1) \|`
191			`(cs[2] & bank_open_2) \| (cs[3] & bank_open_3) \|`
192			`(cs[4] & bank_open_4) \| (cs[5] & bank_open_5) \|`
193			`(cs[6] & bank_open_6) \| (cs[7] & bank_open_7);`
194
195			`always @(posedge clk)`
196			`row_same <= #1 (cs[0] & row_same_0) \| (cs[1] & row_same_1) \|`
197			`(cs[2] & row_same_2) \| (cs[3] & row_same_3) \|`
198			`(cs[4] & row_same_4) \| (cs[5] & row_same_5) \|`
199			`(cs[6] & row_same_6) \| (cs[7] & row_same_7);`
200
201			`always @(posedge clk)`
202			`any_bank_open <= #1 (cs[0] & any_bank_open_0) \| (cs[1] & any_bank_open_1) \|`
203			`(cs[2] & any_bank_open_2) \| (cs[3] & any_bank_open_3) \|`
204			`(cs[4] & any_bank_open_4) \| (cs[5] & any_bank_open_5) \|`
205			`(cs[6] & any_bank_open_6) \| (cs[7] & any_bank_open_7);`
206
207
208			`////////////////////////////////////////////////////////////////////`
209			`//`
210			`// OBCT Modules for each Chip Select`
211			`//`
212
213			`mc_obct u0(`
214			`.clk( clk ),`
215			`.rst( rst ),`
216			`.row_adr( row_adr ),`
217			`.bank_adr( bank_adr ),`
218			`.bank_set( bank_set_0 ),`
219			`.bank_clr( bank_clr_0 ),`
220			`.bank_clr_all( bank_clr_all_0 ),`
221			`.bank_open( bank_open_0 ),`
222			`.any_bank_open( any_bank_open_0 ),`
223			`.row_same( row_same_0 )`
224			`);`
225
226			`ifdef MC_HAVE_CS1
227			`mc_obct u1(`
228			`.clk( clk ),`
229			`.rst( rst ),`
230			`.row_adr( row_adr ),`
231			`.bank_adr( bank_adr ),`
232			`.bank_set( bank_set_1 ),`
233			`.bank_clr( bank_clr_1 ),`
234			`.bank_clr_all( bank_clr_all_1 ),`
235			`.bank_open( bank_open_1 ),`
236			`.any_bank_open( any_bank_open_1 ),`
237			`.row_same( row_same_1 )`
238			`);`
239			`else
240			`mc_obct_dummy u1(`
241			`.clk( clk ),`
242			`.rst( rst ),`
243			`.row_adr( row_adr ),`
244			`.bank_adr( bank_adr ),`
245			`.bank_set( bank_set_1 ),`
246			`.bank_clr( bank_clr_1 ),`
247			`.bank_clr_all( bank_clr_all_1 ),`
248			`.bank_open( bank_open_1 ),`
249			`.any_bank_open( any_bank_open_1 ),`
250			`.row_same( row_same_1 )`
251			`);`
252			`endif
253
254			`ifdef MC_HAVE_CS2
255			`mc_obct u2(`
256			`.clk( clk ),`
257			`.rst( rst ),`
258			`.row_adr( row_adr ),`
259			`.bank_adr( bank_adr ),`
260			`.bank_set( bank_set_2 ),`
261			`.bank_clr( bank_clr_2 ),`
262			`.bank_clr_all( bank_clr_all_2 ),`
263			`.bank_open( bank_open_2 ),`
264			`.any_bank_open( any_bank_open_2 ),`
265			`.row_same( row_same_2 )`
266			`);`
267			`else
268			`mc_obct_dummy u2(`
269			`.clk( clk ),`
270			`.rst( rst ),`
271			`.row_adr( row_adr ),`
272			`.bank_adr( bank_adr ),`
273			`.bank_set( bank_set_2 ),`
274			`.bank_clr( bank_clr_2 ),`
275			`.bank_clr_all( bank_clr_all_2 ),`
276			`.bank_open( bank_open_2 ),`
277			`.any_bank_open( any_bank_open_2 ),`
278			`.row_same( row_same_2 )`
279			`);`
280			`endif
281
282			`ifdef MC_HAVE_CS3
283			`mc_obct u3(`
284			`.clk( clk ),`
285			`.rst( rst ),`
286			`.row_adr( row_adr ),`
287			`.bank_adr( bank_adr ),`
288			`.bank_set( bank_set_3 ),`
289			`.bank_clr( bank_clr_3 ),`
290			`.bank_clr_all( bank_clr_all_3 ),`
291			`.bank_open( bank_open_3 ),`
292			`.any_bank_open( any_bank_open_3 ),`
293			`.row_same( row_same_3 )`
294			`);`
295			`else
296			`mc_obct_dummy u3(`
297			`.clk( clk ),`
298			`.rst( rst ),`
299			`.row_adr( row_adr ),`
300			`.bank_adr( bank_adr ),`
301			`.bank_set( bank_set_3 ),`
302			`.bank_clr( bank_clr_3 ),`
303			`.bank_clr_all( bank_clr_all_3 ),`
304			`.bank_open( bank_open_3 ),`
305			`.any_bank_open( any_bank_open_3 ),`
306			`.row_same( row_same_3 )`
307			`);`
308			`endif
309
310			`ifdef MC_HAVE_CS4
311			`mc_obct u4(`
312			`.clk( clk ),`
313			`.rst( rst ),`
314			`.row_adr( row_adr ),`
315			`.bank_adr( bank_adr ),`
316			`.bank_set( bank_set_4 ),`
317			`.bank_clr( bank_clr_4 ),`
318			`.bank_clr_all( bank_clr_all_4 ),`
319			`.bank_open( bank_open_4 ),`
320			`.any_bank_open( any_bank_open_4 ),`
321			`.row_same( row_same_4 )`
322			`);`
323			`else
324			`mc_obct_dummy u4(`
325			`.clk( clk ),`
326			`.rst( rst ),`
327			`.row_adr( row_adr ),`
328			`.bank_adr( bank_adr ),`
329			`.bank_set( bank_set_4 ),`
330			`.bank_clr( bank_clr_4 ),`
331			`.bank_clr_all( bank_clr_all_4 ),`
332			`.bank_open( bank_open_4 ),`
333			`.any_bank_open( any_bank_open_4 ),`
334			`.row_same( row_same_4 )`
335			`);`
336			`endif
337
338			`ifdef MC_HAVE_CS5
339			`mc_obct u5(`
340			`.clk( clk ),`
341			`.rst( rst ),`
342			`.row_adr( row_adr ),`
343			`.bank_adr( bank_adr ),`
344			`.bank_set( bank_set_5 ),`
345			`.bank_clr( bank_clr_5 ),`
346			`.bank_clr_all( bank_clr_all_5 ),`
347			`.bank_open( bank_open_5 ),`
348			`.any_bank_open( any_bank_open_5 ),`
349			`.row_same( row_same_5 )`
350			`);`
351			`else
352			`mc_obct_dummy u5(`
353			`.clk( clk ),`
354			`.rst( rst ),`
355			`.row_adr( row_adr ),`
356			`.bank_adr( bank_adr ),`
357			`.bank_set( bank_set_5 ),`
358			`.bank_clr( bank_clr_5 ),`
359			`.bank_clr_all( bank_clr_all_5 ),`
360			`.bank_open( bank_open_5 ),`
361			`.any_bank_open( any_bank_open_5 ),`
362			`.row_same( row_same_5 )`
363			`);`
364			`endif
365
366			`ifdef MC_HAVE_CS6
367			`mc_obct u6(`
368			`.clk( clk ),`
369			`.rst( rst ),`
370			`.row_adr( row_adr ),`
371			`.bank_adr( bank_adr ),`
372			`.bank_set( bank_set_6 ),`
373			`.bank_clr( bank_clr_6 ),`
374			`.bank_clr_all( bank_clr_all_6 ),`
375			`.bank_open( bank_open_6 ),`
376			`.any_bank_open( any_bank_open_6 ),`
377			`.row_same( row_same_6 )`
378			`);`
379			`else
380			`mc_obct_dummy u6(`
381			`.clk( clk ),`
382			`.rst( rst ),`
383			`.row_adr( row_adr ),`
384			`.bank_adr( bank_adr ),`
385			`.bank_set( bank_set_6 ),`
386			`.bank_clr( bank_clr_6 ),`
387			`.bank_clr_all( bank_clr_all_6 ),`
388			`.bank_open( bank_open_6 ),`
389			`.any_bank_open( any_bank_open_6 ),`
390			`.row_same( row_same_6 )`
391			`);`
392			`endif
393
394			`ifdef MC_HAVE_CS7
395			`mc_obct u7(`
396			`.clk( clk ),`
397			`.rst( rst ),`
398			`.row_adr( row_adr ),`
399			`.bank_adr( bank_adr ),`
400			`.bank_set( bank_set_7 ),`
401			`.bank_clr( bank_clr_7 ),`
402			`.bank_clr_all( bank_clr_all_7 ),`
403			`.bank_open( bank_open_7 ),`
404			`.any_bank_open( any_bank_open_7 ),`
405			`.row_same( row_same_7 )`
406			`);`
407			`else
408			`mc_obct_dummy u7(`
409			`.clk( clk ),`
410			`.rst( rst ),`
411			`.row_adr( row_adr ),`
412			`.bank_adr( bank_adr ),`
413			`.bank_set( bank_set_7 ),`
414			`.bank_clr( bank_clr_7 ),`
415			`.bank_clr_all( bank_clr_all_7 ),`
416			`.bank_open( bank_open_7 ),`
417			`.any_bank_open( any_bank_open_7 ),`
418			`.row_same( row_same_7 )`
419			`);`
420			`endif
421
422			`endmodule`