URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [mem_if/] [rtl/] [verilog/] [mc_rd_fifo.v] - Blame information for rev 12

Details | Compare with Previous | View Log


/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Memory Controller                                 ////
////  Read FIFO                                                  ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/mem_ctrl/  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: mc_rd_fifo.v,v 1.4 2002-01-21 13:08:52 rudi Exp $
//
//  $Date: 2002-01-21 13:08:52 $
//  $Revision: 1.4 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.3  2001/12/11 02:47:19  rudi
//
//               - Made some changes not to expect clock during reset ...
//
//               Revision 1.2  2001/11/29 02:16:28  rudi
//
//
//               - More Synthesis cleanup, mostly for speed
//               - Several bug fixes
//               - Changed code to avoid auto-precharge and
//                 burst-terminate combinations (apparently illegal ?)
//                 Now we will do a manual precharge ...
//
//               Revision 1.1  2001/07/29 07:34:41  rudi
//
//
//               1) Changed Directory Structure
//               2) Fixed several minor bugs
//
//               Revision 1.1.1.1  2001/05/13 09:39:44  rudi
//               Created Directory Structure
//
//
//
//
 
`include "mc_defines.v"
 
module mc_rd_fifo(clk, rst, clr, din, we, dout, re);
 
input           clk, rst, clr;
input   [35:0]   din;
input           we;
output  [35:0]   dout;
input           re;
 
reg     [3:0]    rd_adr, wr_adr;
reg     [35:0]   r0, r1, r2, r3;
reg     [35:0]   dout;
 
always @(posedge clk or posedge rst)
        if(rst)         rd_adr <= #1 4'h1;
        else
        if(clr)         rd_adr <= #1 4'h1;
        else
        if(re)          rd_adr <= #1 {rd_adr[2:0], rd_adr[3]};
 
always @(posedge clk or posedge rst)
        if(rst)         wr_adr <= #1 4'h1;
        else
        if(clr)         wr_adr <= #1 4'h1;
        else
        if(we)          wr_adr <= #1 {wr_adr[2:0], wr_adr[3]};
 
always @(posedge clk)
        if(we & wr_adr[0])       r0 <= #1 din;
 
always @(posedge clk)
        if(we & wr_adr[1])      r1 <= #1 din;
 
always @(posedge clk)
        if(we & wr_adr[2])      r2 <= #1 din;
 
always @(posedge clk)
        if(we & wr_adr[3])      r3 <= #1 din;
 
always @(rd_adr or r0 or r1 or r2 or r3 or re or we or din)
        case(rd_adr)            // synopsys full_case parallel_case
           4'h1:        dout = r0;
           4'h2:        dout = r1;
           4'h4:        dout = r2;
           4'h8:        dout = r3;
        endcase
 
endmodule

Line No.	Rev	Author	Line
1	12	xianfeng	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Memory Controller ////`
4			`//// Read FIFO ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
16			`//// www.asics.ws ////`
17			`//// rudi@asics.ws ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer.////`
23			`//// ////`
24			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
25			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
26			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
27			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
28			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
29			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
30			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
31			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
32			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
33			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
34			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
35			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
36			`//// POSSIBILITY OF SUCH DAMAGE. ////`
37			`//// ////`
38			`/////////////////////////////////////////////////////////////////////`
39
40			`// CVS Log`
41			`//`
42			`// $Id: mc_rd_fifo.v,v 1.4 2002-01-21 13:08:52 rudi Exp $`
43			`//`
44			`// $Date: 2002-01-21 13:08:52 $`
45			`// $Revision: 1.4 $`
46			`// $Author: rudi $`
47			`// $Locker: $`
48			`// $State: Exp $`
49			`//`
50			`// Change History:`
51			`// $Log: not supported by cvs2svn $`
52			`// Revision 1.3 2001/12/11 02:47:19 rudi`
53			`//`
54			`// - Made some changes not to expect clock during reset ...`
55			`//`
56			`// Revision 1.2 2001/11/29 02:16:28 rudi`
57			`//`
58			`//`
59			`// - More Synthesis cleanup, mostly for speed`
60			`// - Several bug fixes`
61			`// - Changed code to avoid auto-precharge and`
62			`// burst-terminate combinations (apparently illegal ?)`
63			`// Now we will do a manual precharge ...`
64			`//`
65			`// Revision 1.1 2001/07/29 07:34:41 rudi`
66			`//`
67			`//`
68			`// 1) Changed Directory Structure`
69			`// 2) Fixed several minor bugs`
70			`//`
71			`// Revision 1.1.1.1 2001/05/13 09:39:44 rudi`
72			`// Created Directory Structure`
73			`//`
74			`//`
75			`//`
76			`//`
77
78			`include "mc_defines.v"
79
80			`module mc_rd_fifo(clk, rst, clr, din, we, dout, re);`
81
82			`input clk, rst, clr;`
83			`input [35:0] din;`
84			`input we;`
85			`output [35:0] dout;`
86			`input re;`
87
88			`reg [3:0] rd_adr, wr_adr;`
89			`reg [35:0] r0, r1, r2, r3;`
90			`reg [35:0] dout;`
91
92			`always @(posedge clk or posedge rst)`
93			`if(rst) rd_adr <= #1 4'h1;`
94			`else`
95			`if(clr) rd_adr <= #1 4'h1;`
96			`else`
97			`if(re) rd_adr <= #1 {rd_adr[2:0], rd_adr[3]};`
98
99			`always @(posedge clk or posedge rst)`
100			`if(rst) wr_adr <= #1 4'h1;`
101			`else`
102			`if(clr) wr_adr <= #1 4'h1;`
103			`else`
104			`if(we) wr_adr <= #1 {wr_adr[2:0], wr_adr[3]};`
105
106			`always @(posedge clk)`
107			`if(we & wr_adr[0]) r0 <= #1 din;`
108
109			`always @(posedge clk)`
110			`if(we & wr_adr[1]) r1 <= #1 din;`
111
112			`always @(posedge clk)`
113			`if(we & wr_adr[2]) r2 <= #1 din;`
114
115			`always @(posedge clk)`
116			`if(we & wr_adr[3]) r3 <= #1 din;`
117
118			`always @(rd_adr or r0 or r1 or r2 or r3 or re or we or din)`
119			`case(rd_adr) // synopsys full_case parallel_case`
120			`4'h1: dout = r0;`
121			`4'h2: dout = r1;`
122			`4'h4: dout = r2;`
123			`4'h8: dout = r3;`
124			`endcase`
125
126			`endmodule`

Browse

Tools

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [mem_if/] [rtl/] [verilog/] [mc_rd_fifo.v] - Blame information for rev 12