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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [mmc_sd/] [RTL/] [initSD.v] - Blame information for rev 12

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// initSD.v                                                 ////
////                                                              ////
//// This file is part of the spiMaster opencores effort.
//// <http://www.opencores.org/cores//>                           ////
////                                                              ////
//// Module Description:                                          ////
//// When SDInitReq asserted, initialise SD card
////  
////  
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from <http://www.opencores.org/lgpl.shtml>                   ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "spiMaster_defines.v"
 
module initSD (checkSumByte, clk, cmdByte, dataByte1, dataByte2, dataByte3, dataByte4, initError, respByte, respTout, rst, rxDataRdy, rxDataRdyClr, SDInitRdy, SDInitReq, sendCmdRdy, sendCmdReq, spiClkDelayIn, spiClkDelayOut, spiCS_n, txDataEmpty, txDataFull, txDataOut, txDataWen);
input   clk;
input   [7:0]respByte;
input   respTout;
input   rst;
input   rxDataRdy;
input   SDInitReq;
input   sendCmdRdy;
input   [7:0]spiClkDelayIn;
input   txDataEmpty;
input   txDataFull;
output  [7:0]checkSumByte;
output  [7:0]cmdByte;
output  [7:0]dataByte1;
output  [7:0]dataByte2;
output  [7:0]dataByte3;
output  [7:0]dataByte4;
output  [1:0]initError;
output  rxDataRdyClr;
output  SDInitRdy;
output  sendCmdReq;
output  [7:0]spiClkDelayOut;
output  spiCS_n;
output  [7:0]txDataOut;
output  txDataWen;
 
reg     [7:0]checkSumByte, next_checkSumByte;
wire    clk;
reg     [7:0]cmdByte, next_cmdByte;
reg     [7:0]dataByte1, next_dataByte1;
reg     [7:0]dataByte2, next_dataByte2;
reg     [7:0]dataByte3, next_dataByte3;
reg     [7:0]dataByte4, next_dataByte4;
reg     [1:0]initError, next_initError;
wire    [7:0]respByte;
wire    respTout;
wire    rst;
wire    rxDataRdy;
reg     rxDataRdyClr, next_rxDataRdyClr;
reg     SDInitRdy, next_SDInitRdy;
wire    SDInitReq;
wire    sendCmdRdy;
reg     sendCmdReq, next_sendCmdReq;
wire    [7:0]spiClkDelayIn;
reg     [7:0]spiClkDelayOut, next_spiClkDelayOut;
reg     spiCS_n, next_spiCS_n;
wire    txDataEmpty;
wire    txDataFull;
reg     [7:0]txDataOut, next_txDataOut;
reg     txDataWen, next_txDataWen;
 
// diagram signals declarations
reg  [9:0]delCnt1, next_delCnt1;
reg  [7:0]delCnt2, next_delCnt2;
reg  [7:0]loopCnt, next_loopCnt;
 
// BINARY ENCODED state machine: initSDSt
// State codes definitions:
`define START 4'b0000
`define WT_INIT_REQ 4'b0001
`define CLK_SEQ_SEND_FF 4'b0010
`define CLK_SEQ_CHK_FIN 4'b0011
`define RESET_SEND_CMD 4'b0100
`define RESET_DEL 4'b0101
`define RESET_WT_FIN 4'b0110
`define RESET_CHK_FIN 4'b0111
`define INIT_WT_FIN 4'b1000
`define INIT_CHK_FIN 4'b1001
`define INIT_SEND_CMD 4'b1010
`define INIT_DEL1 4'b1011
`define INIT_DEL2 4'b1100
`define CLK_SEQ_WT_DATA_EMPTY 4'b1101
 
reg [3:0]CurrState_initSDSt, NextState_initSDSt;
 
// Diagram actions (continuous assignments allowed only: assign ...)
// diagram ACTION
 
 
// Machine: initSDSt
 
// NextState logic (combinatorial)
always @ (spiClkDelayIn or SDInitReq or txDataFull or loopCnt or sendCmdRdy or respTout or respByte or delCnt1 or delCnt2 or txDataEmpty or spiClkDelayOut or SDInitRdy or spiCS_n or initError or txDataOut or txDataWen or cmdByte or dataByte1 or dataByte2 or dataByte3 or dataByte4 or checkSumByte or sendCmdReq or rxDataRdyClr or CurrState_initSDSt)
begin
  NextState_initSDSt <= CurrState_initSDSt;
  // Set default values for outputs and signals
  next_spiClkDelayOut <= spiClkDelayOut;
  next_SDInitRdy <= SDInitRdy;
  next_spiCS_n <= spiCS_n;
  next_initError <= initError;
  next_txDataOut <= txDataOut;
  next_txDataWen <= txDataWen;
  next_cmdByte <= cmdByte;
  next_dataByte1 <= dataByte1;
  next_dataByte2 <= dataByte2;
  next_dataByte3 <= dataByte3;
  next_dataByte4 <= dataByte4;
  next_checkSumByte <= checkSumByte;
  next_sendCmdReq <= sendCmdReq;
  next_loopCnt <= loopCnt;
  next_delCnt1 <= delCnt1;
  next_delCnt2 <= delCnt2;
  next_rxDataRdyClr <= rxDataRdyClr;
  case (CurrState_initSDSt)  // synopsys parallel_case full_case
    `START:
    begin
      next_spiClkDelayOut <= spiClkDelayIn;
      next_SDInitRdy <= 1'b0;
      next_spiCS_n <= 1'b1;
      next_initError <= `INIT_NO_ERROR;
      next_txDataOut <= 8'h00;
      next_txDataWen <= 1'b0;
      next_cmdByte <= 8'h00;
      next_dataByte1 <= 8'h00;
      next_dataByte2 <= 8'h00;
      next_dataByte3 <= 8'h00;
      next_dataByte4 <= 8'h00;
      next_checkSumByte <= 8'h00;
      next_sendCmdReq <= 1'b0;
      next_loopCnt <= 8'h00;
      next_delCnt1 <= 10'h000;
      next_delCnt2 <= 8'h00;
      next_rxDataRdyClr <= 1'b0;
      NextState_initSDSt <= `WT_INIT_REQ;
    end
    `WT_INIT_REQ:
    begin
      next_SDInitRdy <= 1'b1;
      next_spiClkDelayOut <= spiClkDelayIn;
      next_cmdByte <= 8'h00;
      next_dataByte1 <= 8'h00;
      next_dataByte2 <= 8'h00;
      next_dataByte3 <= 8'h00;
      next_dataByte4 <= 8'h00;
      next_checkSumByte <= 8'h00;
      if (SDInitReq == 1'b1)
      begin
        NextState_initSDSt <= `CLK_SEQ_SEND_FF;
        next_SDInitRdy <= 1'b0;
        next_loopCnt <= 8'h00;
        next_spiClkDelayOut <= `SLOW_SPI_CLK;
        next_initError <= `INIT_NO_ERROR;
      end
    end
    `CLK_SEQ_SEND_FF:
    begin
      if (txDataFull == 1'b0)
      begin
        NextState_initSDSt <= `CLK_SEQ_CHK_FIN;
        next_txDataOut <= 8'hff;
        next_txDataWen <= 1'b1;
        next_loopCnt <= loopCnt + 1'b1;
      end
    end
    `CLK_SEQ_CHK_FIN:
    begin
      next_txDataWen <= 1'b0;
      if (loopCnt == `SD_INIT_START_SEQ_LEN)
      begin
        NextState_initSDSt <= `CLK_SEQ_WT_DATA_EMPTY;
      end
      else
      begin
        NextState_initSDSt <= `CLK_SEQ_SEND_FF;
      end
    end
    `CLK_SEQ_WT_DATA_EMPTY:
    begin
      if (txDataEmpty == 1'b1)
      begin
        NextState_initSDSt <= `RESET_SEND_CMD;
        next_loopCnt <= 8'h00;
      end
    end
    `RESET_SEND_CMD:
    begin
      next_cmdByte <= 8'h40;
      //CMD0
      next_dataByte1 <= 8'h00;
      next_dataByte2 <= 8'h00;
      next_dataByte3 <= 8'h00;
      next_dataByte4 <= 8'h00;
      next_checkSumByte <= 8'h95;
      next_sendCmdReq <= 1'b1;
      next_loopCnt <= loopCnt + 1'b1;
      next_spiCS_n <= 1'b0;
      NextState_initSDSt <= `RESET_DEL;
    end
    `RESET_DEL:
    begin
      next_sendCmdReq <= 1'b0;
      NextState_initSDSt <= `RESET_WT_FIN;
    end
    `RESET_WT_FIN:
    begin
      if (sendCmdRdy == 1'b1)
      begin
        NextState_initSDSt <= `RESET_CHK_FIN;
        next_spiCS_n <= 1'b1;
      end
    end
    `RESET_CHK_FIN:
    begin
      if ((respTout == 1'b1 || respByte != 8'h01) && loopCnt != 8'hff)
      begin
        NextState_initSDSt <= `RESET_SEND_CMD;
      end
      else if (respTout == 1'b1 || respByte != 8'h01)
      begin
        NextState_initSDSt <= `WT_INIT_REQ;
        next_initError <= `INIT_CMD0_ERROR;
      end
      else
      begin
        NextState_initSDSt <= `INIT_SEND_CMD;
      end
    end
    `INIT_WT_FIN:
    begin
      if (sendCmdRdy == 1'b1)
      begin
        NextState_initSDSt <= `INIT_CHK_FIN;
        next_spiCS_n <= 1'b1;
      end
    end
    `INIT_CHK_FIN:
    begin
      if ((respTout == 1'b1 || respByte != 8'h00) && loopCnt != 8'hff)
      begin
        NextState_initSDSt <= `INIT_SEND_CMD;
      end
      else if (respTout == 1'b1 || respByte != 8'h00)
      begin
        NextState_initSDSt <= `WT_INIT_REQ;
        next_initError <= `INIT_CMD1_ERROR;
      end
      else
      begin
        NextState_initSDSt <= `WT_INIT_REQ;
      end
    end
    `INIT_SEND_CMD:
    begin
      next_cmdByte <= 8'h41;
      //CMD1
      next_dataByte1 <= 8'h00;
      next_dataByte2 <= 8'h00;
      next_dataByte3 <= 8'h00;
      next_dataByte4 <= 8'h00;
      next_checkSumByte <= 8'hff;
      next_sendCmdReq <= 1'b1;
      next_loopCnt <= loopCnt + 1'b1;
      next_spiCS_n <= 1'b0;
      next_delCnt1 <= 10'h000;
      NextState_initSDSt <= `INIT_DEL1;
    end
    `INIT_DEL1:
    begin
      next_delCnt1 <= delCnt1 + 1'b1;
      next_delCnt2 <= 8'h00;
      next_sendCmdReq <= 1'b0;
      if (delCnt1 == `TWO_MS)
      begin
        NextState_initSDSt <= `INIT_WT_FIN;
      end
      else
      begin
        NextState_initSDSt <= `INIT_DEL2;
      end
    end
    `INIT_DEL2:
    begin
      next_delCnt2 <= delCnt2 + 1'b1;
      if (delCnt2 == 8'hff)
      begin
        NextState_initSDSt <= `INIT_DEL1;
      end
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst == 1'b1)
    CurrState_initSDSt <= `START;
  else
    CurrState_initSDSt <= NextState_initSDSt;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst == 1'b1)
  begin
    spiClkDelayOut <= spiClkDelayIn;
    SDInitRdy <= 1'b0;
    spiCS_n <= 1'b1;
    initError <= `INIT_NO_ERROR;
    txDataOut <= 8'h00;
    txDataWen <= 1'b0;
    cmdByte <= 8'h00;
    dataByte1 <= 8'h00;
    dataByte2 <= 8'h00;
    dataByte3 <= 8'h00;
    dataByte4 <= 8'h00;
    checkSumByte <= 8'h00;
    sendCmdReq <= 1'b0;
    rxDataRdyClr <= 1'b0;
    loopCnt <= 8'h00;
    delCnt1 <= 10'h000;
    delCnt2 <= 8'h00;
  end
  else
  begin
    spiClkDelayOut <= next_spiClkDelayOut;
    SDInitRdy <= next_SDInitRdy;
    spiCS_n <= next_spiCS_n;
    initError <= next_initError;
    txDataOut <= next_txDataOut;
    txDataWen <= next_txDataWen;
    cmdByte <= next_cmdByte;
    dataByte1 <= next_dataByte1;
    dataByte2 <= next_dataByte2;
    dataByte3 <= next_dataByte3;
    dataByte4 <= next_dataByte4;
    checkSumByte <= next_checkSumByte;
    sendCmdReq <= next_sendCmdReq;
    rxDataRdyClr <= next_rxDataRdyClr;
    loopCnt <= next_loopCnt;
    delCnt1 <= next_delCnt1;
    delCnt2 <= next_delCnt2;
  end
end
 
endmodule

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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [mmc_sd/] [RTL/] [initSD.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	xianfeng
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// initSD.v ////`
5			`//// ////`
6			`//// This file is part of the spiMaster opencores effort.`
7			`//// <http://www.opencores.org/cores//> ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`//// When SDInitReq asserted, initialise SD card`
11			`////`
12			`////`
13			`////`
14			`//// ////`
15			`//// To Do: ////`
16			`////`
17			`//// ////`
18			`//// Author(s): ////`
19			`//// - Steve Fielding, sfielding@base2designs.com ////`
20			`//// ////`
21			`//////////////////////////////////////////////////////////////////////`
22			`//// ////`
23			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
24			`//// ////`
25			`//// This source file may be used and distributed without ////`
26			`//// restriction provided that this copyright statement is not ////`
27			`//// removed from the file and that any derivative work contains ////`
28			`//// the original copyright notice and the associated disclaimer. ////`
29			`//// ////`
30			`//// This source file is free software; you can redistribute it ////`
31			`//// and/or modify it under the terms of the GNU Lesser General ////`
32			`//// Public License as published by the Free Software Foundation; ////`
33			`//// either version 2.1 of the License, or (at your option) any ////`
34			`//// later version. ////`
35			`//// ////`
36			`//// This source is distributed in the hope that it will be ////`
37			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
38			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
39			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
40			`//// details. ////`
41			`//// ////`
42			`//// You should have received a copy of the GNU Lesser General ////`
43			`//// Public License along with this source; if not, download it ////`
44			`//// from <http://www.opencores.org/lgpl.shtml> ////`
45			`//// ////`
46			`//////////////////////////////////////////////////////////////////////`
47			`//`
48			`include "timescale.v"
49			`include "spiMaster_defines.v"
50
51			`module initSD (checkSumByte, clk, cmdByte, dataByte1, dataByte2, dataByte3, dataByte4, initError, respByte, respTout, rst, rxDataRdy, rxDataRdyClr, SDInitRdy, SDInitReq, sendCmdRdy, sendCmdReq, spiClkDelayIn, spiClkDelayOut, spiCS_n, txDataEmpty, txDataFull, txDataOut, txDataWen);`
52			`input clk;`
53			`input [7:0]respByte;`
54			`input respTout;`
55			`input rst;`
56			`input rxDataRdy;`
57			`input SDInitReq;`
58			`input sendCmdRdy;`
59			`input [7:0]spiClkDelayIn;`
60			`input txDataEmpty;`
61			`input txDataFull;`
62			`output [7:0]checkSumByte;`
63			`output [7:0]cmdByte;`
64			`output [7:0]dataByte1;`
65			`output [7:0]dataByte2;`
66			`output [7:0]dataByte3;`
67			`output [7:0]dataByte4;`
68			`output [1:0]initError;`
69			`output rxDataRdyClr;`
70			`output SDInitRdy;`
71			`output sendCmdReq;`
72			`output [7:0]spiClkDelayOut;`
73			`output spiCS_n;`
74			`output [7:0]txDataOut;`
75			`output txDataWen;`
76
77			`reg [7:0]checkSumByte, next_checkSumByte;`
78			`wire clk;`
79			`reg [7:0]cmdByte, next_cmdByte;`
80			`reg [7:0]dataByte1, next_dataByte1;`
81			`reg [7:0]dataByte2, next_dataByte2;`
82			`reg [7:0]dataByte3, next_dataByte3;`
83			`reg [7:0]dataByte4, next_dataByte4;`
84			`reg [1:0]initError, next_initError;`
85			`wire [7:0]respByte;`
86			`wire respTout;`
87			`wire rst;`
88			`wire rxDataRdy;`
89			`reg rxDataRdyClr, next_rxDataRdyClr;`
90			`reg SDInitRdy, next_SDInitRdy;`
91			`wire SDInitReq;`
92			`wire sendCmdRdy;`
93			`reg sendCmdReq, next_sendCmdReq;`
94			`wire [7:0]spiClkDelayIn;`
95			`reg [7:0]spiClkDelayOut, next_spiClkDelayOut;`
96			`reg spiCS_n, next_spiCS_n;`
97			`wire txDataEmpty;`
98			`wire txDataFull;`
99			`reg [7:0]txDataOut, next_txDataOut;`
100			`reg txDataWen, next_txDataWen;`
101
102			`// diagram signals declarations`
103			`reg [9:0]delCnt1, next_delCnt1;`
104			`reg [7:0]delCnt2, next_delCnt2;`
105			`reg [7:0]loopCnt, next_loopCnt;`
106
107			`// BINARY ENCODED state machine: initSDSt`
108			`// State codes definitions:`
109			`define START 4'b0000
110			`define WT_INIT_REQ 4'b0001
111			`define CLK_SEQ_SEND_FF 4'b0010
112			`define CLK_SEQ_CHK_FIN 4'b0011
113			`define RESET_SEND_CMD 4'b0100
114			`define RESET_DEL 4'b0101
115			`define RESET_WT_FIN 4'b0110
116			`define RESET_CHK_FIN 4'b0111
117			`define INIT_WT_FIN 4'b1000
118			`define INIT_CHK_FIN 4'b1001
119			`define INIT_SEND_CMD 4'b1010
120			`define INIT_DEL1 4'b1011
121			`define INIT_DEL2 4'b1100
122			`define CLK_SEQ_WT_DATA_EMPTY 4'b1101
123
124			`reg [3:0]CurrState_initSDSt, NextState_initSDSt;`
125
126			`// Diagram actions (continuous assignments allowed only: assign ...)`
127			`// diagram ACTION`
128
129
130			`// Machine: initSDSt`
131
132			`// NextState logic (combinatorial)`
133			`always @ (spiClkDelayIn or SDInitReq or txDataFull or loopCnt or sendCmdRdy or respTout or respByte or delCnt1 or delCnt2 or txDataEmpty or spiClkDelayOut or SDInitRdy or spiCS_n or initError or txDataOut or txDataWen or cmdByte or dataByte1 or dataByte2 or dataByte3 or dataByte4 or checkSumByte or sendCmdReq or rxDataRdyClr or CurrState_initSDSt)`
134			`begin`
135			`NextState_initSDSt <= CurrState_initSDSt;`
136			`// Set default values for outputs and signals`
137			`next_spiClkDelayOut <= spiClkDelayOut;`
138			`next_SDInitRdy <= SDInitRdy;`
139			`next_spiCS_n <= spiCS_n;`
140			`next_initError <= initError;`
141			`next_txDataOut <= txDataOut;`
142			`next_txDataWen <= txDataWen;`
143			`next_cmdByte <= cmdByte;`
144			`next_dataByte1 <= dataByte1;`
145			`next_dataByte2 <= dataByte2;`
146			`next_dataByte3 <= dataByte3;`
147			`next_dataByte4 <= dataByte4;`
148			`next_checkSumByte <= checkSumByte;`
149			`next_sendCmdReq <= sendCmdReq;`
150			`next_loopCnt <= loopCnt;`
151			`next_delCnt1 <= delCnt1;`
152			`next_delCnt2 <= delCnt2;`
153			`next_rxDataRdyClr <= rxDataRdyClr;`
154			`case (CurrState_initSDSt) // synopsys parallel_case full_case`
155			`START:
156			`begin`
157			`next_spiClkDelayOut <= spiClkDelayIn;`
158			`next_SDInitRdy <= 1'b0;`
159			`next_spiCS_n <= 1'b1;`
160			next_initError <= `INIT_NO_ERROR;
161			`next_txDataOut <= 8'h00;`
162			`next_txDataWen <= 1'b0;`
163			`next_cmdByte <= 8'h00;`
164			`next_dataByte1 <= 8'h00;`
165			`next_dataByte2 <= 8'h00;`
166			`next_dataByte3 <= 8'h00;`
167			`next_dataByte4 <= 8'h00;`
168			`next_checkSumByte <= 8'h00;`
169			`next_sendCmdReq <= 1'b0;`
170			`next_loopCnt <= 8'h00;`
171			`next_delCnt1 <= 10'h000;`
172			`next_delCnt2 <= 8'h00;`
173			`next_rxDataRdyClr <= 1'b0;`
174			NextState_initSDSt <= `WT_INIT_REQ;
175			`end`
176			`WT_INIT_REQ:
177			`begin`
178			`next_SDInitRdy <= 1'b1;`
179			`next_spiClkDelayOut <= spiClkDelayIn;`
180			`next_cmdByte <= 8'h00;`
181			`next_dataByte1 <= 8'h00;`
182			`next_dataByte2 <= 8'h00;`
183			`next_dataByte3 <= 8'h00;`
184			`next_dataByte4 <= 8'h00;`
185			`next_checkSumByte <= 8'h00;`
186			`if (SDInitReq == 1'b1)`
187			`begin`
188			NextState_initSDSt <= `CLK_SEQ_SEND_FF;
189			`next_SDInitRdy <= 1'b0;`
190			`next_loopCnt <= 8'h00;`
191			next_spiClkDelayOut <= `SLOW_SPI_CLK;
192			next_initError <= `INIT_NO_ERROR;
193			`end`
194			`end`
195			`CLK_SEQ_SEND_FF:
196			`begin`
197			`if (txDataFull == 1'b0)`
198			`begin`
199			NextState_initSDSt <= `CLK_SEQ_CHK_FIN;
200			`next_txDataOut <= 8'hff;`
201			`next_txDataWen <= 1'b1;`
202			`next_loopCnt <= loopCnt + 1'b1;`
203			`end`
204			`end`
205			`CLK_SEQ_CHK_FIN:
206			`begin`
207			`next_txDataWen <= 1'b0;`
208			if (loopCnt == `SD_INIT_START_SEQ_LEN)
209			`begin`
210			NextState_initSDSt <= `CLK_SEQ_WT_DATA_EMPTY;
211			`end`
212			`else`
213			`begin`
214			NextState_initSDSt <= `CLK_SEQ_SEND_FF;
215			`end`
216			`end`
217			`CLK_SEQ_WT_DATA_EMPTY:
218			`begin`
219			`if (txDataEmpty == 1'b1)`
220			`begin`
221			NextState_initSDSt <= `RESET_SEND_CMD;
222			`next_loopCnt <= 8'h00;`
223			`end`
224			`end`
225			`RESET_SEND_CMD:
226			`begin`
227			`next_cmdByte <= 8'h40;`
228			`//CMD0`
229			`next_dataByte1 <= 8'h00;`
230			`next_dataByte2 <= 8'h00;`
231			`next_dataByte3 <= 8'h00;`
232			`next_dataByte4 <= 8'h00;`
233			`next_checkSumByte <= 8'h95;`
234			`next_sendCmdReq <= 1'b1;`
235			`next_loopCnt <= loopCnt + 1'b1;`
236			`next_spiCS_n <= 1'b0;`
237			NextState_initSDSt <= `RESET_DEL;
238			`end`
239			`RESET_DEL:
240			`begin`
241			`next_sendCmdReq <= 1'b0;`
242			NextState_initSDSt <= `RESET_WT_FIN;
243			`end`
244			`RESET_WT_FIN:
245			`begin`
246			`if (sendCmdRdy == 1'b1)`
247			`begin`
248			NextState_initSDSt <= `RESET_CHK_FIN;
249			`next_spiCS_n <= 1'b1;`
250			`end`
251			`end`
252			`RESET_CHK_FIN:
253			`begin`
254			`if ((respTout == 1'b1 \|\| respByte != 8'h01) && loopCnt != 8'hff)`
255			`begin`
256			NextState_initSDSt <= `RESET_SEND_CMD;
257			`end`
258			`else if (respTout == 1'b1 \|\| respByte != 8'h01)`
259			`begin`
260			NextState_initSDSt <= `WT_INIT_REQ;
261			next_initError <= `INIT_CMD0_ERROR;
262			`end`
263			`else`
264			`begin`
265			NextState_initSDSt <= `INIT_SEND_CMD;
266			`end`
267			`end`
268			`INIT_WT_FIN:
269			`begin`
270			`if (sendCmdRdy == 1'b1)`
271			`begin`
272			NextState_initSDSt <= `INIT_CHK_FIN;
273			`next_spiCS_n <= 1'b1;`
274			`end`
275			`end`
276			`INIT_CHK_FIN:
277			`begin`
278			`if ((respTout == 1'b1 \|\| respByte != 8'h00) && loopCnt != 8'hff)`
279			`begin`
280			NextState_initSDSt <= `INIT_SEND_CMD;
281			`end`
282			`else if (respTout == 1'b1 \|\| respByte != 8'h00)`
283			`begin`
284			NextState_initSDSt <= `WT_INIT_REQ;
285			next_initError <= `INIT_CMD1_ERROR;
286			`end`
287			`else`
288			`begin`
289			NextState_initSDSt <= `WT_INIT_REQ;
290			`end`
291			`end`
292			`INIT_SEND_CMD:
293			`begin`
294			`next_cmdByte <= 8'h41;`
295			`//CMD1`
296			`next_dataByte1 <= 8'h00;`
297			`next_dataByte2 <= 8'h00;`
298			`next_dataByte3 <= 8'h00;`
299			`next_dataByte4 <= 8'h00;`
300			`next_checkSumByte <= 8'hff;`
301			`next_sendCmdReq <= 1'b1;`
302			`next_loopCnt <= loopCnt + 1'b1;`
303			`next_spiCS_n <= 1'b0;`
304			`next_delCnt1 <= 10'h000;`
305			NextState_initSDSt <= `INIT_DEL1;
306			`end`
307			`INIT_DEL1:
308			`begin`
309			`next_delCnt1 <= delCnt1 + 1'b1;`
310			`next_delCnt2 <= 8'h00;`
311			`next_sendCmdReq <= 1'b0;`
312			if (delCnt1 == `TWO_MS)
313			`begin`
314			NextState_initSDSt <= `INIT_WT_FIN;
315			`end`
316			`else`
317			`begin`
318			NextState_initSDSt <= `INIT_DEL2;
319			`end`
320			`end`
321			`INIT_DEL2:
322			`begin`
323			`next_delCnt2 <= delCnt2 + 1'b1;`
324			`if (delCnt2 == 8'hff)`
325			`begin`
326			NextState_initSDSt <= `INIT_DEL1;
327			`end`
328			`end`
329			`endcase`
330			`end`
331
332			`// Current State Logic (sequential)`
333			`always @ (posedge clk)`
334			`begin`
335			`if (rst == 1'b1)`
336			CurrState_initSDSt <= `START;
337			`else`
338			`CurrState_initSDSt <= NextState_initSDSt;`
339			`end`
340
341			`// Registered outputs logic`
342			`always @ (posedge clk)`
343			`begin`
344			`if (rst == 1'b1)`
345			`begin`
346			`spiClkDelayOut <= spiClkDelayIn;`
347			`SDInitRdy <= 1'b0;`
348			`spiCS_n <= 1'b1;`
349			initError <= `INIT_NO_ERROR;
350			`txDataOut <= 8'h00;`
351			`txDataWen <= 1'b0;`
352			`cmdByte <= 8'h00;`
353			`dataByte1 <= 8'h00;`
354			`dataByte2 <= 8'h00;`
355			`dataByte3 <= 8'h00;`
356			`dataByte4 <= 8'h00;`
357			`checkSumByte <= 8'h00;`
358			`sendCmdReq <= 1'b0;`
359			`rxDataRdyClr <= 1'b0;`
360			`loopCnt <= 8'h00;`
361			`delCnt1 <= 10'h000;`
362			`delCnt2 <= 8'h00;`
363			`end`
364			`else`
365			`begin`
366			`spiClkDelayOut <= next_spiClkDelayOut;`
367			`SDInitRdy <= next_SDInitRdy;`
368			`spiCS_n <= next_spiCS_n;`
369			`initError <= next_initError;`
370			`txDataOut <= next_txDataOut;`
371			`txDataWen <= next_txDataWen;`
372			`cmdByte <= next_cmdByte;`
373			`dataByte1 <= next_dataByte1;`
374			`dataByte2 <= next_dataByte2;`
375			`dataByte3 <= next_dataByte3;`
376			`dataByte4 <= next_dataByte4;`
377			`checkSumByte <= next_checkSumByte;`
378			`sendCmdReq <= next_sendCmdReq;`
379			`rxDataRdyClr <= next_rxDataRdyClr;`
380			`loopCnt <= next_loopCnt;`
381			`delCnt1 <= next_delCnt1;`
382			`delCnt2 <= next_delCnt2;`
383			`end`
384			`end`
385
386			`endmodule`