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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [mmc_sd/] [RTL/] [spiMaster.v] - Blame information for rev 12

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// spiMaster.v                                                    ////
////                                                              ////
//// This file is part of the spiMaster opencores effort.
//// <http://www.opencores.org/cores//>                           ////
////                                                              ////
//// Module Description:                                          ////
////  Top level module
//// 
////  
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from <http://www.opencores.org/lgpl.shtml>                   ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "spiMaster_defines.v"
 
module spiMaster(
  clk_i,
  rst_i,
  address_i,
  data_i,
  data_o,
  strobe_i,
  we_i,
  ack_o,
 
  // SPI logic clock
  spiSysClk,
 
  //SPI bus
  spiClkOut,
  spiDataIn,
  spiDataOut,
  spiCS_n
);
 
//Wishbone bus
input clk_i;
input rst_i;
input [7:0] address_i;
input [7:0] data_i;
output [7:0] data_o;
input strobe_i;
input we_i;
output ack_o;
 
// SPI logic clock
input spiSysClk;
 
//SPI bus
output spiClkOut;
input spiDataIn;
output spiDataOut;
output spiCS_n;
 
// local wires and regs
wire spiSysClk;
wire [7:0] spiClkDelayFromInitSD;
wire rstSyncToSpiClk;
wire [7:0] rxDataFromRWSPIWireData;
wire rxDataRdySetFromRWSPIWireData;
wire txDataFullFromSpiTxRxData;
wire txDataFullClrFromRWSPIWireData;
wire [7:0] txDataToRWSPIWireData;
wire rxDataRdyClrFromRWSDBlock;
wire rxDataRdyClrFromSendCmd;
wire [7:0] rxDataFromSpiTxRxData;
wire rxDataRdy;
wire [7:0] txDataFromRWSDBlock;
wire txDataWenFromRWSDBlock;
wire [7:0] txDataFromSendCmd;
wire txDataWenFromSendCmd;
wire [7:0] txDataFromInitSD;
wire txDataWenFromInitSD;
wire [7:0] dataFromCtrlStsReg;
wire [7:0] dataFromTxFifo;
wire [7:0] dataFromRxFifo;
wire [1:0] spiTransType;
wire [7:0] spiDirectAccessTxData;
wire [1:0] readWriteSDBlockReq;
wire [1:0] SDWriteError;
wire [1:0] SDReadError;
wire [1:0] SDInitError;
wire [7:0] cmdByteFromInitSD;
wire [7:0] dataByte1FromInitSD;
wire [7:0] dataByte2FromInitSD;
wire [7:0] dataByte3FromInitSD;
wire [7:0] dataByte4FromInitSD;
wire [7:0] checkSumByteFromInitSD;
wire [7:0] sendCmdRespByte;
wire [7:0] cmdByteFromRWSDBlock;
wire [7:0] dataByte1FromRWSDBlock;
wire [7:0] dataByte2FromRWSDBlock;
wire [7:0] dataByte3FromRWSDBlock;
wire [7:0] dataByte4FromRWSDBlock;
wire [7:0] checkSumByteFromRWSDBlock;
wire [7:0] txFifoDataOut;
wire [7:0] rxFifoDataIn;
wire [31:0] SDAddr;
wire [7:0] spiClkDelayFromCtrlStsReg;
wire spiCS_nFromInitSD;
wire spiCS_nFromRWSDBlock;
wire spiCS_nFromSpiCtrl;
 
 
assign spiCS_n = spiCS_nFromInitSD & spiCS_nFromRWSDBlock & spiCS_nFromSpiCtrl;
 
// -----------------------------------
// Instance of Module: wishBoneBI
// -----------------------------------
spiMasterWishBoneBI u_spiMasterWishBoneBI(
  .ack_o(               ack_o                 ),
  .address(             address_i             ),
  .clk(                 clk_i                 ),
  .ctrlStsRegSel(       ctrlStsRegSel         ),
  .dataFromCtrlStsReg(  dataFromCtrlStsReg    ),
  .dataFromRxFifo(      dataFromRxFifo        ),
  .dataFromTxFifo(      dataFromTxFifo        ),
  .dataIn(              data_i                ),
  .dataOut(             data_o                ),
  .rst(                 rst_i                 ),
  .rxFifoSel(           rxFifoSel             ),
  .strobe_i(            strobe_i              ),
  .txFifoSel(           txFifoSel             ),
  .writeEn(             we_i                  )
        );
 
// -----------------------------------
// Instance of Module: ctrlStsRegBI
// -----------------------------------
ctrlStsRegBI u_ctrlStsRegBI(
  .busClk(              clk_i                 ),
  .spiSysClk(           spiSysClk             ),
  .rstSyncToBusClkOut(  rstSyncToBusClk       ),
  .rstSyncToSpiClkOut(  rstSyncToSpiClk       ),
  .rstFromWire(         rst_i                 ),
  .address(             address_i             ),
  .strobe_i(            strobe_i              ),
  .dataIn(              data_i                ),
  .dataOut(             dataFromCtrlStsReg    ),
  .ctrlStsRegSel(       ctrlStsRegSel         ),
  .spiTransType(        spiTransType          ),
  .spiTransCtrl(        spiTransCtrl          ),
  .spiTransStatus(      spiTransSts           ),
  .spiDirectAccessTxData(spiDirectAccessTxData),
  .spiDirectAccessRxData(rxDataFromSpiTxRxData),
  .writeEn(             we_i                  ),
  .SDWriteError(        SDWriteError          ),
  .SDReadError(         SDReadError           ),
  .SDInitError(         SDInitError           ),
  .SDAddr(              SDAddr                ),
  .spiClkDelay(         spiClkDelayFromCtrlStsReg)
        );
 
// -----------------------------------
// Instance of Module: spiCtrl
// -----------------------------------
spiCtrl u_spiCtrl(
  .clk(                 spiSysClk             ),
  .rst(                 rstSyncToSpiClk       ),
  .SDInitReq(           SDInitReq             ),
  .SDInitRdy(           SDInitRdy             ),
  .readWriteSDBlockReq( readWriteSDBlockReq   ),
  .readWriteSDBlockRdy( readWriteSDBlockRdy   ),
  .rxDataRdy(           rxDataRdyFromSpiTxRxData),
  .rxDataRdyClr(        rxDataRdyClrFromSpiCtrl),
  .spiTransType(        spiTransType          ),
  .spiTransCtrl(        spiTransCtrl          ),
  .spiTransSts(         spiTransSts           ),
  .txDataWen(           txDataWenFromSpiCtrl  ),
  .spiCS_n(             spiCS_nFromSpiCtrl    )
        );
 
 
// -----------------------------------
// Instance of Module: initSD
// -----------------------------------
initSD u_initSD(
  .clk(                 spiSysClk             ),
  .rst(                 rstSyncToSpiClk       ),
  .SDInitReq(           SDInitReq             ),
  .SDInitRdy(           SDInitRdy             ),
  .initError(           SDInitError           ),
  .sendCmdReq(          sendCmdReqFromInitSD  ),
  .sendCmdRdy(          sendCmdRdy            ),
  .cmdByte(             cmdByteFromInitSD     ),
  .dataByte1(           dataByte1FromInitSD   ),
  .dataByte2(           dataByte2FromInitSD   ),
  .dataByte3(           dataByte3FromInitSD   ),
  .dataByte4(           dataByte4FromInitSD   ),
  .checkSumByte(        checkSumByteFromInitSD),
  .respByte(            sendCmdRespByte       ),
  .respTout(            sendCmdRespTout       ),
  .spiCS_n(             spiCS_nFromInitSD    ),
  .spiClkDelayOut(      spiClkDelayFromInitSD ),
  .spiClkDelayIn(       spiClkDelayFromCtrlStsReg),
  .txDataFull(          txDataFullFromSpiTxRxData),
  .txDataEmpty(         txDataEmptyFromRWSPIWireData),
  .txDataOut(           txDataFromInitSD      ),
  .txDataWen(           txDataWenFromInitSD   ),
  .rxDataRdy(           rxDataRdyFromSpiTxRxData),
  .rxDataRdyClr(        rxDataRdyClrFromInitSD)
        );
 
// -----------------------------------
// Instance of Module: readWriteSDBlock
// -----------------------------------
readWriteSDBlock u_readWriteSDBlock(
  .clk(                 spiSysClk             ),
  .rst(                 rstSyncToSpiClk       ),
  .readWriteSDBlockReq( readWriteSDBlockReq   ),
  .readWriteSDBlockRdy( readWriteSDBlockRdy   ),
  .cmdByte(             cmdByteFromRWSDBlock  ),
  .dataByte1(           dataByte1FromRWSDBlock),
  .dataByte2(           dataByte2FromRWSDBlock),
  .dataByte3(           dataByte3FromRWSDBlock),
  .dataByte4(           dataByte4FromRWSDBlock),
  .checkSumByte(        checkSumByteFromRWSDBlock),
  .readError(           SDReadError             ),
  .respByte(            sendCmdRespByte       ),
  .respTout(            sendCmdRespTout       ),
  .rxDataIn(            rxDataFromSpiTxRxData ),
  .rxDataRdy(           rxDataRdyFromSpiTxRxData),
  .rxDataRdyClr(        rxDataRdyClrFromRWSDBlock),
  .sendCmdRdy(          sendCmdRdy            ),
  .sendCmdReq(          sendCmdReqFromRWSDBlock),
  .spiCS_n(             spiCS_nFromRWSDBlock ),
  .txDataFull(          txDataFullFromSpiTxRxData),
  .txDataEmpty(         txDataEmptyFromRWSPIWireData),
  .txDataOut(           txDataFromRWSDBlock   ),
  .txDataWen(           txDataWenFromRWSDBlock),
  .txFifoData(          txFifoDataOut         ),
  .txFifoRen(           txFifoRE              ),
  .rxFifoData(          rxFifoDataIn          ),
  .rxFifoWen(           rRxFifoWE             ),
  .writeError(          SDWriteError          ),
  .blockAddr(           SDAddr                )
 
        );
 
// -----------------------------------
// Instance of Module: sendCmd
// -----------------------------------
sendCmd u_sendCmd(
  .clk(                 spiSysClk             ),
  .rst(                 rstSyncToSpiClk       ),
  .sendCmdReq1(         sendCmdReqFromInitSD  ),
  .sendCmdReq2(         sendCmdReqFromRWSDBlock),
  .sendCmdRdy(          sendCmdRdy            ),
  .cmdByte_1(           cmdByteFromInitSD     ),
  .cmdByte_2(           cmdByteFromRWSDBlock  ),
  .dataByte1_1(         dataByte1FromInitSD   ),
  .dataByte1_2(         dataByte1FromRWSDBlock),
  .dataByte2_1(         dataByte2FromInitSD   ),
  .dataByte2_2(         dataByte2FromRWSDBlock),
  .dataByte3_1(         dataByte3FromInitSD   ),
  .dataByte3_2(         dataByte3FromRWSDBlock),
  .dataByte4_1(         dataByte4FromInitSD   ),
  .dataByte4_2(         dataByte4FromRWSDBlock),
  .checkSumByte_1(      checkSumByteFromInitSD),
  .checkSumByte_2(      checkSumByteFromRWSDBlock),
  .respByte(            sendCmdRespByte       ),
  .respTout(            sendCmdRespTout       ),
  .rxDataIn(            rxDataFromSpiTxRxData ),
  .rxDataRdy(           rxDataRdyFromSpiTxRxData),
  .rxDataRdyClr(        rxDataRdyClrFromSendCmd),
  .txDataFull(          txDataFullFromSpiTxRxData),
  .txDataEmpty(         txDataEmptyFromRWSPIWireData),
  .txDataOut(           txDataFromSendCmd     ),
  .txDataWen(           txDataWenFromSendCmd  )
        );
 
// -----------------------------------
// Instance of Module: spiTxRxData
// -----------------------------------
spiTxRxData u_spiTxRxData(
  .clk(                 spiSysClk             ),
  .rst(                 rstSyncToSpiClk       ),
  .rx1DataRdyClr(       rxDataRdyClrFromRWSDBlock),
  .rx2DataRdyClr(       rxDataRdyClrFromSendCmd),
  .rx3DataRdyClr(       rxDataRdyClrFromInitSD),
  .rx4DataRdyClr(       rxDataRdyClrFromSpiCtrl),
  .rxDataIn(            rxDataFromRWSPIWireData),
  .rxDataOut(           rxDataFromSpiTxRxData ),
  .rxDataRdy(           rxDataRdyFromSpiTxRxData),
  .rxDataRdySet(        rxDataRdySetFromRWSPIWireData),
  .tx1DataIn(           txDataFromRWSDBlock   ),
  .tx1DataWEn(          txDataWenFromRWSDBlock),
  .tx2DataIn(           txDataFromSendCmd     ),
  .tx2DataWEn(          txDataWenFromSendCmd  ),
  .tx3DataIn(           txDataFromInitSD      ),
  .tx3DataWEn(          txDataWenFromInitSD   ),
  .tx4DataIn(           spiDirectAccessTxData ),
  .tx4DataWEn(          txDataWenFromSpiCtrl  ),
  .txDataFull(          txDataFullFromSpiTxRxData),
  .txDataFullClr(       txDataFullClrFromRWSPIWireData),
  .txDataOut(           txDataToRWSPIWireData )
        );
 
// -----------------------------------
// Instance of Module: readWriteSPIWireData
// -----------------------------------
readWriteSPIWireData u_readWriteSPIWireData(
  .clk(                 spiSysClk             ),
  .clkDelay(            spiClkDelayFromInitSD           ),
  .rst(                 rstSyncToSpiClk       ),
  .rxDataOut(           rxDataFromRWSPIWireData),
  .rxDataRdySet(        rxDataRdySetFromRWSPIWireData),
  .spiClkOut(           spiClkOut             ),
  .spiDataIn(           spiDataIn             ),
  .spiDataOut(          spiDataOut            ),
  .txDataFull(          txDataFullFromSpiTxRxData),
  .txDataFullClr(       txDataFullClrFromRWSPIWireData),
  .txDataIn(            txDataToRWSPIWireData ),
  .txDataEmpty(         txDataEmptyFromRWSPIWireData)
        );
 
sm_TxFifo #(`TX_FIFO_DEPTH, `TX_FIFO_ADDR_WIDTH) u_sm_txFifo (
  .spiSysClk(spiSysClk),
  .busClk(clk_i),
  .rstSyncToBusClk(rstSyncToBusClk),
  .rstSyncToSpiClk(rstSyncToSpiClk),
  .fifoREn(txFifoRE),
  .fifoEmpty(hostTxFifoEmpty),
  .busAddress(address_i[2:0]),
  .busWriteEn(we_i),
  .busStrobe_i(strobe_i),
  .busFifoSelect(txFifoSel),
  .busDataIn(data_i),
  .busDataOut(dataFromTxFifo),
  .fifoDataOut(txFifoDataOut) );
 
 
sm_RxFifo #(`RX_FIFO_DEPTH, `RX_FIFO_ADDR_WIDTH) u_sm_rxFifo(
  .spiSysClk(spiSysClk),
  .busClk(clk_i),
  .rstSyncToBusClk(rstSyncToBusClk),
  .rstSyncToSpiClk(rstSyncToSpiClk),
  .fifoWEn(rRxFifoWE),
  .fifoFull(hostRxFifoFull),
  .busAddress(address_i[2:0]),
  .busWriteEn(we_i),
  .busStrobe_i(strobe_i),
  .busFifoSelect(rxFifoSel),
  .busDataIn(data_i),
  .busDataOut(dataFromRxFifo),
  .fifoDataIn(rxFifoDataIn)  );
 
//
// SPI i/f monitor
//
// synopsys translate_off
integer fspi;
initial begin
        fspi = $fopen("spiMaster.log");
end
always @(posedge clk_i)
        if (strobe_i)
                if (ack_o)
                        if (we_i)
                                $fdisplay(fspi, "%t [%h] <- write %h", $time, address_i, data_i);
                        else
                                $fdisplay(fspi, "%t [%h] -> read %h", $time, address_i, data_o);
// synopsys translate_on
 
endmodule
 
 
 

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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [mmc_sd/] [RTL/] [spiMaster.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	xianfeng	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// spiMaster.v ////`
4			`//// ////`
5			`//// This file is part of the spiMaster opencores effort.`
6			`//// <http://www.opencores.org/cores//> ////`
7			`//// ////`
8			`//// Module Description: ////`
9			`//// Top level module`
10			`////`
11			`////`
12			`////`
13			`//// ////`
14			`//// To Do: ////`
15			`////`
16			`//// ////`
17			`//// Author(s): ////`
18			`//// - Steve Fielding, sfielding@base2designs.com ////`
19			`//// ////`
20			`//////////////////////////////////////////////////////////////////////`
21			`//// ////`
22			`//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////`
23			`//// ////`
24			`//// This source file may be used and distributed without ////`
25			`//// restriction provided that this copyright statement is not ////`
26			`//// removed from the file and that any derivative work contains ////`
27			`//// the original copyright notice and the associated disclaimer. ////`
28			`//// ////`
29			`//// This source file is free software; you can redistribute it ////`
30			`//// and/or modify it under the terms of the GNU Lesser General ////`
31			`//// Public License as published by the Free Software Foundation; ////`
32			`//// either version 2.1 of the License, or (at your option) any ////`
33			`//// later version. ////`
34			`//// ////`
35			`//// This source is distributed in the hope that it will be ////`
36			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
37			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
38			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
39			`//// details. ////`
40			`//// ////`
41			`//// You should have received a copy of the GNU Lesser General ////`
42			`//// Public License along with this source; if not, download it ////`
43			`//// from <http://www.opencores.org/lgpl.shtml> ////`
44			`//// ////`
45			`//////////////////////////////////////////////////////////////////////`
46			`//`
47			`include "timescale.v"
48			`include "spiMaster_defines.v"
49
50			`module spiMaster(`
51			`clk_i,`
52			`rst_i,`
53			`address_i,`
54			`data_i,`
55			`data_o,`
56			`strobe_i,`
57			`we_i,`
58			`ack_o,`
59
60			`// SPI logic clock`
61			`spiSysClk,`
62
63			`//SPI bus`
64			`spiClkOut,`
65			`spiDataIn,`
66			`spiDataOut,`
67			`spiCS_n`
68			`);`
69
70			`//Wishbone bus`
71			`input clk_i;`
72			`input rst_i;`
73			`input [7:0] address_i;`
74			`input [7:0] data_i;`
75			`output [7:0] data_o;`
76			`input strobe_i;`
77			`input we_i;`
78			`output ack_o;`
79
80			`// SPI logic clock`
81			`input spiSysClk;`
82
83			`//SPI bus`
84			`output spiClkOut;`
85			`input spiDataIn;`
86			`output spiDataOut;`
87			`output spiCS_n;`
88
89			`// local wires and regs`
90			`wire spiSysClk;`
91			`wire [7:0] spiClkDelayFromInitSD;`
92			`wire rstSyncToSpiClk;`
93			`wire [7:0] rxDataFromRWSPIWireData;`
94			`wire rxDataRdySetFromRWSPIWireData;`
95			`wire txDataFullFromSpiTxRxData;`
96			`wire txDataFullClrFromRWSPIWireData;`
97			`wire [7:0] txDataToRWSPIWireData;`
98			`wire rxDataRdyClrFromRWSDBlock;`
99			`wire rxDataRdyClrFromSendCmd;`
100			`wire [7:0] rxDataFromSpiTxRxData;`
101			`wire rxDataRdy;`
102			`wire [7:0] txDataFromRWSDBlock;`
103			`wire txDataWenFromRWSDBlock;`
104			`wire [7:0] txDataFromSendCmd;`
105			`wire txDataWenFromSendCmd;`
106			`wire [7:0] txDataFromInitSD;`
107			`wire txDataWenFromInitSD;`
108			`wire [7:0] dataFromCtrlStsReg;`
109			`wire [7:0] dataFromTxFifo;`
110			`wire [7:0] dataFromRxFifo;`
111			`wire [1:0] spiTransType;`
112			`wire [7:0] spiDirectAccessTxData;`
113			`wire [1:0] readWriteSDBlockReq;`
114			`wire [1:0] SDWriteError;`
115			`wire [1:0] SDReadError;`
116			`wire [1:0] SDInitError;`
117			`wire [7:0] cmdByteFromInitSD;`
118			`wire [7:0] dataByte1FromInitSD;`
119			`wire [7:0] dataByte2FromInitSD;`
120			`wire [7:0] dataByte3FromInitSD;`
121			`wire [7:0] dataByte4FromInitSD;`
122			`wire [7:0] checkSumByteFromInitSD;`
123			`wire [7:0] sendCmdRespByte;`
124			`wire [7:0] cmdByteFromRWSDBlock;`
125			`wire [7:0] dataByte1FromRWSDBlock;`
126			`wire [7:0] dataByte2FromRWSDBlock;`
127			`wire [7:0] dataByte3FromRWSDBlock;`
128			`wire [7:0] dataByte4FromRWSDBlock;`
129			`wire [7:0] checkSumByteFromRWSDBlock;`
130			`wire [7:0] txFifoDataOut;`
131			`wire [7:0] rxFifoDataIn;`
132			`wire [31:0] SDAddr;`
133			`wire [7:0] spiClkDelayFromCtrlStsReg;`
134			`wire spiCS_nFromInitSD;`
135			`wire spiCS_nFromRWSDBlock;`
136			`wire spiCS_nFromSpiCtrl;`
137
138
139			`assign spiCS_n = spiCS_nFromInitSD & spiCS_nFromRWSDBlock & spiCS_nFromSpiCtrl;`
140
141			`// -----------------------------------`
142			`// Instance of Module: wishBoneBI`
143			`// -----------------------------------`
144			`spiMasterWishBoneBI u_spiMasterWishBoneBI(`
145			`.ack_o( ack_o ),`
146			`.address( address_i ),`
147			`.clk( clk_i ),`
148			`.ctrlStsRegSel( ctrlStsRegSel ),`
149			`.dataFromCtrlStsReg( dataFromCtrlStsReg ),`
150			`.dataFromRxFifo( dataFromRxFifo ),`
151			`.dataFromTxFifo( dataFromTxFifo ),`
152			`.dataIn( data_i ),`
153			`.dataOut( data_o ),`
154			`.rst( rst_i ),`
155			`.rxFifoSel( rxFifoSel ),`
156			`.strobe_i( strobe_i ),`
157			`.txFifoSel( txFifoSel ),`
158			`.writeEn( we_i )`
159			`);`
160
161			`// -----------------------------------`
162			`// Instance of Module: ctrlStsRegBI`
163			`// -----------------------------------`
164			`ctrlStsRegBI u_ctrlStsRegBI(`
165			`.busClk( clk_i ),`
166			`.spiSysClk( spiSysClk ),`
167			`.rstSyncToBusClkOut( rstSyncToBusClk ),`
168			`.rstSyncToSpiClkOut( rstSyncToSpiClk ),`
169			`.rstFromWire( rst_i ),`
170			`.address( address_i ),`
171			`.strobe_i( strobe_i ),`
172			`.dataIn( data_i ),`
173			`.dataOut( dataFromCtrlStsReg ),`
174			`.ctrlStsRegSel( ctrlStsRegSel ),`
175			`.spiTransType( spiTransType ),`
176			`.spiTransCtrl( spiTransCtrl ),`
177			`.spiTransStatus( spiTransSts ),`
178			`.spiDirectAccessTxData(spiDirectAccessTxData),`
179			`.spiDirectAccessRxData(rxDataFromSpiTxRxData),`
180			`.writeEn( we_i ),`
181			`.SDWriteError( SDWriteError ),`
182			`.SDReadError( SDReadError ),`
183			`.SDInitError( SDInitError ),`
184			`.SDAddr( SDAddr ),`
185			`.spiClkDelay( spiClkDelayFromCtrlStsReg)`
186			`);`
187
188			`// -----------------------------------`
189			`// Instance of Module: spiCtrl`
190			`// -----------------------------------`
191			`spiCtrl u_spiCtrl(`
192			`.clk( spiSysClk ),`
193			`.rst( rstSyncToSpiClk ),`
194			`.SDInitReq( SDInitReq ),`
195			`.SDInitRdy( SDInitRdy ),`
196			`.readWriteSDBlockReq( readWriteSDBlockReq ),`
197			`.readWriteSDBlockRdy( readWriteSDBlockRdy ),`
198			`.rxDataRdy( rxDataRdyFromSpiTxRxData),`
199			`.rxDataRdyClr( rxDataRdyClrFromSpiCtrl),`
200			`.spiTransType( spiTransType ),`
201			`.spiTransCtrl( spiTransCtrl ),`
202			`.spiTransSts( spiTransSts ),`
203			`.txDataWen( txDataWenFromSpiCtrl ),`
204			`.spiCS_n( spiCS_nFromSpiCtrl )`
205			`);`
206
207
208			`// -----------------------------------`
209			`// Instance of Module: initSD`
210			`// -----------------------------------`
211			`initSD u_initSD(`
212			`.clk( spiSysClk ),`
213			`.rst( rstSyncToSpiClk ),`
214			`.SDInitReq( SDInitReq ),`
215			`.SDInitRdy( SDInitRdy ),`
216			`.initError( SDInitError ),`
217			`.sendCmdReq( sendCmdReqFromInitSD ),`
218			`.sendCmdRdy( sendCmdRdy ),`
219			`.cmdByte( cmdByteFromInitSD ),`
220			`.dataByte1( dataByte1FromInitSD ),`
221			`.dataByte2( dataByte2FromInitSD ),`
222			`.dataByte3( dataByte3FromInitSD ),`
223			`.dataByte4( dataByte4FromInitSD ),`
224			`.checkSumByte( checkSumByteFromInitSD),`
225			`.respByte( sendCmdRespByte ),`
226			`.respTout( sendCmdRespTout ),`
227			`.spiCS_n( spiCS_nFromInitSD ),`
228			`.spiClkDelayOut( spiClkDelayFromInitSD ),`
229			`.spiClkDelayIn( spiClkDelayFromCtrlStsReg),`
230			`.txDataFull( txDataFullFromSpiTxRxData),`
231			`.txDataEmpty( txDataEmptyFromRWSPIWireData),`
232			`.txDataOut( txDataFromInitSD ),`
233			`.txDataWen( txDataWenFromInitSD ),`
234			`.rxDataRdy( rxDataRdyFromSpiTxRxData),`
235			`.rxDataRdyClr( rxDataRdyClrFromInitSD)`
236			`);`
237
238			`// -----------------------------------`
239			`// Instance of Module: readWriteSDBlock`
240			`// -----------------------------------`
241			`readWriteSDBlock u_readWriteSDBlock(`
242			`.clk( spiSysClk ),`
243			`.rst( rstSyncToSpiClk ),`
244			`.readWriteSDBlockReq( readWriteSDBlockReq ),`
245			`.readWriteSDBlockRdy( readWriteSDBlockRdy ),`
246			`.cmdByte( cmdByteFromRWSDBlock ),`
247			`.dataByte1( dataByte1FromRWSDBlock),`
248			`.dataByte2( dataByte2FromRWSDBlock),`
249			`.dataByte3( dataByte3FromRWSDBlock),`
250			`.dataByte4( dataByte4FromRWSDBlock),`
251			`.checkSumByte( checkSumByteFromRWSDBlock),`
252			`.readError( SDReadError ),`
253			`.respByte( sendCmdRespByte ),`
254			`.respTout( sendCmdRespTout ),`
255			`.rxDataIn( rxDataFromSpiTxRxData ),`
256			`.rxDataRdy( rxDataRdyFromSpiTxRxData),`
257			`.rxDataRdyClr( rxDataRdyClrFromRWSDBlock),`
258			`.sendCmdRdy( sendCmdRdy ),`
259			`.sendCmdReq( sendCmdReqFromRWSDBlock),`
260			`.spiCS_n( spiCS_nFromRWSDBlock ),`
261			`.txDataFull( txDataFullFromSpiTxRxData),`
262			`.txDataEmpty( txDataEmptyFromRWSPIWireData),`
263			`.txDataOut( txDataFromRWSDBlock ),`
264			`.txDataWen( txDataWenFromRWSDBlock),`
265			`.txFifoData( txFifoDataOut ),`
266			`.txFifoRen( txFifoRE ),`
267			`.rxFifoData( rxFifoDataIn ),`
268			`.rxFifoWen( rRxFifoWE ),`
269			`.writeError( SDWriteError ),`
270			`.blockAddr( SDAddr )`
271
272			`);`
273
274			`// -----------------------------------`
275			`// Instance of Module: sendCmd`
276			`// -----------------------------------`
277			`sendCmd u_sendCmd(`
278			`.clk( spiSysClk ),`
279			`.rst( rstSyncToSpiClk ),`
280			`.sendCmdReq1( sendCmdReqFromInitSD ),`
281			`.sendCmdReq2( sendCmdReqFromRWSDBlock),`
282			`.sendCmdRdy( sendCmdRdy ),`
283			`.cmdByte_1( cmdByteFromInitSD ),`
284			`.cmdByte_2( cmdByteFromRWSDBlock ),`
285			`.dataByte1_1( dataByte1FromInitSD ),`
286			`.dataByte1_2( dataByte1FromRWSDBlock),`
287			`.dataByte2_1( dataByte2FromInitSD ),`
288			`.dataByte2_2( dataByte2FromRWSDBlock),`
289			`.dataByte3_1( dataByte3FromInitSD ),`
290			`.dataByte3_2( dataByte3FromRWSDBlock),`
291			`.dataByte4_1( dataByte4FromInitSD ),`
292			`.dataByte4_2( dataByte4FromRWSDBlock),`
293			`.checkSumByte_1( checkSumByteFromInitSD),`
294			`.checkSumByte_2( checkSumByteFromRWSDBlock),`
295			`.respByte( sendCmdRespByte ),`
296			`.respTout( sendCmdRespTout ),`
297			`.rxDataIn( rxDataFromSpiTxRxData ),`
298			`.rxDataRdy( rxDataRdyFromSpiTxRxData),`
299			`.rxDataRdyClr( rxDataRdyClrFromSendCmd),`
300			`.txDataFull( txDataFullFromSpiTxRxData),`
301			`.txDataEmpty( txDataEmptyFromRWSPIWireData),`
302			`.txDataOut( txDataFromSendCmd ),`
303			`.txDataWen( txDataWenFromSendCmd )`
304			`);`
305
306			`// -----------------------------------`
307			`// Instance of Module: spiTxRxData`
308			`// -----------------------------------`
309			`spiTxRxData u_spiTxRxData(`
310			`.clk( spiSysClk ),`
311			`.rst( rstSyncToSpiClk ),`
312			`.rx1DataRdyClr( rxDataRdyClrFromRWSDBlock),`
313			`.rx2DataRdyClr( rxDataRdyClrFromSendCmd),`
314			`.rx3DataRdyClr( rxDataRdyClrFromInitSD),`
315			`.rx4DataRdyClr( rxDataRdyClrFromSpiCtrl),`
316			`.rxDataIn( rxDataFromRWSPIWireData),`
317			`.rxDataOut( rxDataFromSpiTxRxData ),`
318			`.rxDataRdy( rxDataRdyFromSpiTxRxData),`
319			`.rxDataRdySet( rxDataRdySetFromRWSPIWireData),`
320			`.tx1DataIn( txDataFromRWSDBlock ),`
321			`.tx1DataWEn( txDataWenFromRWSDBlock),`
322			`.tx2DataIn( txDataFromSendCmd ),`
323			`.tx2DataWEn( txDataWenFromSendCmd ),`
324			`.tx3DataIn( txDataFromInitSD ),`
325			`.tx3DataWEn( txDataWenFromInitSD ),`
326			`.tx4DataIn( spiDirectAccessTxData ),`
327			`.tx4DataWEn( txDataWenFromSpiCtrl ),`
328			`.txDataFull( txDataFullFromSpiTxRxData),`
329			`.txDataFullClr( txDataFullClrFromRWSPIWireData),`
330			`.txDataOut( txDataToRWSPIWireData )`
331			`);`
332
333			`// -----------------------------------`
334			`// Instance of Module: readWriteSPIWireData`
335			`// -----------------------------------`
336			`readWriteSPIWireData u_readWriteSPIWireData(`
337			`.clk( spiSysClk ),`
338			`.clkDelay( spiClkDelayFromInitSD ),`
339			`.rst( rstSyncToSpiClk ),`
340			`.rxDataOut( rxDataFromRWSPIWireData),`
341			`.rxDataRdySet( rxDataRdySetFromRWSPIWireData),`
342			`.spiClkOut( spiClkOut ),`
343			`.spiDataIn( spiDataIn ),`
344			`.spiDataOut( spiDataOut ),`
345			`.txDataFull( txDataFullFromSpiTxRxData),`
346			`.txDataFullClr( txDataFullClrFromRWSPIWireData),`
347			`.txDataIn( txDataToRWSPIWireData ),`
348			`.txDataEmpty( txDataEmptyFromRWSPIWireData)`
349			`);`
350
351			sm_TxFifo #(`TX_FIFO_DEPTH, `TX_FIFO_ADDR_WIDTH) u_sm_txFifo (
352			`.spiSysClk(spiSysClk),`
353			`.busClk(clk_i),`
354			`.rstSyncToBusClk(rstSyncToBusClk),`
355			`.rstSyncToSpiClk(rstSyncToSpiClk),`
356			`.fifoREn(txFifoRE),`
357			`.fifoEmpty(hostTxFifoEmpty),`
358			`.busAddress(address_i[2:0]),`
359			`.busWriteEn(we_i),`
360			`.busStrobe_i(strobe_i),`
361			`.busFifoSelect(txFifoSel),`
362			`.busDataIn(data_i),`
363			`.busDataOut(dataFromTxFifo),`
364			`.fifoDataOut(txFifoDataOut) );`
365
366
367			sm_RxFifo #(`RX_FIFO_DEPTH, `RX_FIFO_ADDR_WIDTH) u_sm_rxFifo(
368			`.spiSysClk(spiSysClk),`
369			`.busClk(clk_i),`
370			`.rstSyncToBusClk(rstSyncToBusClk),`
371			`.rstSyncToSpiClk(rstSyncToSpiClk),`
372			`.fifoWEn(rRxFifoWE),`
373			`.fifoFull(hostRxFifoFull),`
374			`.busAddress(address_i[2:0]),`
375			`.busWriteEn(we_i),`
376			`.busStrobe_i(strobe_i),`
377			`.busFifoSelect(rxFifoSel),`
378			`.busDataIn(data_i),`
379			`.busDataOut(dataFromRxFifo),`
380			`.fifoDataIn(rxFifoDataIn) );`
381
382			`//`
383			`// SPI i/f monitor`
384			`//`
385			`// synopsys translate_off`
386			`integer fspi;`
387			`initial begin`
388			`fspi = $fopen("spiMaster.log");`
389			`end`
390			`always @(posedge clk_i)`
391			`if (strobe_i)`
392			`if (ack_o)`
393			`if (we_i)`
394			`$fdisplay(fspi, "%t [%h] <- write %h", $time, address_i, data_i);`
395			`else`
396			`$fdisplay(fspi, "%t [%h] -> read %h", $time, address_i, data_o);`
397			`// synopsys translate_on`
398
399			`endmodule`
400
401
402