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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [mmc_sd/] [RTL/] [spiMaster_defines.v] - Blame information for rev 17

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// ------------------------ spiMaster_defines.v ----------------------
// Version 0.0 - April 2008. Created
// Version 1.0 - 3rd June 2008. Fixed synchronisation issue between busClk and
//               spiSysClk. Fixed bug in bus accessible reset. Changed names of
//               fifo related modules to avoid conflict with other IP cores.
// Version 1.1 - 23rd August 2008. Modified reset synchronisation. Fixed bug
//               in wb_ack. Fixed file headers, and added description
// Version 1.2 - 25th October 2008. Modified readWriteSPIWireData to clock data
//               from the SPI bus on the rising edge of SCLK. This increases the
//               tsetup timing margin when reading SPI data. It turns out that the timing
//               was marginal for some SD cards when using a 24Mhz SPI clock.
//               Problem was exacerbated by the fact that the design prevents the 
//               final SPI interface Flipflops being pushed into the IO blocks.
 
`define SPI_MASTER_VERSION_NUM 8'h12
//`define SPI_SYS_CLK_48MHZ
`define SPI_SYS_CLK_30MHZ
//`define SPI_SYS_CLK_25MHZ
 
`define SIM_COMPILE
 
//memoryMap
`define CTRL_STS_REG_BASE 8'h00
`define RX_FIFO_BASE 8'h10
`define TX_FIFO_BASE 8'h20
`define ADDRESS_DECODE_MASK 8'hf0
`define SPI_MASTER_VERSION_REG 8'h00
`define SPI_MASTER_CONTROL_REG 8'h01
`define TRANS_TYPE_REG 8'h02
`define TRANS_CTRL_REG 8'h03
`define TRANS_STS_REG 8'h04
`define TRANS_ERROR_REG 8'h05
`define DIRECT_ACCESS_DATA_REG 8'h06
`define SD_ADDR_7_0_REG 8'h07
`define SD_ADDR_15_8_REG 8'h08
`define SD_ADDR_23_16_REG 8'h09
`define SD_ADDR_31_24_REG 8'h0a
`define SPI_CLK_DEL_REG 8'h0b
 
 
//FifoAddresses
`define FIFO_DATA_REG 3'b000
`define FIFO_STATUS_REG 3'b001
`define FIFO_DATA_COUNT_MSB 3'b010
`define FIFO_DATA_COUNT_LSB 3'b011
`define FIFO_CONTROL_REG 3'b100
 
 
`ifdef SIM_COMPILE
`define SLOW_SPI_CLK 8'h2
`define FAST_SPI_CLK 8'h00
`define TWO_MS 10'h001
`define TWO_FIFTY_MS 12'h001
`define ONE_HUNDRED_MS 12'h00c
`else //not SIM_COMPILE
 
`ifdef SPI_SYS_CLK_48MHZ
 
// --------------- spiSysClk = 48MHz
// if you change the clock frequency you will need to change these constants
 
// SLOW_SPI_CLK controls the SPI clock at start up.
// should be aiming for 400KHz
// SLOW_SPI_CLK = (spiSysClk / (400KHz * 2)) - 1
`define SLOW_SPI_CLK 8'h3b
// controls the SPI clock after init is complete.
// should be aiming for 24MHz ?
// controls the SPI clock after init is complete.
// should be aiming for 24MHz ?
// if spiSysClk >= 48MHz
// FAST_SPI_CLK = (spiSysClk / (24MHz * 2)) - 1
// else FAST_SPI_CLK = 0
`define FAST_SPI_CLK 8'h00
// TWO_MS = ((2mS * spiSysClk) / 256) - 1
`define TWO_MS 10'h177
// TWO_FIFTY_MS = ((250mS * spiSysClk) / 65536) - 1
`define TWO_FIFTY_MS 12'h0b6
// ONE_HUNDRED_MS = ((100mS * spiSysClk) / 65536) - 1
`define ONE_HUNDRED_MS 12'h048
 
`else //not SPI_SYS_CLK_48MHZ
 
`ifdef SPI_SYS_CLK_30MHZ
// --------------- spiSysClk = 30MHz
`define SLOW_SPI_CLK 8'h24
`define FAST_SPI_CLK 8'h00
`define TWO_MS 10'h0e9
`define TWO_FIFTY_MS 12'h071
`define ONE_HUNDRED_MS 12'h02c
 
`else
 
`ifdef SPI_SYS_CLK_25MHZ
// --------------- spiSysClk = 25MHz
`define SLOW_SPI_CLK 8'h1e
`define FAST_SPI_CLK 8'h00
`define TWO_MS 10'h0c2
`define TWO_FIFTY_MS 12'h060
`define ONE_HUNDRED_MS 12'h025
 
`endif //SPI_SYS_CLK_25MHZ
`endif //SPI_SYS_CLK_30MHZ
`endif //SPI_SYS_CLK_48MHZ
`endif //SIM_COMPILE
 
 
 
`ifdef SIM_COMPILE
`define SD_INIT_START_SEQ_LEN 8'h03
`define MAX_8_BIT 8'h08
`else
`define SD_INIT_START_SEQ_LEN 8'ha0
`define MAX_8_BIT 8'hff
`endif
 
 
`define WR_RESP_TOUT 12'hf00
 
`define NO_BLOCK_REQ 2'b00
`define WRITE_SD_BLOCK 2'b01
`define READ_SD_BLOCK 2'b10
 
`define READ_NO_ERROR 2'b00
`define READ_CMD_ERROR 2'b01
`define READ_TOKEN_ERROR 2'b10
 
`define WRITE_NO_ERROR 2'b00
`define WRITE_CMD_ERROR 2'b01
`define WRITE_DATA_ERROR 2'b10
`define WRITE_BUSY_ERROR 2'b11
 
 
`define TRANS_NOT_BUSY 1'b0
`define TRANS_BUSY 1'b1
 
`define TRANS_START 1'b1
`define TRANS_STOP 1'b0
 
`define DIRECT_ACCESS 2'b00
`define INIT_SD 2'b01
`define RW_READ_SD_BLOCK 2'b10
`define RW_WRITE_SD_BLOCK 2'b11
 
`define INIT_NO_ERROR 2'b00
`define INIT_CMD0_ERROR 2'b01
`define INIT_CMD1_ERROR 2'b10
 
`define TX_FIFO_DEPTH 512
`define TX_FIFO_ADDR_WIDTH 9
`define RX_FIFO_DEPTH 512
`define RX_FIFO_ADDR_WIDTH 9
 

Line No.	Rev	Author	Line
1	12	xianfeng	`// ------------------------ spiMaster_defines.v ----------------------`
2			`// Version 0.0 - April 2008. Created`
3			`// Version 1.0 - 3rd June 2008. Fixed synchronisation issue between busClk and`
4			`// spiSysClk. Fixed bug in bus accessible reset. Changed names of`
5			`// fifo related modules to avoid conflict with other IP cores.`
6			`// Version 1.1 - 23rd August 2008. Modified reset synchronisation. Fixed bug`
7			`// in wb_ack. Fixed file headers, and added description`
8			`// Version 1.2 - 25th October 2008. Modified readWriteSPIWireData to clock data`
9			`// from the SPI bus on the rising edge of SCLK. This increases the`
10			`// tsetup timing margin when reading SPI data. It turns out that the timing`
11			`// was marginal for some SD cards when using a 24Mhz SPI clock.`
12			`// Problem was exacerbated by the fact that the design prevents the`
13			`// final SPI interface Flipflops being pushed into the IO blocks.`
14
15			`define SPI_MASTER_VERSION_NUM 8'h12
16	17	xianfeng	//`define SPI_SYS_CLK_48MHZ
17			`define SPI_SYS_CLK_30MHZ
18	12	xianfeng	//`define SPI_SYS_CLK_25MHZ
19
20			`define SIM_COMPILE
21
22			`//memoryMap`
23			`define CTRL_STS_REG_BASE 8'h00
24			`define RX_FIFO_BASE 8'h10
25			`define TX_FIFO_BASE 8'h20
26			`define ADDRESS_DECODE_MASK 8'hf0
27			`define SPI_MASTER_VERSION_REG 8'h00
28			`define SPI_MASTER_CONTROL_REG 8'h01
29			`define TRANS_TYPE_REG 8'h02
30			`define TRANS_CTRL_REG 8'h03
31			`define TRANS_STS_REG 8'h04
32			`define TRANS_ERROR_REG 8'h05
33			`define DIRECT_ACCESS_DATA_REG 8'h06
34			`define SD_ADDR_7_0_REG 8'h07
35			`define SD_ADDR_15_8_REG 8'h08
36			`define SD_ADDR_23_16_REG 8'h09
37			`define SD_ADDR_31_24_REG 8'h0a
38			`define SPI_CLK_DEL_REG 8'h0b
39
40
41			`//FifoAddresses`
42			`define FIFO_DATA_REG 3'b000
43			`define FIFO_STATUS_REG 3'b001
44			`define FIFO_DATA_COUNT_MSB 3'b010
45			`define FIFO_DATA_COUNT_LSB 3'b011
46			`define FIFO_CONTROL_REG 3'b100
47
48
49			`ifdef SIM_COMPILE
50			`define SLOW_SPI_CLK 8'h2
51			`define FAST_SPI_CLK 8'h00
52			`define TWO_MS 10'h001
53			`define TWO_FIFTY_MS 12'h001
54			`define ONE_HUNDRED_MS 12'h00c
55			`else //not SIM_COMPILE
56
57			`ifdef SPI_SYS_CLK_48MHZ
58
59			`// --------------- spiSysClk = 48MHz`
60			`// if you change the clock frequency you will need to change these constants`
61
62			`// SLOW_SPI_CLK controls the SPI clock at start up.`
63			`// should be aiming for 400KHz`
64			`// SLOW_SPI_CLK = (spiSysClk / (400KHz * 2)) - 1`
65			`define SLOW_SPI_CLK 8'h3b
66			`// controls the SPI clock after init is complete.`
67			`// should be aiming for 24MHz ?`
68			`// controls the SPI clock after init is complete.`
69			`// should be aiming for 24MHz ?`
70			`// if spiSysClk >= 48MHz`
71			`// FAST_SPI_CLK = (spiSysClk / (24MHz * 2)) - 1`
72			`// else FAST_SPI_CLK = 0`
73			`define FAST_SPI_CLK 8'h00
74			`// TWO_MS = ((2mS * spiSysClk) / 256) - 1`
75			`define TWO_MS 10'h177
76			`// TWO_FIFTY_MS = ((250mS * spiSysClk) / 65536) - 1`
77			`define TWO_FIFTY_MS 12'h0b6
78			`// ONE_HUNDRED_MS = ((100mS * spiSysClk) / 65536) - 1`
79			`define ONE_HUNDRED_MS 12'h048
80
81			`else //not SPI_SYS_CLK_48MHZ
82
83			`ifdef SPI_SYS_CLK_30MHZ
84			`// --------------- spiSysClk = 30MHz`
85			`define SLOW_SPI_CLK 8'h24
86			`define FAST_SPI_CLK 8'h00
87			`define TWO_MS 10'h0e9
88			`define TWO_FIFTY_MS 12'h071
89			`define ONE_HUNDRED_MS 12'h02c
90
91			`else
92
93			`ifdef SPI_SYS_CLK_25MHZ
94			`// --------------- spiSysClk = 25MHz`
95			`define SLOW_SPI_CLK 8'h1e
96			`define FAST_SPI_CLK 8'h00
97			`define TWO_MS 10'h0c2
98			`define TWO_FIFTY_MS 12'h060
99			`define ONE_HUNDRED_MS 12'h025
100
101			`endif //SPI_SYS_CLK_25MHZ
102			`endif //SPI_SYS_CLK_30MHZ
103			`endif //SPI_SYS_CLK_48MHZ
104			`endif //SIM_COMPILE
105
106
107
108			`ifdef SIM_COMPILE
109			`define SD_INIT_START_SEQ_LEN 8'h03
110			`define MAX_8_BIT 8'h08
111			`else
112			`define SD_INIT_START_SEQ_LEN 8'ha0
113			`define MAX_8_BIT 8'hff
114			`endif
115
116
117			`define WR_RESP_TOUT 12'hf00
118
119			`define NO_BLOCK_REQ 2'b00
120			`define WRITE_SD_BLOCK 2'b01
121			`define READ_SD_BLOCK 2'b10
122
123			`define READ_NO_ERROR 2'b00
124			`define READ_CMD_ERROR 2'b01
125			`define READ_TOKEN_ERROR 2'b10
126
127			`define WRITE_NO_ERROR 2'b00
128			`define WRITE_CMD_ERROR 2'b01
129			`define WRITE_DATA_ERROR 2'b10
130			`define WRITE_BUSY_ERROR 2'b11
131
132
133			`define TRANS_NOT_BUSY 1'b0
134			`define TRANS_BUSY 1'b1
135
136			`define TRANS_START 1'b1
137			`define TRANS_STOP 1'b0
138
139			`define DIRECT_ACCESS 2'b00
140			`define INIT_SD 2'b01
141			`define RW_READ_SD_BLOCK 2'b10
142			`define RW_WRITE_SD_BLOCK 2'b11
143
144			`define INIT_NO_ERROR 2'b00
145			`define INIT_CMD0_ERROR 2'b01
146			`define INIT_CMD1_ERROR 2'b10
147
148			`define TX_FIFO_DEPTH 512
149			`define TX_FIFO_ADDR_WIDTH 9
150			`define RX_FIFO_DEPTH 512
151			`define RX_FIFO_ADDR_WIDTH 9
152

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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [mmc_sd/] [RTL/] [spiMaster_defines.v] - Blame information for rev 17