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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [mmc_sd/] [RTL/] [spiTxRxData.v] - Blame information for rev 12

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1 12 xianfeng 
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// spiTxRxData.v                                                ////
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////                                                              ////
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//// This file is part of the spiMaster opencores effort.
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//// <http://www.opencores.org/cores//>                           ////
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////                                                              ////
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//// Module Description:                                          ////
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////  Mux access to SPI RX and TX data
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////
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////
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////
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////                                                              ////
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//// To Do:                                                       ////
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////
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////                                                              ////
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//// Author(s):                                                   ////
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//// - Steve Fielding, sfielding@base2designs.com                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from <http://www.opencores.org/lgpl.shtml>                   ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//`include "timescale.v"
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module spiTxRxData (
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  clk,
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  rst,
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  tx1DataIn,
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  tx2DataIn,
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  tx3DataIn,
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  tx4DataIn,
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  tx1DataWEn,
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  tx2DataWEn,
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  tx3DataWEn,
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  tx4DataWEn,
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  txDataOut,
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  txDataFull,
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  txDataFullClr,
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  rx1DataRdyClr,
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  rx2DataRdyClr,
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  rx3DataRdyClr,
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  rx4DataRdyClr,
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  rxDataIn,
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  rxDataOut,
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  rxDataRdy,
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  rxDataRdySet
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);
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input clk;
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input rst;
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input [7:0] tx1DataIn;
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input [7:0] tx2DataIn;
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input [7:0] tx3DataIn;
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input [7:0] tx4DataIn;
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input tx1DataWEn;
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input tx2DataWEn;
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input tx3DataWEn;
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input tx4DataWEn;
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output [7:0] txDataOut;
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reg [7:0] txDataOut;
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output txDataFull;
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reg txDataFull;
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input txDataFullClr;
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input rx1DataRdyClr;
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input rx2DataRdyClr;
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input rx3DataRdyClr;
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input rx4DataRdyClr;
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input [7:0] rxDataIn;
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output [7:0] rxDataOut;
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reg [7:0] rxDataOut;
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output rxDataRdy;
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reg rxDataRdy;
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input rxDataRdySet;
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// --- Transmit control
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always @(posedge clk) begin
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  if (rst == 1'b1) begin
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    txDataOut <= 8'h00;
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    txDataFull <= 1'b0;
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  end
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  else begin
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    if (tx1DataWEn == 1'b1) begin
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      txDataOut <= tx1DataIn;
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      txDataFull <= 1'b1;
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    end
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    else if (tx2DataWEn == 1'b1) begin
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      txDataOut <= tx2DataIn;
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      txDataFull <= 1'b1;
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    end
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    else if (tx3DataWEn == 1'b1) begin
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      txDataOut <= tx3DataIn;
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      txDataFull <= 1'b1;
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    end
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    else if (tx4DataWEn == 1'b1) begin
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      txDataOut <= tx4DataIn;
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      txDataFull <= 1'b1;
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    end
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    if (txDataFullClr == 1'b1)
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      txDataFull <= 1'b0;
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  end
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end
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// --- Receive control
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always @(posedge clk) begin
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  if (rst == 1'b1) begin
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    rxDataOut <= 8'h00;
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    rxDataRdy <= 1'b0;
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  end
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  else begin
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    if (rx1DataRdyClr == 1'b1 || rx2DataRdyClr == 1'b1 || rx3DataRdyClr == 1'b1 || rx4DataRdyClr == 1'b1) begin
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      rxDataRdy <= 1'b0;
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    end
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    if (rxDataRdySet == 1'b1) begin
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      rxDataRdy <= 1'b1;
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      rxDataOut <= rxDataIn;
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    end
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  end
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end
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endmodule
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